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| june 2002 2975 stender way, santa clara, california 95054 telephone: (800) 345-7015 ? twx: 910-338-2070 ? fax: (408) 330-1748 printed in u.s.a. ?2001 integrated device technology, inc. idt79rc32334 and idt79RC32332 integrated communications processors (y revision) riscore? 32300 family user reference manual
general disclaimer integrated device technology, inc. reserves the right to make changes to its products or specifications at any time, without no tice, in order to improve design or performance and to supply the best possible product. id t does not assume any responsibility for us e of any circuitry described other than t he circuitry embodied in an idt product. the company makes no representations that circuitry described herein is free from pat ent infringement or other rights of third part ies which may result from its use. no license is granted by implication or otherwise under any patent, patent rights or other rights, of integrated device technology, inc. code disclaimer code examples provided by idt are for ill ustrative purposes only and should not be relied upon for developing applications. any use of the code examples below is completely at your own risk. idt makes no representations or warranties of any kind concerning the noninfringement, quality, safety or su itability of the code, either express or implied, including without limi tation any implied warranties of merchantability, fitness for a p articu- lar purpose, or non-infringement. further, idt makes no represen tations or warranties as to the truth, accuracy or completeness of any statements, information or materials concerning code exam ples contained in any idt publication or public disclosure or that is contained on any idt internet site. in no event will idt be liable for any direct, consequential, incidental, indirect, punitive or special damages, however they may arise, and even if idt has been previously advised about the possibility of such damages. th e code examples also may be subject to united stat es export control laws and may be subject to the export or import laws of other coun tries and it is your res ponsibility to comply with any applicable laws or regulations. life support policy integrated device technology's products are not authorized for us e as critical components in life support devices or systems un less a specific written agreement pertaining to such intended use is executed between t he manufacturer and an officer of idt. 1. life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) supp ort or sustain life and whose failure to perform, when properly used in accordance with instru ctions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any components of a life support device or system whose failure to per form can be reasonably expecte d to cause the failure of the life support device or system, or to affect its safety or effectiveness. the idt logo, dualsync, dualasnyc and zbt ar e registered trademarks of integrated device technology, inc. idt, qdr, riscontroll er, riscore, rc3041, rc3051, rc3052, rc3081, rc32134, rc32332, rc32334, rc32355, rc32364, rc36100, rc4700, rc 4640, rc64145, rc4650, rc5000, rc64474, rc64475, saram, smart zbt, supersync, swi tchstar, terasync,teraclock, are trademarks of integrated device technology, inc. powering what's next and enabling a digitally connected world are se rvice marks of integrated device technology, inc. q, qsi, s ynchroswitch and turboclock are regist ered trademarks of quality semiconduc- tor, a wholly-owned subsidiary of integrated device technology, inc. notes 79rc32334/332 user reference manual i june 4, 2002 about this manual introduction this user reference manual includes hardware and software info rmation on the rc32334 (y revision) 1 , a high performance integrated processor that comb ines a high performance 32-bit cpu core with system logic to provide direct connection to boot memory , main memory, i/o, and pc i. it also includes on-chip peripherals such as dma channels, reset ci rcuitry, interrupts, timers, and uarts. this is also the user reference manual for the rc 32332 (y revision) integrated processor. the informa- tion herein generally refers explicitly only to the rc32334 but is applicable to the rc32332 unless noted otherwise. differences bet ween the rc32334 and the rc32332 are identified in appendix g. additional information information not included in this manual such as me chanicals, package pin-outs, and electrical character- istics can be found in the data sheet for this devic e, which is available from the idt website (www.idt.com) as well as through your loca l idt sales representative. content summary chapter 1, ?rc32334 device overview,? provides a complete introd uction to the performance capabil- ities of the rc32334. included in this chapter is a summa ry of features for the device as well as a system block diagram and inter nal register maps. chapter 2, ?rc32300 cpu core,? describes the features of the rc32300 cpu core. chapter 3, ?cpu instruction set overview,? presents a general overview on the three cpu instruc- tion formats as well as the comput ational instructions of the mips ar chitecture. instruction set summary tables are also provided. chapter 4, ?cpu pipeline architecture,? discusses pipeline features as well as interlock and excep- tion handling of the device?s riscore? 32300. chapter 5, ?memory management,? contains a discussion on the vi rtual-to-physical address transla- tion technique, tlb management, and operation modes for the rc32334. register formats and field description tables are also provided in this chapter. chapter 6, ?cpu exception processing,? defines and describes the various exception types and handling processes for the rc32334. also provided in this chapter are the cpo regist er formats, their field descriptions, and general exc eption handling flowcharts. chapter 7, ?cache organization, operation, and coherency,? includes a general discussion on the operation of cache as well as the more specific ca che attributes of the rc3 2334. flowcharts and various diagrams are provided to clarify the concepts discussed in this chapter. chapter 8, ?rc32334 internal bus,? presents a general overview of the rc32334?s internal bus that provides a connection to inter nal peripherals and controllers. chapter 9, ?external local bus interface,? presents a general overview of the rc32334?s system bus that provides an easy connection to main memory and to peripherals. chapter 10, ?memory controller,? provides a functional overview on the cpu core, dma or pci bridge generated transactions. a block diagram , register maps, signal descripti on table, and timing diagrams for various read and write oper ations are also included. 1. for information on an earlier user manual that covers the z revision, contact your idt sales representative. about this manual content summary 79rc32334/332 user reference manual ii june 4, 2002 notes chapter 11, ?synchronous dram controller,? contains a discussion on the operations and support provided by the rc32334?s 32-bit sdram controller. ti ming diagrams are provided to illustrate the different read and write transactions. chapter 12, ?pci interface controller,? contains descriptions of the pci host/satellite modes and master/target operations supported in the rc32334. r egister maps and register field definitions are included. chapter 13, ?dma controllers,? includes descriptions on the f our general purpose dma channels and the transfer operations supported. byte swapping between big- and li ttle-endian is also discussed and includes examples. chapter 14, ?expansion interrupt controller,? provides a functional and operational overview on this controller. this chapter includes a block diagram, si gnal definitions and register mapping tables for each of the 14 groups supported. chapter 15, ?programmable i/o (pio) controller,? provides the signal descr iptions, register mapping and programming information on the software programmable options of the rc32334?s 15 peripheral pins. chapter 16, ?timer controller,? provides a user overview on t he functions of the rc32334?s nine on- chip timers. a block diagram, signal defin itions and register maps are included. chapter 17, ?uart controller,? describes the operation of the tw o 16550 compatible uarts available on the rc32334. register maps and descriptions are included. chapter 18, ?serial peripheral interface,? describes the properties and operations of this interface to low-cost serial peripherals. chapter 19, ?clocking, r eset, and initialization,? provides a description of the clock signals that are used on the rc32334 processor and includes a discussi on on the basic system clocks and system timing parameters. this chapter also pr ovides a brief explanation on the pow er reduction modes for this device and a description of the rc32334 initialization and reset registers. chapter 20, ?jtag boundary scan,? introduces the standard jtag interface used for board-level debugging. a description on the test access port (t ap) interface and tap controller state assignments is also included. chapter 21, ?ejtag (in-circuit emulator) interface,? describes the debug support unit (dsu). it covers the debug instructions added to the mips ii isa instruction set as well as support functions and registers for debugging. appendix a, ?rc32300 cpu core enhancements to mips ii isa,? discusses in detail architectural enhancements to the mips ii isa. appendix b, ?opcode map,? provides an opcode map. appendix c, ?the timing of cache operations,? provides a table for pr imary data cache operations and a table for primary instruction cache operat ions, as well as caveats about cache operations. appendix d, ?rc32334/rc32332 standby mode operation,? discusses power reduction, in partic- ular, the ?wait? instruction and the standby mode that follows this instruction. appendix e, ?coprocessor 0 hazards,? identifies the rc32334 cp0 hazards. appendix f, ?integer multiply scheduling,? discusses integer multiply performance, defines instruc- tions, and summarizes integer multiply and divide performance. appendix g, ?rc32332 differences,? identifies the differences between the rc32334 and the rc32332. about this manual revision history 79rc32334/332 user reference manual iii june 4, 2002 notes revision history november 15, 2000 : initial publication. february 5, 2001 : in chapter 12, separated pci cpu memory and i/o space 1 base register section into two sections, one dealing with cpu memory and the other with cpu i/o, and changed bit description to reflect cpu i/o base uses [23:20] instead of [31:28]. february 26, 2001 : changed alternate function for uart_tx[0] from pio[3] to pio[1] in table 1.2 and g.4. in chapter 15, clarified that timer_tc_n[0] is no t present in the rc32332 and added a reference in the signal definitions section to tables g.2 and g.3. in appendi x g, added two tables (g.2 and g.3) to highlight the differences in pio pin name assignments between the rc32334 and rc32332. april 2, 2001 : made the following changes in chapter 18: added system clock formula under serial peripheral clock register section; removed ?active? from description for bit 2 in table 18.4; changed spse register to spsr register in table 18.6; in master programming example, item 1, changed formula in paren- theses to 3.7 mhz (67/ [(8+1) * 2]); in master programming example, item 2, changed formula in paren- theses to 3.7 / 2 = 1.85 mhz. may 17, 2001 : table 17.6, ?interrupt identity register fields and descriptions,? has been revised to show that for bits 3:1 (current interrupt field) the value 111 has the same status and priority level as the value 011. also, in table 11.2, under sdram organization column, 2nd category from the bottom, the data now reads ?2 mb x 16 x 4 banks? instead of ?4 mb x 16 x 4 banks.? finally, in table 11.6, for bit 28 (sdram bank size field), the value descrip tions now omit any reference to 16m-bit and 64m-bit. these references were confusing because the rc32334 and rc32332 devices also support 128m-bit sdrams. july 26, 2001 : in chapter 10, the bit address for me m_addr[25:2] was changed from 40000 to 3c00000 in figures 10.6 through 10.30. june 4, 2002 : made the following changes based on the introd uction of y silicon: chapter 8, internal bus?changes in bit 7 description in table 8.12, changes in table 8.13. chapter 11, sdram controller? added more sdram address multiplexing and control registers (sdram sec ondary control), changes to tables 11.1 and 11.2, changes in sdram initializa tion section. chapter 12, pci interface?added cpu to pci and pci to cpu mapping diagrams, new memory /io space base register and pci memory/io base address registers, target fifo s are 16 words deep, added pci target control register and new feature sections, added additional fields in pci arbitration register (table 12.15), added 2 new base address regis- ters, revised tables 12.1, 12.7, and 12.12, changed re set for system identification number from 00h to 01h (table 12.24). chapter 13, dma controller s?added new feature configuration register, added sdram to pci arbitration algorithm field, and revised function description for interrupt_n[3] and n[4] pins in table 13.3. pio chapter?added new feature register. clocking, reset and initialization chapter?revised description in first row of table 19.1. about this manual revision history 79rc32334/332 user reference manual iv june 4, 2002 notes notes 79rc32334/332 user reference manual v june 4, 2002 table of contents about this manual introduction .......................................................................................................................... i content summary ................................................................................................................. i revision history .................................................................................................................. iii 1 rc32334 device overview foreword....................................................................................................................... ...............1-1 introduction ................................................................................................................... ...............1-1 block diagram .................................................................................................................. ...........1-1 documentation conventions and definitions .....................................................................1-1 signal terminology ............................................................................................................. 1-2 list of features ............................................................................................................... .............1-3 system block diagram ........................................................................................................... .....1-4 system overview................................................................................................................ .........1-4 pin description table ? rc32334 .............................................................................................1- 6 pin description table ? rc32332 ............................................................................................1-13 logic diagram ? rc32334.......................................................................................................1 -19 logic diagram ? rc32332.......................................................................................................1 -20 typical rc32334 memory map .................................................................................................1-21 rc32334 internal register map addresses and definitions .................................................................................................................... ..............1-21 biu control registers.......................................................................................................1-2 1 base address and base mask registers .........................................................................1-22 memory control registers................................................................................................1-23 dram memory controller registers ................................................................................1-23 expansion interrupt registers ..........................................................................................1-23 programmable i/o registers............................................................................................1-25 timer controller registers ...............................................................................................1-25 uart control registers...................................................................................................1-26 serial peripheral interface registers................................................................................1-27 dma control registers.....................................................................................................1-27 pci interface control registers........................................................................................1-29 2 rc32300 cpu core introduction ................................................................................................................... ...............2-1 performance overview ........................................................................................................... .....2-1 rc32300 cpu core features .....................................................................................................2 -1 rc32300 cpu overview ........................................................................................................... ..2-2 cpu registers.................................................................................................................. ..2-2 configuration .................................................................................................................. ....2-3 cp0 considerations............................................................................................................. ........2-4 table of contents 79rc32334/332 user reference manual vi june 4, 2002 notes memory management unit (mmu) ..............................................................................................2-4 on-chip instruction and data caches..........................................................................................2- 4 power reduction mode ........................................................................................................... ....2-4 standby mode operation ...................................................................................................2-4 3 cpu instruction set overview introduction ................................................................................................................... ...............3-1 cpu instruction formats ........................................................................................................ .....3-1 load and store instructions (i-type) ........................................................................................... .3-2 scheduling a load delay slot ............................................................................................3-2 defining access types.......................................................................................................3-2 computational instructions (r-type and i-type) ...........................................................................3-3 operations with 32-bit operands .......................................................................................3-3 cycle timing for multiply and divide instructions...............................................................3-3 jump & branch instructions (j-type and r-type) .........................................................................3-3 overview of jump instructions ...........................................................................................3-3 overview of branch instructions ........................................................................................3-4 special instructions (r-type).................................................................................................. ......3-4 exception instructions......................................................................................................... .........3-4 coprocessor instructions (i-type).............................................................................................. ...3-4 summary of cpu supported instruction sets .............................................................................3-4 4 cpu pipeline architecture introduction ................................................................................................................... ...............4-1 cpu pipeline stages ............................................................................................................ .......4-1 1i - instruction fetch, phase one ......................................................................................4-2 2i - instruction fetch, phase two.......................................................................................4-2 1r - register fetch, phase one ........................................................................................4-2 2r - register fetch, phase two ........................................................................................4-2 1a - execution, phase one................................................................................................4-2 2a - execution, phase two ................................................................................................4-2 1d - data fetch, phase one..............................................................................................4-2 2d - data fetch, phase two ..............................................................................................4-3 1w - write back, phase one .............................................................................................4-3 2w - write back, phase two..............................................................................................4-3 branch delay ................................................................................................................... ............4-3 load delay..................................................................................................................... ..............4-4 interlock and exception handling ............................................................................................... .4-4 exception conditions .........................................................................................................4- 5 stall conditions ............................................................................................................... ...4-5 slip conditions ................................................................................................................ ...4-6 5 memory management introduction ................................................................................................................... ...............5-1 virtual-to-physical address translation .......................................................................................5 -1 tlb management ................................................................................................................. .......5-2 table of contents 79rc32334/332 user reference manual vii june 4, 2002 notes mmu register descriptions ...................................................................................................... ...5-3 index register (0)............................................................................................................. ..5-3 random register (1)..........................................................................................................5- 4 entrylo0 (2), and entrylo1 (3) registers...........................................................................5-4 context register (4) ........................................................................................................... 5-5 pagemask register (5) ......................................................................................................5-6 wired register (6) ............................................................................................................. .5-6 bad virtual address register (badvaddr) (8) ....................................................................5-7 entryhi register (10).......................................................................................................... 5-8 kernel/user operating modes and addressing ...........................................................................5-8 user mode...................................................................................................................... ....5-8 kernel mode.................................................................................................................... ...5-9 6 cpu exception processing introduction ................................................................................................................... ...............6-1 exception processing registers ................................................................................................. .6-1 count register (9)............................................................................................................. .6-2 compare register (11) .......................................................................................................6-3 status register (12) ........................................................................................................... 6-3 status register modes and access states ........................................................................6-5 cause register (13) ...........................................................................................................6 -5 exception program counter (epc) register (14) ..............................................................6-7 processor revision identifier (p rid) register (15) ............................................................6-7 config register (16) ........................................................................................................... 6-8 iwatch register (18) ..........................................................................................................6 -9 dwatch register (19).........................................................................................................6- 9 debug exception program counter (d ebugepc) register (23) ......................................6-10 debug register (24).........................................................................................................6-1 0 error checking and correcting (ecc) register (26)........................................................6-10 cache error (cacheerr) r egister (27)..............................................................................6-10 taglo register (28).......................................................................................................... 6- 11 error exception program counter (e rror epc) register (30) ..........................................6-12 processor exceptions ........................................................................................................... .....6-12 exception types...............................................................................................................6 -12 general exception process..............................................................................................6-13 priority of exceptions .......................................................................................................6- 13 exception vector locations..............................................................................................6-13 reset exception ...............................................................................................................6 -14 debug exception..............................................................................................................6- 15 soft reset exception........................................................................................................6-1 5 nonmaskable interrupt (nmi) exception ..........................................................................6-16 address error exception ..................................................................................................6-16 tlb exceptions................................................................................................................. .........6-17 tlb refill exception.........................................................................................................6- 17 tlb invalid exception ......................................................................................................6-18 tlb modified exception ...................................................................................................6-18 cache error exception .....................................................................................................6-18 bus error exception .........................................................................................................6-1 9 integer overflow exception ..............................................................................................6-19 trap exception ................................................................................................................. 6-20 table of contents 79rc32334/332 user reference manual viii june 4, 2002 notes system call exception .....................................................................................................6-20 breakpoint exception .......................................................................................................6-20 reserved instruction exception .......................................................................................6-21 coprocessor unusable exception....................................................................................6-21 interrupt exception ...........................................................................................................6 -21 dwatch exception............................................................................................................6-2 2 iwatch exception .............................................................................................................6- 22 exception handling and servicing flowcharts .................................................................6-22 7 cache organization, operation, and coherency introduction ................................................................................................................... ...............7-1 cache operation overview ................................................................................................7-1 rc32334 cache description ...................................................................................................... .7-2 rc32334 cache attributes ................................................................................................7-2 cache organization and accessibility .........................................................................................7- 2 organization of the primary instruction cache (i-cache)...................................................7-2 organization of the primary da ta cache (d-cache)..........................................................7-3 accessing the primary caches................................................................................................... .7-5 primary cache states........................................................................................................... .......7-6 primary cache states ........................................................................................................7-6 cache line ownership ........................................................................................................... .....7-6 cache write policy ............................................................................................................. .........7-7 store buffer ................................................................................................................... .....7-7 cache replacement policy....................................................................................................... ...7-7 cache initialization........................................................................................................... ............7-8 cache locking .................................................................................................................. ...........7-8 when to use cache locking ..............................................................................................7-8 example: data cache locking...........................................................................................7-8 example: instruction cache locking..................................................................................7-9 8 rc32334 internal bus introduction ................................................................................................................... ...............8-1 list of features for rc32300 cpu bus.......................................................................................8-1 block diagram .................................................................................................................. ...........8-1 functional overview ............................................................................................................ ........8-2 address module................................................................................................................. ..........8-2 address incrementer..........................................................................................................8- 2 address mux .................................................................................................................... .8-2 address decode................................................................................................................. 8-3 data module .................................................................................................................... ............8-3 cpu read/write operations...................................................................................................... ..8-3 dma read/write operations ...................................................................................................... .8-4 arbitration.................................................................................................................... .......8-4 memory port sizing ............................................................................................................. ........8-4 bus turnaround (bta) register.................................................................................................. .8-4 watchdog timer................................................................................................................. ..........8-5 table of contents 79rc32334/332 user reference manual ix june 4, 2002 notes bus time-out counters .......................................................................................................... .....8-5 bus error timers............................................................................................................... ...........8-5 register descriptions.......................................................................................................... .........8-5 interface control registers .................................................................................................... ......8-6 cpu port-width control register: virtual address 0xffff_e200 ....................................8-6 cpu bus turnaround (bta) control regist er: virtual address 0xffff_e204..................8-8 cpu bus error address register (read on ly): virtual address 0xffff_e208 ................8-9 bta control register..........................................................................................................8 -9 address latch timing register.................................................................................................. 8-11 arbitration register ..........................................................................................................8 -12 buserror control register ................................................................................................8-12 buserror address register ..............................................................................................8-12 sysid register ................................................................................................................. 8-14 9 external local bus interface introduction ................................................................................................................... ...............9-1 operation ...................................................................................................................... ...............9-1 variable port-width interface.................................................................................................. .....9-2 debug signals ................................................................................................................. ...........9-4 10 memory controller introduction ................................................................................................................... .............10-1 list of features ............................................................................................................... ...........10-1 block diagram .................................................................................................................. .........10-1 functional overview ............................................................................................................ ......10-2 memory controller operation .................................................................................................... 10-2 integrated processor generated transactions ................................................................10-2 dma controller or pci bridge generated transactions...................................................10-2 chip selects ................................................................................................................... ..10-3 transceiver control interface ...........................................................................................10-3 using 8- or 16-bit boot proms .................................................................................................1 0-3 wait-state generator (wsg)..................................................................................................... 10-4 address decoding ............................................................................................................... ......10-4 memory type and port-width size support ..............................................................................10-5 port-width size................................................................................................................ ..........10-6 i/o width support.............................................................................................................1 0-7 programmable wait-state generator ........................................................................................10-7 external wait-state behavior ...........................................................................................10-7 bus error recovery ............................................................................................................. ......10-8 signal descriptions ............................................................................................................ ........10-8 register definitions.......................................................................................................... .........10-9 memory msb base address register for banks 1:0......................................................10-10 memory msb bank mask registers for banks 1:0 ........................................................10-10 memory control register for banks 5:0 ......................................................................... 10-11 timing diagrams................................................................................................................ ......10-12 table of contents 79rc32334/332 user reference manual x june 4, 2002 notes 11 synchronous dram controller introduction ................................................................................................................... ............. 11-1 features....................................................................................................................... .............. 11-1 sdram enhancements in y silicon revision.................................................................. 11-1 block diagram .................................................................................................................. ......... 11-3 functional overview ............................................................................................................ ...... 11-3 base address decoding................................................................................................... 11-7 page row comparators................................................................................................... 11-7 burst support .................................................................................................................. .11-7 ras/cas address mux .................................................................................................. 11-8 refresh timer.................................................................................................................. .11-8 error recovery ................................................................................................................. 11-8 sdram initialization ........................................................................................................... ....... 11-8 register definitions........................................................................................................... ......... 11-9 sdram control registers ....................................................................................................... 1 1-10 sdram primary control register.................................................................................. 11-10 sdram secondary control register ............................................................................. 11-13 timing diagrams................................................................................................................ ...... 11-15 sodimm ......................................................................................................................... ......... 11-21 sodimm configuration .................................................................................................. 11-21 sdram sodimm even bank non-page word read.................................................... 11-21 sdram sodimm odd bank non-page word read ..................................................... 11-22 sdram sodimm refresh............................................................................................. 11-23 output_clk usage ........................................................................................................... 11-2 3 12 pci interface controller introduction ................................................................................................................... .............12-1 features....................................................................................................................... ..............12-1 pci interface enhancements in y silicon revision..........................................................12-1 functional overview ............................................................................................................ ......12-3 memory mapping .............................................................................................................12-4 rc32334 pci bus target operation ................................................................................12-5 rc32334 pci bus master operation ...............................................................................12-6 rc32334 pci bus target operation ................................................................................12-7 pci satellite mode ...........................................................................................................12 -7 pci commands supported ..............................................................................................12-9 pci configuration regi ster access................................................................................12-10 pci polling error handling ............................................................................................. 12-11 pci interrupts ................................................................................................................. 12-11 signal definitions ............................................................................................................. ........ 12-11 register definitions........................................................................................................... .......12-12 pci controller interrupt pending register 11 .................................................................12-13 cpu to pci mailbox interrupt pending register 12 .......................................................12-13 pci to cpu mailbox interrupt pending register 13 .......................................................12-14 pci memory space [1,2,3] base register......................................................................12-14 pci i/o base register....................................................................................................12-15 new feature register ....................................................................................................12-16 table of contents 79rc32334/332 user reference manual xi june 4, 2002 notes pci target control register ...........................................................................................12-17 pci arbitration register .................................................................................................12-21 pci to cpu memory/io space [1,2,3,4] base registers ...............................................12-22 pci configuration address register ..............................................................................12-24 pci configuration data register....................................................................................12-24 rc32334 pci configuration registers ....................................................................................12-24 vendor id register.........................................................................................................12-2 5 device id register .........................................................................................................12-2 6 pci command register .................................................................................................12-26 pci status register........................................................................................................12-2 7 device revision identification register..........................................................................12-27 class code register ......................................................................................................12-28 cacheline size ...............................................................................................................12 -28 master latency timer register ......................................................................................12-29 header type...................................................................................................................1 2-29 bist ........................................................................................................................... ....12-29 pci memory/io base address [1,2,3,4] registers.........................................................12-30 subsystem vendor id ....................................................................................................12-32 subsystem id.................................................................................................................12 -32 interrupt line register....................................................................................................12-3 2 interrupt pin register .....................................................................................................12-3 2 min_gnt register.........................................................................................................12-33 max_lat register.........................................................................................................12-33 trdy timeout value......................................................................................................12-33 retry timeout value.......................................................................................................12-34 13 dma controllers introduction ................................................................................................................... .............13-1 list of features ............................................................................................................... ...........13-1 dma enhancements in y silicon revision.......................................................................13-1 block diagram .................................................................................................................. .........13-3 dma operations ................................................................................................................. .......13-3 endianness swapping......................................................................................................13-4 dma transfer modes............................................................................................................. ....13-4 dma transfer operations ................................................................................................13-5 last partial word transfers..............................................................................................13-7 transfer restrictions ........................................................................................................13 -7 dma arbitration methods........................................................................................................ ...13-7 dma access..................................................................................................................... 13-9 signal definitions ............................................................................................................. ..........13-9 dma ready...................................................................................................................... 13-9 dma done......................................................................................................................1 3-10 internal dma interrupt signals ....................................................................................... 13-11 restarting dma channels..............................................................................................13-12 register mapping and descriptions.........................................................................................13-12 configuration register ......................................................................................................... ....13-14 base descriptor address register...........................................................................................13-1 6 dma example ................................................................................................................13-1 7 current address register ....................................................................................................... .13-19 table of contents 79rc32334/332 user reference manual xii june 4, 2002 notes source address register........................................................................................................ .13-19 destination address register ..................................................................................................1 3-19 next descriptor addr ess register ...........................................................................................13-2 0 status register ................................................................................................................ ........13-20 timing diagrams................................................................................................................ ......13-22 14 expansion interrupt controller introduction ................................................................................................................... .............14-1 features....................................................................................................................... ..............14-1 block diagram .................................................................................................................. .........14-1 operational overview ........................................................................................................... .....14-2 signal definitions ............................................................................................................. ..........14-2 registers and address mapping................................................................................................14 -3 interrupt pending register..................................................................................................... ....14-6 interrupt mask register ........................................................................................................ .....14-6 interrupt clear register ....................................................................................................... ......14-6 register group settings ........................................................................................................ ....14-7 register group 0 settings................................................................................................14-7 register group 1 settings................................................................................................14-7 register group 2 settings................................................................................................14-7 register group 3 settings................................................................................................14-8 register group 4 settings................................................................................................14-8 register group 5 settings................................................................................................14-8 register group 6 settings................................................................................................14-8 register group 7 settings................................................................................................14-9 register group 8 settings................................................................................................14-9 register group 9 settings................................................................................................14-9 register group 10 settings..............................................................................................14-9 register group 11 settings ..............................................................................................14-9 register group 12 settings............................................................................................14-10 register group 13 settings............................................................................................14-10 register group 14 settings............................................................................................ 14-11 timing diagrams................................................................................................................ ...... 14-11 rc32334 interrupt flow......................................................................................................... ..14-13 1. initialize interrupts ......................................................................................................1 4-13 2. wait for interrupt.........................................................................................................1 4-13 3. software interrupt service routine (isr)...................................................................14-13 optional algorithm for priority interrupts ........................................................................14-13 optional algorithm for non-pr ioritized interrupts............................................................14-13 15 programmable i/o (pio) controller introduction ................................................................................................................... .............15-1 features....................................................................................................................... ..............15-1 overview....................................................................................................................... .............15-1 block diagram .................................................................................................................. .........15-2 table of contents 79rc32334/332 user reference manual xiii june 4, 2002 notes performing initialization programming.......................................................................................15- 3 signal definitions ............................................................................................................. ..........15-3 register mapping and definitions..............................................................................................1 5-5 pio data register 0 .........................................................................................................15- 5 pio data register 1 .........................................................................................................15- 6 pio direction register 0 ..................................................................................................15-7 pio direction register 1 ..................................................................................................15-8 pio function select register 0........................................................................................15-9 pio function select register 1......................................................................................15-10 new feature register .................................................................................................... 15-11 timing diagrams................................................................................................................ ......15-12 16 timer controller introduction ................................................................................................................... .............16-1 features....................................................................................................................... ..............16-1 block diagram .................................................................................................................. .........16-1 overview....................................................................................................................... .............16-2 signal definitions ............................................................................................................. ..........16-3 register mapping............................................................................................................... ........16-3 timer control register description ..................................................................................16-4 timer count register .......................................................................................................16-5 timer compare register ..................................................................................................16-5 timing diagrams................................................................................................................ ........16-6 17 uart controller introduction ................................................................................................................... .............17-1 block diagram .................................................................................................................. .........17-1 overview....................................................................................................................... .............17-2 uart operation...............................................................................................................17 -3 user interrupts ................................................................................................................ ...........17-3 signal definitions ............................................................................................................. ..........17-3 uart 0&1 registers ........................................................................................................17-4 uart 0 registers ............................................................................................................17- 4 uart 1 registers ............................................................................................................17- 4 receive buffer register (rbr) ........................................................................................17-5 transmit buffer register (tbr)........................................................................................17-5 interrupt enable register (ier)........................................................................................17-5 divisor latch least register (dll) ..................................................................................17-6 divisor latch most register (dlm) ..................................................................................17-6 interrupt identity register (iir).........................................................................................17-6 buffer control register (bcr)..........................................................................................17-8 line control register (lcr).............................................................................................17-9 modem control register (mcr).......................................................................................17-9 line status register (lsr) ............................................................................................17-10 modem status register (msr) ...................................................................................... 17-11 scratch register (scr)..................................................................................................17-12 reset register (rr).......................................................................................................17-12 timing diagram ................................................................................................................. ......17-12 table of contents 79rc32334/332 user reference manual xiv june 4, 2002 notes 18 serial peripheral interface introduction ................................................................................................................... .............18-1 signal descriptions ............................................................................................................ ........18-2 spi data setup/hold and delay timing ...........................................................................18-3 spi setup and register descriptions ........................................................................................18-3 spi interrupt description ..................................................................................................18-4 serial peripheral clock r egister (spcnt).......................................................................18-4 serial peripheral control register (spcntl) ..................................................................18-5 serial peripheral status register (spsr)........................................................................18-6 serial peripheral data i/o register (spdr).....................................................................18-7 interface to spi serial e2proms by atmel (at25128) .................................................18-8 master programming example ..................................................................................................18- 8 timing diagrams................................................................................................................ ........18-8 19 clocking, reset, and initialization introduction ................................................................................................................... .............19-1 signal terminology ............................................................................................................. .......19-1 basic system clocks ............................................................................................................ .....19-1 cpu_masterclk .................................................................................................................1 9-1 pclock......................................................................................................................... .....19-2 phase-locked loop (pll) operation ........................................................................................19-2 pll components and operation......................................................................................19-2 pll analog power filtering ..................................................................................................... ..19-3 reset function................................................................................................................. ..........19-3 reset and initialization interface ......................................................................................19-4 boot-mode configuration settings ...................................................................................19-4 reset_boot_mode settings ...............................................................................................19-5 pci_host_mode settings...................................................................................................19-5 reset of on-chip system controller logic .......................................................................19-5 20 jtag boundary scan introduction ................................................................................................................... .............20-1 system logic tap controll er overview.....................................................................................20-2 signal definitions ............................................................................................................. ..........20-2 test data register (dr)........................................................................................................ .....20-3 boundary scan registers ................................................................................................20-3 instruction register (ir)...................................................................................................... .......20-5 extest ......................................................................................................................... ......20-6 sample/preload................................................................................................................2 0-6 bypass ......................................................................................................................... ....20-6 clamp.......................................................................................................................... .....20-7 deviceid....................................................................................................................... ....20-7 validate....................................................................................................................... ......20-7 reserved....................................................................................................................... ...20-8 unused......................................................................................................................... ....20-8 usage considerations ........................................................................................................... ....20-8 table of contents 79rc32334/332 user reference manual xv june 4, 2002 notes 21 ejtag (in-circuit emulator) interface introduction ................................................................................................................... .............21-1 overview....................................................................................................................... .............21-2 block diagrams................................................................................................................. .........21-3 debug support unit ............................................................................................................. ......21-3 instruction address match logic ......................................................................................21-4 data address & data value match logic .........................................................................21-4 processor address bus & processo r data bus match logic...........................................21-4 ejtag interface ................................................................................................................ ........21-4 operating modes..............................................................................................................21 -5 jtag operation ................................................................................................................. ........21-7 test interface and boundary-scan architecture...............................................................21-7 test access port operation..............................................................................................21-7 tap controller state assignments ...................................................................................21-9 instruction register (ir) .................................................................................................21-10 test data register (dr) .................................................................................................21-10 implementation register ................................................................................................ 21-11 processor access ..........................................................................................................21-17 reset overview..............................................................................................................21- 18 ejtag module clocking ................................................................................................21-19 instruction register ........................................................................................................21- 19 the debug unit ..............................................................................................................21- 21 extended instructions .......................................................................................................... ....21-21 sdbbp (software debug breakpoint)............................................................................21-21 deret (debug exception return).................................................................................21-22 extended cp0 registers (debug registers) ...........................................................................21-22 debug register ..............................................................................................................21- 22 debug exception program counter register (depc)....................................................21-24 debug exception save register (desave)...................................................................21-25 register map ................................................................................................................... ........21-25 debug control register..................................................................................................21-25 instruction address match registers..............................................................................21-27 data address and data ma tch registers ........................................................................21-28 processor bus match registers.....................................................................................21-29 debug exception ................................................................................................................ .....21-32 debug exception causes...............................................................................................21-32 debug exception enabling/disabling .............................................................................21-32 debug exception handling.............................................................................................21-32 exception handling when in debug mode (dm bit is set) ..............................................21-33 servicing the debug exception ......................................................................................21-33 pc trace....................................................................................................................... ...........21-33 instruction trace method ....................................................................................................... ..21-34 pc status and exception vector encoding..............................................................................21-34 pc status encoding .......................................................................................................21-34 exception vector encoding ............................................................................................21-35 external interface definition.................................................................................................. ...21-36 ejtag .......................................................................................................................... ..21-36 priority of target address output (ejtag_tpc)...........................................................................21-36 table of contents 79rc32334/332 user reference manual xvi june 4, 2002 notes real time ejtag_tpc output (tm=?0? in dcr[0]).............................................................21-36 non-real time ejtag_tpc output (tm=?1? in dcr[0]).....................................................21-37 examples of pc trace output .................................................................................................21- 37 conditional pc relative jump instruction......................................................................21-37 indirect jump instruction ................................................................................................21-37 pc trace of an exception followed by a jump indirect instruction .............................21-38 pc trace of an indirect instruction followed by an exception.......................................21-38 examples of trace trigger output...........................................................................................21-3 9 instruction address trace trigger ..................................................................................21-39 trace trigger and general exception at the same time ...............................................21-39 jump indirect causes trace trigger ..............................................................................21-39 instruction after jump indirect causes trace trigger ....................................................21-40 switching from real-time trace to debug ..............................................................................21-40 real-time trace mode to debug mode (no ejtag_tpc output)......................................21-40 real-time trace mode to debug mode .........................................................................21-41 pin out of the standard ejtag...............................................................................................21- 41 ejtag application information................................................................................................21 -42 using jtag boundary scan and ejtag .......................................................................21-42 hot plug-in of the ejtag probe to target system ........................................................21-43 appendix a rc32300 cpu core enhancements to mips ii isa introduction ................................................................................................................... .............. a-1 prefetch (pref) ................................................................................................................ ......... a-1 elimination of 64-bit instructions ............................................................................................. .... a-3 conditional move operations .................................................................................................... .a-3 move conditional on not zero .......................................................................................... a-3 move conditional on zero ................................................................................................. a-3 instructions for dsp support ................................................................................................... ... a-3 multiply add................................................................................................................... .... a-4 multiply add unsigned ...................................................................................................... a-4 multiply subtract ............................................................................................................. .. a-4 multiply subtract unsigned ............................................................................................... a-5 count leading zeros......................................................................................................... a-5 count leading ones ......................................................................................................... a-6 appendix b opcode map appendix c the timing of cache operations introduction ................................................................................................................... .............. c-1 caveats about cache operations .............................................................................................. c-1 cache operations tables ........................................................................................................ ... c-1 fill_i equation definitions .................................................................................................... ....... c-3 appendix d rc32334/rc32332 standby mode operation introduction ................................................................................................................... .............. d-1 table of contents 79rc32334/332 user reference manual xvii june 4, 2002 notes power management............................................................................................................... ..... d-1 power reduction modes ................................................................................................... d-1 entering standby mode .......................................................................................................... .... d-1 appendix e coprocessor 0 hazards introduction ................................................................................................................... .............. e-1 list of hazards ................................................................................................................ .. e-1 appendix f integer multiply scheduling introduction ................................................................................................................... ...............f-1 appendix g rc32332 differences introduction ................................................................................................................... .............. g-1 differences in features........................................................................................................ ....... g-1 memory controller............................................................................................................. g -1 pci controller on-chip arbiter........................................................................................... g-1 pci controller device id ................................................................................................... g-1 dma controller flow control............................................................................................. g-2 pio controller signals....................................................................................................... g- 2 timer controller signal ................................................................................................... g-3 interrupt lines ................................................................................................................ ... g-3 uart interface................................................................................................................. .g-3 internal bus interface sysid register ............................................................................... g-3 jtag device_id register ............................................................................................... g-3 jtag boundary scan cells............................................................................................... g-3 electrical / pinout ............................................................................................................ .. g-3 pin description table .......................................................................................................... ........ g-4 logic diagram.................................................................................................................. ......... g-10 index ............................................................................................................................... ........................i-1 table of contents 79rc32334/332 user reference manual xviii june 4, 2002 notes notes 79rc32334/332 user reference manual xix june 4, 2002 list of tables table 1.1 example of byte ordering for ?big endi an? or ?little endian? system definition ..............1-2 table 1.2 pin description for rc32334 .......................................................................................... .1-6 table 1.3 pin description for rc32332 ..........................................................................................1 -13 table 1.4 rc32334 typical memory map ......................................................................................1-21 table 1.5 internal address map fo r biu control registers.............................................................1-22 table 1.6 internal address map for memory and dram base address and base mask registers......................................................................................................1-22 table 1.7 internal address map for memory control registers......................................................1-23 table 1.8 internal address map for dram memory controller registers ......................................1-23 table 1.9 internal address mapping of expansion interrupt registers ..........................................1-23 table 1.10 internal address mapping of programmable i/o registers ............................................1-25 table 1.11 internal address mapping of timer controller registers................................................1-25 table 1.12 internal address mapping of uart 0 registers.............................................................1-26 table 1.13 internal address mapping of uart 1 registers.............................................................1-27 table 1.14 internal address mappi ng of spi registers....................................................................1-27 table 1.15 internal address mapping of dma channel 0 registers ................................................1-28 table 1.16 internal address mapping of dma channel 1 registers ................................................1-28 table 1.17 internal address mapping of dma channel 2 registers ................................................1-28 table 1.18 internal address mapping of dma channel 3 registers ................................................1-29 table 1.19 internal address mapping of pci interface control registers ........................................1-29 table 3.1 permitted address combinations .....................................................................................3-2 table 3.2 performance levels of mul/div and new instructions....................................................3-3 table 3.3 load and store instructions........................................................................................... ...3-4 table 3.4 arithmetic instructions (alu immediate) ..........................................................................3-5 table 3.5 arithmetic instructions (3-operand, r-type) ....................................................................3-5 table 3.6 multiply, divide and dsp instructions ...............................................................................3- 6 table 3.7 jump and branch instructions .......................................................................................... 3-6 table 3.8 shift instructions .................................................................................................... ...........3-7 table 3.9 coprocessor instructions .............................................................................................. ....3-7 table 3.10 special instructions................................................................................................. ..........3-7 table 3.11 exception instructions............................................................................................... ........3-8 table 3.12 cp0 instructions ..................................................................................................... ..........3-8 table 5.1 tlb register field descriptions ....................................................................................... 5-2 table 5.2 rc32334 mmu registers................................................................................................. 5-3 table 5.3 index register field descriptions ..................................................................................... 5-3 table 5.4 random register field descriptions ................................................................................5-4 table 5.5 entrylo0 and entrylo1 register field descriptions .........................................................5-5 table 5.6 tlb page coherency attributes .......................................................................................5- 5 table 5.7 context register field descriptions .................................................................................5- 5 table 5.8 pagemask register field descriptions.............................................................................5-6 table 5.9 wired register field descriptions ....................................................................................5 -7 table 5.10 entryhi register fiel d content descriptions ....................................................................5-8 table 6.1 basic cp0 registers................................................................................................... ......6-2 table 6.2 status register field descriptions.................................................................................... 6-4 table 6.3 cause register field descriptions ...................................................................................6- 6 table 6.4 cause register exccode field.........................................................................................6 -6 table 6.5 prid register field descriptions ...................................................................................... 6-7 table 6.6 config register field content descriptions......................................................................6-8 table 6.7 watch register field description...................................................................................... 6-9 list of tables 79rc32334/332 user reference manual xx june 4, 2002 notes table 6.8 dwatch register field descriptions .................................................................................6-9 table 6.9 ecc register fi eld descriptions ....................................................................................6-1 0 table 6.10 cache error register field descriptions ........................................................................6-10 table 6.11 taglo register field descriptions .................................................................................. 6- 11 table 6.12 primary cache state values........................................................................................... 6-12 table 6.13 exception priority order (highest to lowest) ...................................................................6-13 table 6.14 base address vector offset........................................................................................... .6-14 table 6.15 list of rc32334 exception vectors.................................................................................6-1 4 table 6.16 rc32334 exception vectors...........................................................................................6 -14 table 6.17 list of exception handling flowchart types ...................................................................6-22 table 7.1 rc32334 cache attributes.............................................................................................. .7-2 table 7.2 primary i-cache line field descriptions ..........................................................................7-3 table 7.3 primary d-cache line field description...........................................................................7-4 table 7.4 primary cache states.................................................................................................. .....7-6 table 8.1 cpu bus interface control registers ...............................................................................8-5 table 8.2 cpu to ip register addresses and descriptions..............................................................8-5 table 8.3 port width control regi ster field definition .....................................................................8-6 table 8.4 encoding of 8-, 16-, and 32-bit port widths......................................................................8-7 table 8.5 memory region address ranges.....................................................................................8-7 table 8.6 cpu bus turnaround (bta) contro l register field descriptions.....................................8-8 table 8.7 width encoding of bus turnaround cycles ......................................................................8-9 table 8.8 bus turnaround (bta) control register field descriptions ...........................................8-10 table 8.9 width encoding of bus turnaround cycles ....................................................................8-10 table 8.10 address latch timing bit field descriptions .................................................................. 8-11 table 8.11 arbitration field val ues and action description..............................................................8-12 table 8.12 buserror control regi ster field descriptions .................................................................8-13 table 8.13 sysid register field descriptions ..................................................................................8- 15 table 9.1 port width assignments to data lines .............................................................................9-2 table 9.2 data transfer sequences for 8-bit port width..................................................................9-2 table 9.3 data transfer sequences for 16-bit port width................................................................9-3 table 9.4 data transfer sequences for 32-bit port width................................................................9-3 table 10.1 8- and 16-bit lsb addresses and write-enable connections ........................................10-4 table 10.2 rc32334 typical memory map ......................................................................................10-5 table 10.3 memory type field values and actions..........................................................................10-6 table 10.4 port width size field values and actions.......................................................................10-6 table 10.5 minimum wait-state settings .........................................................................................1 0-7 table 10.6 memory controller pin descriptions ...............................................................................10-8 table 10.7 list of memory control registers ...................................................................................10 -9 table 10.8 internal chip select base addresses ...........................................................................10-10 table 10.9 internal chip select grouping....................................................................................... 1 0-11 table 10.10 memory mask field definitions and values.................................................................. 10-11 table 10.11 memory controller register field descriptions, channels 5:0 ..................................... 10-11 table 11.1 sdram differences between z and y revisions .......................................................... 11-1 table 11.2 modified and new sdram control registers ................................................................ 11-2 table 11.3 supported sdrams ..................................................................................................... .. 11-3 table 11.4 sdram address multiplexing......................................................................................... 11 -4 table 11.5 sdram command encoding ......................................................................................... 11-6 table 11.6 base address and base mask address map ................................................................. 11-7 table 11.7 sdram register address map ...................................................................................... 11-9 table 11.8 sdram primary control r egister field descriptions................................................... 11-10 table 11.9 sdram secondary control regi ster field descriptions .............................................. 11-13 table 12.1 pci differences between z and y revisions .................................................................12-2 table 12.2 additional pci control registers ....................................................................................1 2-3 table 12.3 initialization pins mem_addr[22:20] settings..................................................................12-3 table 12.4 pci address map...................................................................................................... ......12-7 list of tables 79rc32334/332 user reference manual xxi june 4, 2002 notes table 12.5 pci serial eeprom address fields ..............................................................................12-9 table 12.6 pci commands ......................................................................................................... .....12-9 table 12.7 pci device to idsel mapping......................................................................................12-1 0 table 12.8 rc32334 muxed pci pin names and directions .........................................................12-12 table 12.9 pci interface control register address map................................................................12-12 table 12.10 pci controller interrupt pending register 11 field descriptions..................................12-13 table 12.11 cpu to pci mailbox interrupt p ending register 12 field descriptions ........................12-14 table 12.12 pci to cpu mailbox interrupt p ending register 13 field descriptions ........................12-14 table 12.13 pci memory space [1,2,3] base register field descriptions ......................................12-15 table 12.14 pci i/o base register field descriptions.....................................................................12-15 table 12.15 pci new feature regist er field descriptions ..............................................................12-17 table 12.16 pci target control register field descriptions ............................................................12-18 table 12.17 pci arbitration regist er field descriptions ..................................................................12-22 table 12.18 pci to cpu memory/io space [1,2,3,4 ] base register field descriptions ..................12-23 table 12.19 pci configuration address register field descriptions ...............................................12-24 table 12.20 pci configuration data r egister field description.......................................................12-24 table 12.21 rc32334 pci configuration registers .........................................................................12-25 table 12.22 vendor id address field description............................................................................12-25 table 12.23 device id address field description ............................................................................12-26 table 12.24 command register.................................................................................................... ...12-26 table 12.25 configuration pci status register................................................................................12- 27 table 12.26 configuration device revision identif ication register fiel d description ......................12-27 table 12.27 class code register field description .........................................................................12-28 table 12.28 class code definitions .............................................................................................. ...12-28 table 12.29 configuration cacheline size field description............................................................12-29 table 12.30 master latency timer register field descriptions .......................................................12-29 table 12.31 header type register field description .......................................................................12-29 table 12.32 bist register field description....................................................................................1 2-30 table 12.33 memory/io base address regist er 1 (bar1) field description...................................12-30 table 12.34 memory/i/o base address registers 2 and 4 (bar2,4) field description...................12-31 table 12.35 memory/i/o base address regist er (bar3) field description.....................................12-31 table 12.36 subsystem vendor id field description .......................................................................12-32 table 12.37 subsystem id field description....................................................................................12 -32 table 12.38 interrupt line register field description ......................................................................12-32 table 12.39 interrupt pin register field description ........................................................................12-3 3 table 12.40 min_gnt register field description ...........................................................................12-33 table 12.41 max_lat register field description.............................................................................12-33 table 12.42 trdy timeout value field description ........................................................................12-33 table 12.43 retry timeout value field description .........................................................................12-34 table 13.1 dma differences between z and y revisions ...............................................................13-2 table 13.2 new fields in dma c onfiguration register ....................................................................13-2 table 13.3 fixed priority encoding.............................................................................................. .....13-8 table 13.4 dma signal pins and definitions..................................................................................13-1 0 table 13.5 dma interrupt definitions............................................................................................ .. 13-11 table 13.6 dma channel 0 register address map........................................................................13-13 table 13.7 dma channel 1 register address map........................................................................13-13 table 13.8 dma channel 2 register address map........................................................................13-13 table 13.9 dma channel 3 register address map........................................................................13-14 table 13.10 configuration register field descriptions ....................................................................13-14 table 13.11 base descriptor address field description ..................................................................13-17 table 13.12 current descriptor address field description ..............................................................13-19 table 13.13 source address register field description ..................................................................13-19 table 13.14 destination address field description..........................................................................13-20 table 13.15 next descriptor addr ess field description ...................................................................13-20 table 13.16 status register ..................................................................................................... ........13-20 list of tables 79rc32334/332 user reference manual xxii june 4, 2002 notes table 14.1 interrupt signal pins and definitions...............................................................................1 4-3 table 14.2 expansion interrupt register group 0 address map......................................................14-3 table 14.3 bus error register group 1 address map ......................................................................14-3 table 14.4 pio low register group 2 address map .......................................................................14-3 table 14.5 pio high register group 3 address map.......................................................................14-4 table 14.6 timer rollover interrupt register group 4 address map ...............................................14-4 table 14.7 uart 0 interrupt register group 5 address map ..........................................................14-4 table 14.8 uart 1 interrupt register group 6 address map ..........................................................14-4 table 14.9 dma channel 0 register group 7 address map............................................................14-4 table 14.10 dma channel 1 register group 8 address map............................................................14-4 table 14.11 dma channel 2 register group 9 address map............................................................14-5 table 14.12 dma channel 3 register group 10 address map..........................................................14-5 table 14.13 pci controller interrupt register group 11 address map ..............................................14-5 table 14.14 external interrupt register group 12 address map........................................................14-5 table 14.15 pci to cpu interrupt register group 13 address map ..................................................14-5 table 14.16 spi interrupt register group 14 address map...............................................................14-5 table 14.17 interrupt pending field description ................................................................................1 4-6 table 14.18 interrupt mask register ............................................................................................. .....14-6 table 14.19 interrupt clear regist er field descriptions.....................................................................14-6 table 14.20 group 0 register settings ........................................................................................... ...14-7 table 14.21 group 1 (bus error) register settings............................................................................14- 7 table 14.22 group 2 (pio low) register settings .............................................................................14-7 table 14.23 group 3 (pio high) register settings ............................................................................14-8 table 14.24 group 4 (timer rollover interrupt) register settings .....................................................14-8 table 14.25 group 5 (uart 0 interrupt) register settings................................................................14-8 table 14.26 group 6 (uart 1 interrupt) register settings................................................................14-8 table 14.27 group 7 (dma memory2i/o interrupt 0) register settings.............................................14-9 table 14.28 group 8 (dma memory2io interrupt 1) register settings..............................................14-9 table 14.29 group 9 (dma pci master in terrupt 0) register settings...............................................14-9 table 14.30 group 10 (dma pci master in terrupt 1) register settings.............................................14-9 table 14.31 group 11 (pci controller) register settings.................................................................14-10 table 14.32 group 12 register settings .......................................................................................... 14-10 table 14.33 group 13 register settings .......................................................................................... 14-11 table 14.34 group 14 register settings .......................................................................................... 14-11 table 15.1 serial mode protocol/alter nate signal descriptions .......................................................15-3 table 15.2 uart interface/alternate signal descriptions................................................................15-4 table 15.3 timer/alternate signal descriptions ...............................................................................15- 4 table 15.4 dma interface/alternate signal descriptions..................................................................15-5 table 15.5 pio interface/alternate signal descriptions ...................................................................15-5 table 15.6 pio register address map............................................................................................. 15-5 table 15.7 pio data register 0 field description............................................................................15-6 table 15.8 pio data register 0 high/low descriptions...................................................................15-6 table 15.9 pio data register 1 field description............................................................................15-7 table 15.10 pio data register 1 high/low descriptions...................................................................15-7 table 15.11 pio function direction r egister 0 field description ......................................................15-7 table 15.12 pio direction register 0 input/output descriptions .......................................................15-8 table 15.13 pio direction register 1 field description .....................................................................15-9 table 15.14 pio direction register 1 input/output description .........................................................15-9 table 15.15 pio function select regi ster 0 field description...........................................................15-9 table 15.16 pio special function/general purpos e select register 0 description ........................15-10 table 15.17 pio function select regi ster 1 field description......................................................... 15-11 table 15.18 pio function select register 1 spec ial function/general purpose description.......... 15-11 table 15.19 pio new feature register field description................................................................ 15-11 table 16.1 pin definitions for the timer/counter signals.................................................................16-3 table 16.2 timer register 0 (general purpose) address map ........................................................16-3 list of tables 79rc32334/332 user reference manual xxiii june 4, 2002 notes table 16.3 timer register 1 (general purpose) address map ........................................................16-3 table 16.4 timer register 2 (general purpose) address map ........................................................16-3 table 16.5 register 3 for watchdog address map...........................................................................16-3 table 16.6 register 4 for cpu bus time-out address map ............................................................16-4 table 16.7 register 5 for ip bus time-out address map .................................................................16-4 table 16.8 register 6 for dram refresh address map...................................................................16-4 table 16.9 register 7 for warm reset address map .......................................................................16-4 table 16.10 timer controller regi ster field descriptions ..................................................................16-5 table 16.11 count register fields descriptions ................................................................................16 -5 table 16.12 compare register fields descriptions ...........................................................................16-5 table 17.1 divisor value examples for typical baud rates.............................................................17-2 table 17.2 rc32334 pin descriptions............................................................................................. .17-3 table 17.3 uart0 register address map .......................................................................................17-4 table 17.4 uart1 register address map .......................................................................................17-4 table 17.5 interrupt enable regi ster field descriptions ..................................................................17-6 table 17.6 interrupt identity register fields and descriptions.........................................................17-7 table 17.7 buffer control register field descriptions......................................................................17-8 table 17.8 line control register field descriptions ........................................................................17-9 table 17.9 modem control regist er field descriptions ...............................................................17-10 table 17.10 line status register field descriptions........................................................................17-10 table 17.11 modem status register field descriptions................................................................. 17-11 table 17.12 scratch register field descriptions..............................................................................17- 12 table 18.1 spi signal descriptions .............................................................................................. ....18-2 table 18.2 spi register address map ............................................................................................. 18-4 table 18.3 spi clock register (s pcnt) field description ..............................................................18-5 table 18.4 spi control register field descriptions .........................................................................18-5 table 18.5 spi status register (spsr) field desc riptions..............................................................18-6 table 18.6 spi data i/o register (spdr) field description............................................................18-7 table 19.1 boot-mode configuration settings..................................................................................19- 4 table 19.2 rc32334 reset_boot_mode initialization settings..........................................................19-5 table 20.1 jtag pin descriptions................................................................................................ ....20-2 table 20.2 instructions supported by rc32334?s jtag boundary scan ........................................20-5 table 20.3 system controller device identification register............................................................20-7 table 21.1 ejtag pins ........................................................................................................... .........21-4 table 21.2 cpu core device i dentification register...................................................................... 21-11 table 21.3 implementation register............................................................................................. .21-12 table 21.4 ejtag_control_register .............................................................................................21 -14 table 21.5 instruction decoding................................................................................................. ....21-19 table 21.6 debug register....................................................................................................... ......21-23 table 21.7 debug exception program counter..............................................................................21-24 table 21.8 debug exception save register...................................................................................21-25 table 21.9 32-bit register map (base address = 0xff30 0000)......................................................21-25 table 21.10 debug control register - dcr .....................................................................................21- 26 table 21.11 instruction address break status register - ibs..........................................................21-27 table 21.12 instruction address break register n - iban ................................................................21-27 table 21.13 instruction address break mask register n - ibmn......................................................21-27 table 21.14 instruction address break control n register - ibcn ...................................................21-28 table 21.15 data address break status - dbs................................................................................21-28 table 21.16 data address break n register - dban........................................................................21-29 table 21.17 processor bus break status - pbs ..............................................................................21-29 table 21.18 processor address bus break register n - pban........................................................21-29 table 21.19 processor data bus br eak n register - pbdn .............................................................21-30 table 21.20 processor data bus mask n register - pbmn..............................................................21-30 table 21.21 processor bus break contro l and address mask n - pbcn .........................................21-30 table 21.22 dynamic trace information........................................................................................... 21-34 list of tables 79rc32334/332 user reference manual xxiv june 4, 2002 notes table 21.23 pc trace status information ........................................................................................2 1-34 table 21.24 exception and exception codes at ejtag_tpc ...............................................................21-35 table 21.25 pin numbering of the jtag and ejtag target connector ..........................................21-42 table a.1 value of hint field for the prefetch instruction ................................................................ a-2 table c.1 primary data cache operations...................................................................................... c-1 table c.2 primary instruction cache operations............................................................................. c-2 table f.1 integer multiply and divide performance..........................................................................f-2 table g.1 feature set comparison between rc32332 and rc32334 ........................................... g-1 table g.2 pio [data/direction/function select] register 0 comparison ......................................... g-2 table g.3 pio [data/direction/function select] register 1 comparison ......................................... g-2 table 21.26 pin description for rc32332 ......................................................................................... .. g-4 notes 79rc32334/332 user reference manual xxv june 4, 2002 list of figures figure 1.1 rc32334 block diagram ................................................................................................ ..1-1 figure 1.2 signal transitions ................................................................................................... ..........1-2 figure 1.3 clock-to-q delay ..................................................................................................... .........1-3 figure 1.4 system block diagram ................................................................................................. ....1-4 figure 1.5 logic diagram for rc32334 ...........................................................................................1 -19 figure 1.6 logic diagram for rc32332 ...........................................................................................1 -20 figure 2.1 rc32300 cpu core block ............................................................................................... 2-2 figure 2.2 rc32300 registers .................................................................................................... ......2-2 figure 2.3 big-endian byte ordering convention..............................................................................2-3 figure 2.4 little-endian byte ordering convention ...........................................................................2-3 figure 3.1 cpu instruction formats .............................................................................................. ....3-1 figure 4.1 instruction pipeline stages .......................................................................................... .....4-1 figure 4.2 pipeline activities.................................................................................................. ............4-3 figure 4.3 cpu pipeline branch delay............................................................................................ ..4-4 figure 4.4 cpu pipeline load delay .............................................................................................. ...4-4 figure 4.5 exception detection.................................................................................................. ........4-5 figure 4.6 data cache miss ...................................................................................................... ........4-5 figure 4.7 instruction cache miss ............................................................................................... ......4-6 figure 5.1 overview of a 32-bit vi rtual address translation..............................................................5-1 figure 5.2 tlb register format .................................................................................................. ......5-2 figure 5.3 index register format ................................................................................................ ......5-3 figure 5.4 random register format ............................................................................................... ..5-4 figure 5.5 entrylo0 and entrylo1 register formats ........................................................................5-4 figure 5.6 context register format.............................................................................................. .....5-5 figure 5.7 pagemask register format ............................................................................................. .5-6 figure 5.8 diagram showing ranges of wired and random entries................................................5-7 figure 5.9 wired register format................................................................................................ ......5-7 figure 5.10 bad virtual address r egister (badvaddr) format ...........................................................5-8 figure 5.11 entryhi register format ............................................................................................. ......5-8 figure 5.12 illustration of rc32334 user mode address space .........................................................5-9 figure 5.13 illustration of rc32334 kernel mode address space ....................................................5-10 figure 6.1 count register format ................................................................................................ .....6-2 figure 6.2 compare register format .............................................................................................. ..6-3 figure 6.3 status register format............................................................................................... ......6-3 figure 6.4 cause register format................................................................................................ .....6-6 figure 6.5 epc register format.................................................................................................. ......6-7 figure 6.6 prid register format ................................................................................................. ......6-7 figure 6.7 config register format............................................................................................... ......6-8 figure 6.8 iwatch register format............................................................................................... .....6-9 figure 6.9 dwatch register format ............................................................................................... ...6-9 figure 6.10 ecc register format ................................................................................................. ....6-10 figure 6.11 cacheerr register ................................................................................................... .......6-10 figure 6.12 taglo register format............................................................................................... ....6-11 figure 6.13 errorepc register ................................................................................................... .......6-12 figure 6.14 general exception process ........................................................................................... .6-13 figure 6.15 process of the reset exception...................................................................................... 6-15 figure 6.16 process of the soft reset and nmi exceptions..............................................................6-16 figure 6.17 process of the cache error exception............................................................................6-19 figure 6.18 general exception handling (hw)..................................................................................6-2 3 list of figures 79rc32334/332 user reference manual xxvi june 4, 2002 notes figure 6.19 general exception servicing guideline (sw).................................................................6-24 figure 6.20 tlb refill exception handling (hw)...............................................................................6-2 5 figure 6.21 tlb refill exception servicing guideline (sw) ..............................................................6-26 figure 6.22 cache error exception handling (h w) and servicing guidelines (sw) .........................6-27 figure 6.23 reset, soft reset & nmi exception handl ing (hw) and servicing guidelines (sw) .....6-28 figure 7.1 logical hierarchy of memory.......................................................................................... ..7-1 figure 7.2 primary i-cache line format.......................................................................................... ..7-3 figure 7.3 primary d-cache line format.......................................................................................... 7-4 figure 7.4 conceptual primary cache lookup sequence.................................................................7-5 figure 7.5 primary cache data and tag organization......................................................................7-5 figure 8.1 ip bus bridge block diagram .......................................................................................... .8-1 figure 8.2 subblock ordered data retrieval.....................................................................................8 -2 figure 8.3 address latch time with fast decode setting.................................................................8-3 figure 8.4 address latch time with slow decode setting................................................................8-3 figure 8.5 rc32334 cpu_ad[31:0] data phase.................................................................................8-4 figure 8.6 format of cpu port width control register .....................................................................8-6 figure 8.7 cpu bus turnaround (bta) control register format......................................................8-8 figure 8.8 bus turnaround (bta) control register format ............................................................8-10 figure 8.9 timing of bus turnaround cycle( s) (example of 1 cycle bta)......................................8-11 figure 8.10 address latch timing register....................................................................................... 8-11 figure 8.11 arbitration register field .......................................................................................... ......8-12 figure 8.12 buserror control register fields .................................................................................... 8-12 figure 8.13 buserror address register........................................................................................... ..8-12 figure 8.14 sysid register fields ............................................................................................... ......8-14 figure 9.1 external local bus inte rface unit block diagram.............................................................9-1 figure 9.2 debug signals during a read .......................................................................................... 9-5 figure 9.3 debug signals during a write. ........................................................................................ .9-6 figure 10.1 block diagram of rc 32334 memory controller..............................................................10-1 figure 10.2 subblock ordered burst read sequences.....................................................................10-2 figure 10.3 memory base address r egister for banks 1:0.............................................................10-10 figure 10.4 memory bank mask regi ster for banks 1:0 .................................................................10-10 figure 10.5 memory control register channel 5:0 .........................................................................10-11 figure 10.6 single word sram read transaction .........................................................................10-13 figure 10.7 single word sram read transaction with wait-state ................................................10-14 figure 10.8 single word sram write transaction..........................................................................10-15 figure 10.9 single word sram write transaction with wait-state ................................................10-16 figure 10.10 quad word burst read sram transaction .................................................................10-17 figure 10.11 sram 4 word burst write............................................................................................ 10-18 figure 10.12 tri-byte 16-bit sram write transaction .......................................................................10-18 figure 10.13 ioi 1 word single read............................................................................................. ...10-19 figure 10.14 ioi 1 word single read with wait-state.......................................................................10-20 figure 10.15 ioi 1 word single write............................................................................................ ....10-21 figure 10.16 ioi 1 word single write with wait-state.......................................................................10-22 figure 10.17 ioi 4 word burst read .............................................................................................. ...10-22 figure 10.18 ioi 4 word burst write............................................................................................. .....10-23 figure 10.19 iom 1 word single read............................................................................................. .10-23 figure 10.20 iom 1 word single read with wait-state.....................................................................10-24 figure 10.21 iom 1 word single write............................................................................................ ..10-25 figure 10.22 iom 1 word single write with wait-state.....................................................................10-26 figure 10.23 iom 4 word burst read .............................................................................................. .10-26 figure 10.24 iom 4 word burst write............................................................................................. ...10-27 figure 10.25 dual-port 1 word single read .....................................................................................10 -27 figure 10.26 dual-port 1 word single read with wait-state ............................................................10-28 figure 10.27 dual-port 1 word single write...................................................................................... 10-29 figure 10.28 single word sram write transaction with wait-state ................................................10-30 list of figures 79rc32334/332 user reference manual xxvii june 4, 2002 notes figure 10.29 dual-port 4 word burst read.......................................................................................1 0-30 figure 10.30 dual-port 4 word burst write ....................................................................................... 10-31 figure 11.1 sdram block diagram ................................................................................................. .11-3 figure 11.2 subblock ordered retrieval method...............................................................................11-8 figure 11.3 sdram primary contro l register fields......................................................................11-10 figure 11.4 sdram secondary contro l register fields .................................................................11-13 figure 11.5 sdram non-p age burst read.....................................................................................11-15 figure 11.6 sdram non-page burst write.....................................................................................11-16 figure 11.7 sdram non-p age word read ....................................................................................11-16 figure 11.8 sdram non-page word write.....................................................................................11-17 figure 11.9 sdram page-hit burst read.......................................................................................11-1 7 figure 11.10 sdram page-hit burst write.......................................................................................11 -18 figure 11.11 sdram page-hit word read.......................................................................................11-1 8 figure 11.12 sdram page-hit word write.......................................................................................11- 19 figure 11.13 sdram page-miss burst read....................................................................................11-19 figure 11.14 sdram page-miss word read....................................................................................11-20 figure 11.15 sdram refresh ...................................................................................................... .....11-20 figure 11.16 sdram sodimm even bank non-page word read...................................................11-21 figure 11.17 sdram sodimm odd bank non-page word read....................................................11-22 figure 11.18 sdram sodimm refresh ...........................................................................................11-2 3 figure 12.1 pci interface controller block diagram..........................................................................12-3 figure 12.2 cpu to pci memory mapping ........................................................................................12- 4 figure 12.3 pci to cpu memory mapping ........................................................................................12- 5 figure 12.4 pci controller interrupt pending register 11 fields.....................................................12-13 figure 12.5 cpu to pci mailbox interr upt pending register 12 fields ...........................................12-13 figure 12.6 pci to cpu mailbox interr upt pending register 13 fields ...........................................12-14 figure 12.7 pci memory space [1,2,3] base register....................................................................12-15 figure 12.8 pci i/o base register ............................................................................................... ...12-15 figure 12.9 pci new feature register............................................................................................ 12-17 figure 12.10 pci target control register ........................................................................................ .12-17 figure 12.11 pci arbitration register fields .................................................................................... .12-22 figure 12.12 pci to cpu memory/io space [1,2,3,4] base register................................................12-22 figure 12.13 pci configuration addr ess register fields ..................................................................12-24 figure 12.14 pci configuration da ta register field..........................................................................12-2 4 figure 12.15 vendor id register ................................................................................................. ......12-25 figure 12.16 device id register................................................................................................. .......12-26 figure 12.17 pci command register............................................................................................... .12-26 figure 12.18 pci status register ................................................................................................ ......12-27 figure 12.19 configuration device revi sion identification register..................................................12-27 figure 12.20 class code register................................................................................................ .....12-28 figure 12.21 cacheline size register ............................................................................................ ...12-28 figure 12.22 master latency timer register fields ..........................................................................12-29 figure 12.23 header type register field......................................................................................... .12-29 figure 12.24 bist register field................................................................................................ .......12-29 figure 12.25 pci memory/io base a ddress [1,2,3,4] register .........................................................12-30 figure 12.26 subsystem vendor id register ....................................................................................12- 32 figure 12.27 subsystem id register.............................................................................................. ...12-32 figure 12.28 interrupt line register ............................................................................................ ......12-32 figure 12.29 interrupt pin register............................................................................................. .......12-32 figure 12.30 min_gnt register ................................................................................................... ....12-33 figure 12.31 max_lat register................................................................................................... ....12-33 figure 12.32 trdy timeout value register .....................................................................................12- 33 figure 12.33 retry timeout register............................................................................................. ....12-34 figure 13.1 diagram of dma general bl ock with ip bus interface....................................................13-3 figure 13.2 dma transfer configuration.......................................................................................... .13-6 list of figures 79rc32334/332 user reference manual xxviii june 4, 2002 notes figure 13.3 diagram showing the ro tating arbitration scheme .......................................................13-8 figure 13.4 dma ready sampling point .........................................................................................13- 10 figure 13.5 dma done timing diagram..........................................................................................13- 11 figure 13.6 configuration register fields ....................................................................................... 13-14 figure 13.7 base descriptor address register field.......................................................................13-16 figure 13.8 next descriptor address field......................................................................................1 3-19 figure 13.9 source address field ................................................................................................ ...13-19 figure 13.10 destination address fields......................................................................................... ..13-20 figure 13.11 next descript or address field...................................................................................... 13-20 figure 13.12 status register fields............................................................................................. ......13-20 figure 13.13 two word sram to sram access by dma ................................................................13-23 figure 14.1 expansion interrupt c ontroller block diagram................................................................14-1 figure 14.2 expansion interrupt blo ck diagram group/bit-slice.......................................................14-2 figure 14.3 interrupt pending register fields ................................................................................... 14-6 figure 14.4 interrupt mask register ............................................................................................. .....14-6 figure 14.5 interrupt clear register field...................................................................................... ....14-6 figure 14.6 pio input asserting internal cpu_int_n[3].....................................................................14-11 figure 14.7 internal condition asserting in ternal cpu_int_n[3] interrupt..........................................14-11 figure 14.8 pending register write asse rting internal cpu_int_n[3] ...............................................14-11 figure 14.9 pending or clear regist er write de-asserting internal cpu_int_n[3] interrupt .............14-12 figure 14.10 internal condition as serting pci interrupt ....................................................................14-12 figure 14.11 pending or clear register write de-asserting pci interrupt........................................14-12 figure 14.12 cpu interrupts..................................................................................................... .........14-12 figure 15.1 pio block diagram ................................................................................................... ......15-2 figure 15.2 pio block diagram bit-slice......................................................................................... ..15-2 figure 15.3 pio data register 0 fields.......................................................................................... ...15-6 figure 15.4 pio data register 1 fields.......................................................................................... ...15-6 figure 15.5 pio direction register 0 fields ..................................................................................... .15-7 figure 15.6 pio direction register 1 fields ..................................................................................... .15-8 figure 15.7 pio function select register 0 fields............................................................................15- 9 figure 15.8 pio function select register 1 fields..........................................................................15-10 figure 15.9 pio new feature register fields .................................................................................15-1 1 figure 15.10 pio input, affecting data register................................................................................1 5-12 figure 15.11 data register write, affecting pio output ...................................................................15-12 figure 16.1 timer block diagram ................................................................................................. .....16-1 figure 16.2 diagram of individual timer core...................................................................................1 6-2 figure 16.3 timer control register fields ....................................................................................... ..16-4 figure 16.4 count register fields ............................................................................................... ......16-5 figure 16.5 compare register fields............................................................................................. ...16-5 figure 16.6 timer rollover causi ng timer_tc_n to toggle ................................................................16-6 figure 16.7 timer_gate_n input causing timer to count...................................................................16-6 figure 17.1 uart block diagram.................................................................................................. ....17-1 figure 17.2 interrupt flow...................................................................................................... ............17-3 figure 17.3 receive buffer register............................................................................................. .....17-5 figure 17.4 transmit buffer register............................................................................................ .....17-5 figure 17.5 interrupt enable register........................................................................................... .....17-5 figure 17.6 divisor latch least register (dll).................................................................................1 7-6 figure 17.7 divisor latch most register (dlm).................................................................................17 -6 figure 17.8 interrupt identity register ......................................................................................... ......17-6 figure 17.9 buffer control register (bcr) fields..............................................................................17 -8 figure 17.10 line control register fields ....................................................................................... ....17-9 figure 17.11 modem control register fields ..................................................................................17-1 0 figure 17.12 line status register fields........................................................................................ ...17-10 figure 17.13 modem status register fields....................................................................................17- 11 figure 17.14 scratch register field ............................................................................................. .....17-12 list of figures 79rc32334/332 user reference manual xxix june 4, 2002 notes figure 17.15 reset register field ............................................................................................... ......17-12 figure 17.16 uart timing ........................................................................................................ ........17-12 figure 18.1 spi block diagram................................................................................................... .......18-1 figure 18.2 serial peripheral interfac e (spi) clock/data timing.......................................................18-3 figure 18.3 spi clock register field............................................................................................ .....18-5 figure 18.4 serial peripheral control (spcntl) register fields ......................................................18-5 figure 18.5 spi status regi ster (spsr) fields.................................................................................18 -6 figure 18.6 spi data i/o register ............................................................................................... ......18-7 figure 18.7 illustration of glueless connection between rc32334 processor and atmel spi serial e2proms.........................................................................................18-8 figure 18.8 spi clock-to-data output relationship ..........................................................................18-9 figure 18.9 spi clock-to-data input relationship .............................................................................18- 9 figure 19.1 signal transitions .................................................................................................. .........19-1 figure 19.2 clock-to-q delay .................................................................................................... ........19-1 figure 19.3 system clocks data set up, output, and hold timing....................................................19-2 figure 19.4 timing illustration of cpu_maste rclk-to-pclock multiply by 2..........................................19-2 figure 19.5 pll passive components .............................................................................................. 19-3 figure 19.6 pll filter circuit for noisy environments .......................................................................19-3 figure 19.7 mode configuration interface reset sequence..............................................................19-4 figure 19.8 reset vector initialization part 1 of 2............................................................................. .19-6 figure 19.9 reset vector initialization part 2 of 2............................................................................. .19-6 figure 20.1 dual tap controll er block diagram ...............................................................................20-1 figure 20.2 diagram of the jtag logic ........................................................................................... .20-2 figure 20.3 state diagram of rc32334?s tap controller .................................................................20-3 figure 20.4 diagram of observe-only input cell................................................................................20 -4 figure 20.5 diagram of output cell .............................................................................................. .....20-4 figure 20.6 diagram of output enable cell....................................................................................... 20-4 figure 20.7 diagram of bidirectional cell ....................................................................................... ...20-5 figure 20.8 system controller device id instruction format.............................................................20-7 figure 21.1 dual tap controll er block diagram ...............................................................................21-1 figure 21.2 block diagram ....................................................................................................... .........21-3 figure 21.3 simplified ejtag block diagram ...................................................................................21- 3 figure 21.4 rc32334 debug operating modes ................................................................................21-7 figure 21.5 tap controller state diagram ........................................................................................ 21-8 figure 21.6 cpu core device id instruction format.......................................................................21-11 figure 21.7 byte organization in a 32-bit ejtag data register.....................................................21-13 figure 21.8 examples of byte organization in a 32-bit ejtag data register................................21-14 figure 21.9 examples of the sync operation ..................................................................................21-1 6 figure 21.10 ejtag processor access ............................................................................................2 1-18 figure 21.11 reset overview ..................................................................................................... .......21-19 figure 21.12 shift order sequence of the jtag_all_ir register.....................................................21-21 figure 21.13 trace of conditional pc re lative jump instruction ......................................................21-37 figure 21.14 trace of indirect jump instruction ................................................................................2 1-38 figure 21.15 trace of an exception followed by a jump indirect instruction ...................................21-38 figure 21.16 trace of indirect jump inst ruction followed by an exception ......................................21-38 figure 21.17 instruction address trace trigger.................................................................................2 1-39 figure 21.18 trace trigger and general ex ception at the same time .............................................21-39 figure 21.19 jump indirect c auses trace trigger ............................................................................21-40 figure 21.20 instruction after jump i ndirect causes trace trigger...................................................21-40 figure 21.21 real-time tr ace mode to debug mode (no tpc output).............................................21-40 figure 21.22 real time trace mode to debug mode (debug exception in branch delay slot) .......21-41 figure 21.23 timing diagram of the ejtag interface signals..........................................................21-41 figure 21.24 application diagram of ta rget board and ejtag connection.....................................21-42 figure a.1 format of prefetch instruction ....................................................................................... .. a-1 figure a.2 flowchart for prefetch operation..................................................................................... a-2 list of figures 79rc32334/332 user reference manual xxx june 4, 2002 notes figure d.1 flowchart for standby mode operation........................................................................... d-2 notes 79rc32334/332 user reference manual 1 - 1 june 4, 2002 chapter 1 rc32334 device overview foreword in this manual, numerous references are made to the rc32334, fewer references to the rc32332. because the rc32334 core and the rc32332 core are essent ially the same device, the information in this manual applies equally to both devices except where noted in occasional notes and footnotes in various chapters. therefore, all referenc es to the rc32334 should be interpre ted as applying also to the rc32332 except where noted. the differences between t he rc32334 and rc32332 are summarized in appendix g. introduction the rc32334 is an integrated processor that combines a 32-bit mips instruction set architecture (isa) cpu core with a number of on-chip peripherals, to enable direct connection to boot memory, main memory, i/o, and pci. the rc32334 also includes system logic for dma, reset, interrupts, timers, and uarts. the rc32334 integrates all of the per ipherals commonly associated with an embedded system to reduce board space, design time, and effort. block diagram the rc32334 block diagram is shown in figure 1.1. the sections that follow present an operational overview of the various peripheral interfaces and controller capabilitie s that comprise the rc32334 system. also included in this chapter is a full pin descripti on table and logic diagram. mo re detailed explanations and user details such as register des criptions, timing diagrams and memory maps are provided in the specific chapter for that function. figure 1.1 rc32334 block diagram documentation conventions and definitions note that throughout this manual the foll owing terms and conventions will be used: ? to avoid confusion when dealing wit h a mixture of ?active-low? and ?active-high? signals, the terms assertion and negation are used. the term assert or assertion is used to indicate that a signal is active or true, independent of whether that level is represented by a high or low voltage. the term negate or negation is used to indicate that a signal is inactive or false. ? to define the active polarity of a signal, a suff ix will be used. signals ending with an ?_n? should be interpreted as being active, or asserted, when at a logic zero (low) level. all other signals (including timer, uart, interrupt modules cpu core dma channels sdram control memory i/o control rc32334 pci bus pci i/f and bridge address bus sdram control memory & i/o control serial peripheral interface data bus biu rc32334 device overview block diagram 79rc32334/332 user reference manual 1 - 2 june 4, 2002 notes clocks, buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level. ? to define buses, the most significant bit (msb) will be on the left and least significant bit (lsb) will be on the right. no leading zeros will be included. ? to represent numerical values, ei ther decimal, binary, or hexadec imal formats will be used. the binary format is as follows: 0b ddd, where ?d? represents either 0 or 1; the hexadecimal format is as follows: 0xdd, where ?d? represents the hexadecimal digit( s); otherwise, it is decimal. ? unless otherwise denoted, a byte will refer to an 8-bit quantity. a halfword will refer to a 16-bit quan- tity. a triple-byte will refer to a 24-bit quantity. a word will refer to a 32-bit quantity, and a double or double word will refer to a 64-bit quantity. ? a bit is set when its value is 0b1. a bit is cleared when its value is 0b0. ? the compressed notation abc[x|y|z]d refers to abcxd, abcyd, and abczd. ? in words, bit 31 is always the most significant bit and bit 0 is the least signifi cant bit. in halfwords, bit 15 is always the most significant bit and bit 0 is the least significant bit. in by tes, bit 7 is always the most significant bit and bit 0 is the least significant bit. ? the ordering of bytes within words is referred to as either ?big endian? or ?little endian.? big endian systems label byte zero as the mo st significant (leftmost) byte of a word. little endian systems label byte zero as the least signific ant (rightmost) byte of a word. table 1.1 example of byte ordering for ?big endian? or ?little endian? system definition signal terminology throughout this manual, when describing signal trans itions, the following terminology is used: ? rising edge indicates a low-to-high (0 to 1) transition. ? falling edge indicates a high-to-l ow (1 to 0) transition. ? clock-to-q delay is the amount of time it takes for a signal to move from the input of a device (clock) to the output of the device (q). these terms are illustrated in figure 1.2 and figure 1.3. figure 1.2 signal transitions 0 1 2 3 bit 0 bit 31 address of bytes within words: big endian 3 2 1 0 bit 0 bit 31 address of bytes within words: little endian 1 2 3 4 high-to-low transition low-to-high transition single clock cycle rc32334 device overview list of features 79rc32334/332 user reference manual 1 - 3 june 4, 2002 notes figure 1.3 clock-to-q delay list of features note: this list is not entirely applicable to the rc 32332. for the differences in features between the rc32334 and rc32332, see table g.1 in appendix g. ? high performance 32-bit cpu core ? dsp instruction set extensions ? enhanced mips-ii isa compatible ? 8kb instruction/2kb data cache, lockable per line ? big or little endian support ? sdram controller (32-bit memory only) ? 4 banks, non-interleaved, 512mb total ? automatic refresh generation ? memory & peripheral controller ? 6 banks, up to 32 or 64mb per bank (bank dependent) ? 8/16/ or 32-bit interface per bank ? supports flash rom, prom, sram, dual -port memory, and peripheral devices ? intel or motorola style io suppor ts external wait-state generation ? pci bridge ? 32-bit pci, up to 66 mhz ? revision 2.2 compliant ? target and master ? host or satellite ? on-chip three slot pci arbiter ? 4 dma channels ? 4 general purpose dma, each with endia nness swappers and byte lane data alignment ? any channel can be used for pci ? supports scatter/gather ? supports memory-to-memory, memory-to-i/o, memo ry-to-pci, pci-to-pc i, and i/o-to-i/o trans- fers ? supports chaining via linked lists of records ? supports unaligned transfers ? supports burst transfers ? programmable dma trans actions burst size ? uart interface ? two 16550 compatible uarts ? baud rate support up to 1.5m ? modem signals included on one channel ? programmable io (pio) ? input/output/interrupt source ? individually programmable clock input q data in data out clock-to-q delay rc32334 device overview system block diagram 79rc32334/332 user reference manual 1 - 4 june 4, 2002 notes ? interrupt control ? provides services for internal and external sources ? allows status of each interrupt to be read and masked ? four general purpose 32-bit timer/counters ? serial peripheral interface (spi) ? boundary scan jtag interface (ieee std. 1149.1 compatible) ? in circuit emulator interface ? compatible with enhanced jtag (ejtag) standard system block diagram figure 1.4 illustrates the typical system impl ementation, based on the rc32334 integrated processor. the rc32334 provides all of the ne cessary control and address signals to drive the external memory and i/o. note that, depending on the loading of the system bus, external data buffers could be used to reduce the loading and isolate different memory regions. figure 1.4 system block diagram system overview note: the pci bridge information and the uart info rmation in this section is not entirely applicable to the rc32332. for the differences, see table g.1 in appendix g. the rc32334 generates all necessary control signal s and address buses to the external memory and i/o. for main memory, i/o, on-chip peripherals, re gisters, and pci, the rc32334 divides the physical address space into 13 different regions. memory controller. the memory controller on the rc32334 pr ovides all of the address buses and control signals for interfacing the rc32334 to st andard sram, prom, flash, and i/o, and includes the boot prom interface. the memory controller provides six individual chip selects and supports 8, 16, and 32-bit wide memory and i/os. the two chip se lects have highly configur able memory address ranges, allowing selection of various memory types and widths to be supported. the rc32334 provides controls for optional external data transceivers, for systems that require fast signalling with large loads. sdram controller . the sdram controller provides higher throughput while using available dram circuitry, adding little to the cost of the system. t he sdram controller directly manages four banks of 32-bit physical non-interleaved memory. each bank is 32-bi ts wide and supports a maximum of 64 mb per bank, timers, uart, interrupt controller cpu core dma channels memory i/o control rc32334 32-bit, 66 mhz pci bus pci bridge with arbiter address & control clock sdram memory & i/o dram ctl serial peripheral interface pio serial eeprom rc32334 32-bit data bus rc32334 device overview system overview 79rc32334/332 user reference manual 1 - 5 june 4, 2002 notes up to a total memory size of 512 mb. the sdram memory subsystem can be implemented with a broad range of device types, including so -dimms and sdram modules with dev ices from 16 mb to 256 mb. the sdram controller has a built-in refresh generator. pci bridge. to transfer data between main memory and the pci bus, the rc32334 incorporates a pci bridge. at reset time, the pci bridge can be configured as either a host or satel lite bridge. the pci bridge supports 32-bit pci?at up to 66mhz ?and is revision 2.2 compliant. as a pci master, the rc32334 can generate memory, i/o, or configuration cycles for direct local-to-pci bus accesses. the pci bridge contains internal logic to arbitrate t he ownership of the pci bus between multiple pci bus master devices. for up to three external pci devices, two arbitration schemes are supported: ? round robin, allowing devices to control the bus in a programmable sequential order ? fixed priority, allowing the user to provide mo re bus bandwidth to a specific pci-based peripheral as a pci target, the rc32334 allows access to its internal registers and to the rc32334 local bus through the pci, i/o read and write, or memory read and write commands. the rc32334 pci bridge supports byte swapping between littl e endian and big endian ordering conv entions for systems when the cpu subsystem is configured as a big endian system. dma controller. four general purpose dma channels move data between source and destination ports. source and destination ports can be system me mory, pci, or i/o devices. any of the four channels can be used for pci initiator reads or writes. all four channels support a descriptor structure, to allow effi- cient data scatter/gather. the dma controller s upports swapping of data between big and little endian memory and i/o subsystems. it also supports quad-word burst transfers. all external 16 and 8-bit memory i/os are treated as memory -mapped, word-aligned devices. expansion interrupt controller. the expansion interrupt controller pr ovides the interrupt logic for soft- ware to analyze the various rc32334 generated system interrupts and adds to the control already provided through the cp0 registers of the riscore? 32300. ea ch system interrupt is registered and the pending status provided through this feature. the pending stat us can then be used to automatically generate a hard- ware interrupt to the cpu core via individual mask bits. the pending interrupt status can also be optionally set or cleared by a direct software write. pio. programmable i/o (pio) pins are provided on t he rc32334 so that any unused peripheral pins can be programmed for use as general purpose discrete i/o pins. these pio pins can be software programmed as input or output lines, allowi ng pin values to be software program med in output mode and software read- able while in the input mode. the pio pins can al so be used as a source of interrupts to the cpu. uart. the rc32334 incorporates two 16550 (an enhanced version of the 16450) compatible uarts. to relieve the cpu of software overhead, the 16550 uart can be put into fifo mode, allowing execution of either 16450 or 16550 compatible software. two sets of 16-byte fifos are enabled during the 16550 mode: one set in the receive data path and one set in the transmit data path. a baud rate generator is included that divides the system clock by 1 to 65k and provides a 16x clock for driving the transmitter and receiver logic. timers/counters. three on-chip 32-bit general purpose timers are provided on the rc32334. each timer consists of both a count and a compare register . the count register resets to zero and then incre- ments until it equals the compare register. when the count and comp are registers are equal, the tc_n output is asserted and the count is then reset to zero. jtag. board-level manufacturing debugging is facilitat ed through implementation of a fully compliant ieee std. 1149.1 jtag boundary scan interface. in-circuit emulation . the part provides an on-chip debug port, enabling an external system to access cpu core information. in conjunction with an in-cir cuit emulator (compatible with the ejtag standard defined by mips technologies), this enables a sophist icated system debug capability to improve the soft- ware development process. serial peripheral interface (spi ). this slow speed serial interfac e provides direct connection to spi- based peripherals, including eeproms and analog to digital (a-to-d) converters. rc32334 device overview pin description table ? rc32334 79rc32334/332 user reference manual 1 - 6 june 4, 2002 pin description table ? rc32334 the following table lists the pins provided on the rc32334. note that those pin names followed by ?_n? are active-low signals. all external pull-ups and pull-downs require 10 k ? resistor. name type reset state status drive strength capability description local system interface mem_data[31:0] i/o z high local system data bus primary data bus for memory. i/o and sdram. requires external pull-up. mem_addr[25:2] i/o [25:10] z [9:2] l [25:16] low [15:2] high memory address bus these signals provide the memory or dram address, during a memory or dram bus transaction. during each word data, the address increments either in linea r or sub-block ordering, depending on the transaction type. the table below indicates how the memory write enable signals are used to address discreet memory port width types. mem_addr[22] alternate function: reset_boot_mode[1]. mem_addr[21] alternate function: reset_boot_mode[0]. mem_addr[20] alternate function: reset_pci_host_mode. mem_addr[19] alternate function: modebit [9]. mem_addr[18] alternate function: modebit [8]. mem_addr[17] alternate function: modebit [7]. mem_addr[15] alternate function: sdram_addr[15]. mem_addr[14] alternate function: sdram_addr[14]. mem_addr[13] alternate function: sdram_addr[13]. mem_addr[11] alternate function: sdram_addr[11]. mem_addr[10] alternate function: sdram_addr[10]. mem_addr[9] alternate function: sdram_addr[9]. mem_addr[8] alternate function: sdram_addr[8]. mem_addr[7] alternate function: sdram_addr[7]. mem_addr[6] alternate function: sdram_addr[6]. mem_addr[5] alternate function: sdram_addr[5]. mem_addr[4] alternate function: sdram_addr[4]. mem_addr[3] alternate function: sdram_addr[3]. mem_addr[2] alternate function: sdram_addr[2]. mem_cs_n[5:0] output h low with internal pull- up memory chip select negated recommend external pull-up. signals that a memory bank is actively selected. mem_oe_n output h high memory output enable negated recommend external pull-up. signals that a memory bank can output its data lines onto the cpu_ad bus. mem_we_n[3:0] output h high memory write enable negated bus signals which bytes are to be written during a memory transaction. bits act as byte enable and mem_addr[1:0] signals for 8-bit or 16-bit wide addressing. table 1.2 pin description for rc32334 (part 1 of 7) port width pin signals mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] dma (32-bit) mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] 32-bit mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] 16-bit byte high write enable mem_addr[1] not used (driven low) byte low write enable 8-bit not used (driven high) mem_addr[1] mem_addr[0] byte write enable rc32334 device overview pin description table ? rc32334 79rc32334/332 user reference manual 1 - 7 june 4, 2002 mem_wait_n input ? memory wait negated requires external pull-up. sram/ioi/iom modes: allows external wait-states to be injected during last cycle before data is sampled. dpm (dual-port) mode: allows dual-port busy signal to restart memory transaction. alternate function: sdram_wait_n. mem_245_oe_n output h low memory fct245 output enable negated controls output enable to optional fct245 transceiver bank by asserting during both reads and writes to a memory or i/o bank. mem_245_dt_r_n output z high memory fct245 direction xmit/rcv negated recommend external pull-up. alternate function: cpu_dt_r_n. see cpu core specific signals below. output_clk output cpu-mas terclk high output clock optional clock output. pci interface pci_ad[31:0] i/o z pci pci multiplexed address/data bus address driven by bus master during initial frame_n assertion, and then the data is driven by the bus mas- ter during writes; or the data is driven by the bus slave during reads. pci_cbe_n[3:0] i/o z pci pci multiplexed command/byte enable bus command (not negated) bus driven by the bus master during the initial frame_n assertion. byte enable negated bus driven by the bus master during the data phase(s). pci_par i/o z pci pci parity even parity of the pci_ad[31:0] bus. driven by bus master during address and write data phases. driven by the bus slave during the read data phase. pci_frame_n i/o z pci pci frame negated driven by the bus master. assertion indicates the beginning of a bus transaction. de-assertion indicates the last datum. pci_trdy_n i/o z pci pci target ready negated driven by the bus slave to indicate the current datum can complete. pci_irdy_n i/o z pci pci initiator ready negated driven by the bus master to indicate that the current datum can complete. pci_stop_n i/o z pci pci stop negated driven by the bus slave to terminate the current bus transaction. pci_idsel_n input ? pci initialization device select uses pci_req_n[2] pin. see the pci subsection. pci_perr_n i/o z pci pci parity error negated driven by the receiving bus agent 2 clocks after the data is received, if a parity error occurs. pci_serr_n i/o open- collector zpci system error external pull-up resistor is required. driven by any agent to indicate an address parity error, data parity during a special cycle command, or any other system error. pci_clk input ? pci clock clock for pci bus transactions. uses the rising edge for all timing references. pci_rst_n input l ? pci reset negated host mode: resets all pci related logic. satellite mode: with boot from pci mode: resets all pci related logic and also warm resets the 32334. pci_devsel_n i/o z pci pci device select negated driven by the target to indicate that the target has decoded the present address as a target address. name type reset state status drive strength capability description table 1.2 pin description for rc32334 (part 2 of 7) rc32334 device overview pin description table ? rc32334 79rc32334/332 user reference manual 1 - 8 june 4, 2002 pci_req_n[2] input z ? pci bus request #2 negated requires external pull-up. host mode: pci_req_n[2] is an input indicating a request from an external device. satellite mode: used as pci_idsel pin which selects this device during a configuration read or write. alternate function: pci_idsel (satellite). pci_req_n[1] input z ? pci bus request #1 negated requires external pull-up. host mode: pci_req_n[2] is an input indicating a request from an external device. alternate function: unused (satellite). pci_req_n[0] i/o z high pci bus request #0 negated requires external pull-up for burst mode. host mode: pci_req_n[0] is an input indicating a request from an external device. satellite mode: pci_req_n[0] is an output indicating a request from this device. pci_gnt_n[2] output z 1 high pci bus grant #2 negated recommend external pull-up. host mode: pci_gnt_n[2] is an output indicating a grant to an external device. satellite mode: pci_gnt_n[2] is used as the pci_inta_n output pin. alternate function: pci_inta_n (satellite). pci_gnt_n[1] / pci_eeprom_cs i/o x for 1 pci clock then h 2 high pci bus grant #1 negated recommend external pull-up. host mode: pci_gnt_n[2:1] are outputs indicating grants to external devices. satellite mode: used as pci_eprom_cs output pin for serial chip select for loading pci configuration regis- ters in the rc32334 reset initialization vector pci boot mode. defaults to the output direction at reset time. 1st alternate function: pci_eeprom_cs (satellite). 2nd alternate function: pio[11]. pci_gnt_n[0] i/o z high pci bus grant #0 negated host mode: pci_gnt_n[0] is an output indicating a grant to an external device. recommend external pull-up. satellite mode: pci_gnt_n[0] is an input indicating a grant to this device. require external pull-up. pci_inta_n output open- collector zpci pci interrupt #a negated uses pci_gnt_n[2]. see the pci subsection. pci_lock_n input ? pci lock negated driven by the bus master to indicate that an exclusive operation is occurring. 1 z in host mode; l in satellite non-boot mode; z in satellite boot mode. 2 h in host mode; l in satellite non-boot mode; l in satellite boot mode. sdram control interface sdram_addr_12 output l high sdram address bit 12 and precharge all sdram mode: provides sdram address bit 12 (10 on the sdram chip) during row address and "pre- charge all" signal during refresh, read and write command. sdram_ras_n output h high sdram ras negated sdram mode: provides sdram ras control signal to all sdram banks. sdram_cas_n output h high sdram cas negated sdram mode: provides sdram cas control signal to all sdram banks. sdram_we_n output h high sdram we negated sdram mode: provides sdram we control signal to all sdram banks. sdram_cke output h high sdram clock enable sdram mode: provides clock enable to all sdram banks. name type reset state status drive strength capability description table 1.2 pin description for rc32334 (part 3 of 7) rc32334 device overview pin description table ? rc32334 79rc32334/332 user reference manual 1 - 9 june 4, 2002 sdram_cs_n[3:0] output h high sdram chip select negated bus recommend external pull-up. sdram mode: provides chip select to each sdram bank. sodimm mode: provides upper select byte enables [7:4]. sdram_s_n[1:0] output h high sdram sodimm select negated bus sdram mode: not used. sdram sodimm mode: upper and lower chip selects. sdram_bemask_n [3:0] output h high sdram byte enable mask negated bus (dqm) sdram mode: provides byte enables for each byte lane of all dram banks. sodimm mode: provides lower select byte enables [3:0]. sdram_245_oe_n output h low sdram fct245 output enable negated recommend external pull-up. sdram mode: controls output enable to optional fct2 45 transceiver bank by asserting during both reads and writes to any dram bank. sdram_245_dt_r_n output z high sdram fct245 direction transmit/receive recommend external pull-up. uses cpu_dt_r_n. see cpu core specific signals below. on-chip peripherals dma_ready_n[1:0] / dma_done_n[1:0] i/o z low dma ready negated bus requires external pull-up. ready mode: input pin for each general purpose dma channel that can initiate the next datum in the current dma descriptor frame. done mode: input pin for each general purpose dma channel that can terminate the current dma descriptor frame. dma_ready_n[0] 1st alternate function pio[1]; 2nd alternate function: dma_done_n[0]. dma_ready_n[1] 1st alternate function pio[0]; 2nd alternate function: dma_done_n[1]. pio[15:0] i/o see related pins low programmable input/output general purpose pins that can each be configured as a general purpose input or general purpose output. these pins are multiplexed with other pin functions: uart_cts_n[0], uart_dsr_n[0], uart_dtr_n[0], uart_rts _n[0], pci_gnt_n[1], spi_mosi, spi_miso, spi_sck, spi_ss_n, uart_rx[0], uart_tx[0], uart_rx[1], uart_tx[1], timer_tc_n[0], dma_ready_n[0], dma_ready_n[1]. note that pci_gnt_n[1], spi_mosi, spi_sck, and spi_ss_n default to outputs at reset time. the others default to inputs. timer_tc_n[0] / timer_gate_n[0] i/o z low timer terminal count overflow negated terminal count mode (timer_tc_n): output indicating that the timer has reached its count compare value and has overflowed back to 0. gate mode (timer_gate_n): input indicating that the timer may count one tick on the next clock edge. 1st alternate function: pio[2]. 2nd alternate function: timer_gate_n[0]. uart_rx[1:0] i/o z low uart receive data bus uart mode: each uart channel receives data on their respective input pin. uart_rx[0] alternate function: pio[6]. uart_rx[1] alternate function: pio[4]. uart_tx[1:0] i/o z low uart transmit data bus uart mode: each uart channel sends data on their respective output pin. note that these pins default to inputs at reset time and must be programmed via the pio interface before being used as uart outputs. uart_tx[0] alternate function: pio[5]. uart_tx[1] alternate function: pio[3]. name type reset state status drive strength capability description table 1.2 pin description for rc32334 (part 4 of 7) rc32334 device overview pin description table ? rc32334 79rc32334/332 user reference manual 1 - 10 june 4, 2002 uart_cts_n[0] uart_dsr_n[0] uart_dtr_n[0] uart_rts_n[0] i/o z low uart transmit data bus uart mode: data bus modem control signal pins for uart channel 0. uart_cts_n[0] alternate function: pio[15]. uart_dsr_n[0] alternate function: pio[14]. uart_dtr_n[0] alternate function: pio[13]. uart_rts_n[0] alternate function: pio[12]. spi_mosi i/o l low spi data output serial mode: output pin from rc32334 as an input to a serial chip for the serial data input stream. in pci satellite mode, acts as an output pin from rc32334 that connects as an input to a serial chip for the serial data input stream for loading pci configuration registers in the rc32334 reset initialization vector pci boot mode. 1st alternate function: pio[10]. defaults to the output direction at reset time. 2nd alternate function: pci_eeprom_mdo. spi_miso i/o z low spi data input serial mode: input pin to rc32334 from the output of a serial chip for the serial data output stream. in pci satellite mode, acts as an input pin from rc32334 that connects as an output to a serial chip for the serial data output stream for loading pci configuration registers in the rc32334 reset initialization vector pci boot mode. defaults to input direction at reset time. 1st alternate function: pio[7]. 2nd alternate function: pci_eeprom_mdi. spi_sck i/o l low spi clock serial mode: output pin for serial clock. in pci satellite mode, acts as an output pin for serial clock for loading pci configuration registers in the rc323334 reset initialization vector pci boot mode. 1st alternate function: pio[9]. defaults to the output direction at reset time. 2nd alternate function: pci_eeprom_sk. spi_ss_n i/o h low spi chip select output pin selecting the serial protocol device as opposed to the pci sa tellite mode eeprom device. alternate function: pio[8]. defaults to the output direction at reset time. cpu core specific signals cpu_nmi_n input ? cpu non-maska ble interrupt requires external pull-up. this interrupt input is active low to the cpu. cpu_masterclk input ? cpu master system clock provides the basic system clock. cpu_int_n[5:4], [2:0] input ? cpu interrupt requires external pull-up. these interrupt inputs are active low to the cpu. cpu_coldreset_n input l ? cpu cold reset this active-low signal is asserted to the rc32334 after v cc becomes valid on the initial power-up. the reset initialization vectors for the rc32334 are latched by cold reset. cpu_dt_r_n output z ? cpu direction transmit/receive this active-low signal controls the dt/r pin of an opt ional fct245 transceiver bank. it is asserted during read operations. requires external pull-up. 1st alternate function: mem_245_dt_r_n. 2nd alternate function: sdram_245_dt_r_n. name type reset state status drive strength capability description table 1.2 pin description for rc32334 (part 5 of 7) rc32334 device overview pin description table ? rc32334 79rc32334/332 user reference manual 1 - 11 june 4, 2002 jtag interface signals jtag_tck input ? jtag test clock requires external pull-down. an input test clock used to shift into or out of the boundary-scan register cells. jtag_tck is independent of the system and the processor clock with nominal 50% duty cycle. jtag_tdi, ejtag_dint_n input ? jtag test data in requires an external pull-up on the board. on the rising edge of jtag_tck, serial input data are shifted into either the instruction or data register, depending on the tap controller state. during real mode, this input is used as an interrupt line to stop the debug unit from real time mode and return the debug unit back to run time mode (standard jtag). this pin is also used as the ejtag_dint_n signal in the ejtag mode. jtag_tdo, ejtag_tpc output z high jtag test data out the jtag_tdo is serial data shifted out from instruction or data register on the falling edge of jtag_tck. when no data is shifted out, the jtag_tdo is tri-stated. during real time mode, this signal provides a non-sequen- tial program counter at the processor clock or at a division of processor clock. this pin is also used as the ejtag_tpc signal in the ejtag mode. jtag_tms input ? jtag test mode select requires external pull-up. the logic signal received at the jtag_tms input is decoded by the tap controller to control test operation. jtag_tms is sampled on the rising edge of the jtag_tck. jtag_trst_n input l ? jtag test reset when neither jtag nor ejtag are being used, jtag_trst _n must be driven or pulled low, or the jtag_tms/ ejtag_tms signals must be pulled up and jtag_clk actively clocked. ejtag_dclk output z ? ejtag test clock processor clock. during real time mode, this signal is used to capture address and data from the ejtag_tpc signal at the processor clock speed or any division of the internal pipeline. ejtag_pcst[2:0] i/o z low ejtag pc trace status information 111 (stl) pipe line stall 110 (jmp) branch/jump forms with pc output 101 (brt) branch/jump forms with no pc output 100 (exp) excepti on generated with an exce ption vector code output 011 (seq) sequential performance 010 (tst) trace is outputted at pipeline stall time 001 (tsq) trace trigger output at performance time 000 (dbm) run debug mode alternate function: modebit[2:0]. ejtag_debugboot input ? requires external pull- down ejtag debugboot the ejtag_debugboot input is used during reset and forces the cpu core to take a debug exception at the end of the reset sequence instead of a reset exception. this enables the cpu to boot from the ice probe without having the external memory working. this input signal is level sensitive and is not latched internally. this signal will also set the jtagbrk bit in the jtag_control_register[12]. ejtag_tms input ? requires external pull- up ejtag test mode select an external pull-up on the board is required. the ejtag_tms is sampled on the rising edge of jtag_tck. debug signals debug_cpu_dma_n i/o z low debug cpu versus dma negated de-assertion high during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction was generated from the cpu. assertion low during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction was generated from dma. alternate function: modebit[6]. name type reset state status drive strength capability description table 1.2 pin description for rc32334 (part 6 of 7) rc32334 device overview pin description table ? rc32334 79rc32334/332 user reference manual 1 - 12 june 4, 2002 debug_cpu_ack_n i/o z low debug cpu acknowledge negated indicates either a data acknowledge to the cpu or dma. alternate function: modebit[4]. debug_cpu_ads_n i/o z low debug cpu address/data strobe negated assertion indicates that either a cpu or a dma transaction is beginning and that the mem_data[31:4] bus has the current block address. alternate function: modebit[5]. debug_cpu_i_d_n i/o z low debug cpu instruction versus data negated assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is a cpu or dma data transaction. de-assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is a cpu instruction transaction. alternate function: modebit[3]. name type reset state status drive strength capability description table 1.2 pin description for rc32334 (part 7 of 7) rc32334 device overview pin description table ? rc32332 79rc32334/332 user reference manual 1 - 13 june 4, 2002 pin description table ? rc32332 the following table lists the pins provided on the rc32332. note that those pin names followed by ?_n? are active-low signals. all external pull-ups and pull-downs require 10 k ? resistor. name type reset state status drive strength capability description local system interface mem_data[31:0] i/o z high local system data bus primary data bus for memory. i/o and sdram. mem_addr[22:2] i/o [25:10] z [9:2] l [22:16] low [15:2] high memory address bus these signals provide the memory or dram address, during a memory or dram bus transaction. during each word data, the address increments either in linear or sub-block ordering, depending on the transac- tion type. the table below indicates how the memory write enable signals are used to address discrete memory port width types. mem_addr[22] alternate function: reset_boot_mode[1]. mem_addr[21] alternate function: reset_boot_mode[0]. mem_addr[20] alternate function: reset_pci_host_mode. mem_addr[19] alternate function: modebit [9]. mem_addr[18] alternate function: modebit [8]. mem_addr[17] alternate function: modebit [7]. mem_addr[15] alternate function: sdram_addr[15]. mem_addr[14] alternate function: sdram_addr[14]. mem_addr[13] alternate function: sdram_addr[13]. mem_addr[11] alternate function: sdram_addr[11]. mem_addr[10] alternate function: sdram_addr[10]. mem_addr[9] alternate function: sdram_addr[9]. mem_addr[8] alternate function: sdram_addr[8]. mem_addr[7] alternate function: sdram_addr[7]. mem_addr[6] alternate function: sdram_addr[6]. mem_addr[5] alternate function: sdram_addr[5]. mem_addr[4] alternate function: sdram_addr[4]. mem_addr[3] alternate function: sdram_addr[3]. mem_addr[2] alternate function: sdram_addr[2] mem_cs_n[5:0] output h low memory chip select negated recommend external pull-up. signals that a memory bank is actively selected. mem_oe_n output h high memory output enable negated recommend external pull-up. signals that a memory bank can output its data lines onto the cpu_ad bus. mem_we_n[3:0] output h high memory write enable negated bus signals which bytes are to be written during a memory transaction. bits act as byte enable and mem_addr[1:0] signals for 8-bit or 16-bit wide addressing. mem_wait_n input ? memory wait negated requires external pull-up. sram/ioi/iom modes: allows external wait-states to be injected during the last cycle before data is sam- pled. dpm (dual-port) mode: allows dual-port busy signal to restart memory transaction. alternate function: sdram_wait_n. table 1.3 pin description for rc32332 (part 1 of 6) port width pin signals mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] dma (32-bit) mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] 32-bit mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] 16-bit byte high write e nable mem_addr[1] not used (driven low) byte low write enable 8-bit not used (driven high) mem_addr[1] mem_addr[0] byte write enable rc32334 device overview pin description table ? rc32332 79rc32334/332 user reference manual 1 - 14 june 4, 2002 mem_245_oe_n output h low memory fct245 output enable negated controls output enable to optional fct245 transceiver bank by asserting during both reads and writes to a memory or i/o bank. mem_245_dt_r_n output z high memory fct245 direction xmit/rcv negated recommend external pull-up. alternate function: cpu_dt_r_n. see cpu core specific signals below. output_clk output cpu-mas terclk high output clock optional clock output. pci interface pci_ad[31:0] i/o z pci pci multiplexed address/data bus address driven by bus master during initial frame_n assertion, and then the data is driven by the bus master during writes; or the data is driven by the bus slave during reads. pci_cbe_n[3:0] i/o z pci pci multiplexed command/byte enable bus command (not negated) bus driven by the bus master during the initial frame_n assertion. byte enable negated bus driven by the bus master during the data phase(s). pci_par i/o z pci pci parity even parity of the pci_ad[31:0] bus. driven by bus master during address and write data phases. driven by the bus slave during the read data phase. pci_frame_n i/o z pci pci frame negated driven by the bus master. assertion indicates the beginning of a bus transaction. de-assertion indicates the last datum. pci_trdy_n i/o z pci pci target ready negated driven by the bus slave to indicate the current datum can complete. pci_irdy_n i/o z pci pci initiator ready negated driven by the bus master to indicate that the current datum can complete. pci_stop_n i/o z pci pci stop negated driven by the bus slave to terminate the current bus transaction. pci_idsel_n input ? pci initialization device select uses pci_req_n[2] pin. see the pci subsection. pci_perr_n i/o z pci pci parity error negated driven by the receiving bus agent 2 clocks after the data is received, if a parity error occurs. pci_serr_n i/o open- collector zpci system error external pull-up resistor is required. driven by any agent to indicate an address parity error, data parity during a special cycle command, or any other system error. pci_clk input ? pci clock clock for pci bus transactions. uses the rising edge for all timing references. pci_rst_n input l ? pci reset negated host mode: resets all pci related logic. satellite mode: with boot from pci mode: resets all pci related logic and also warm resets the 32332. pci_devsel_n i/o z pci pci device select negated driven by the target to indicate that the target has decoded the present address as a target address. pci_req_n[2] input z ? pci bus request #2 negated requires external pull-up. host mode: pci_req_n[2] is an input indicating a request from an external device. satellite mode: used as pci_idsel pin which selects this device during a configuration read or write. alternate function: pci_idsel (satellite). pci_req_n[0] i/o z high pci bus request #0 negated requires external pull-up for burst mode. host mode: pci_req_n[0] is an input indicating a request from an external device. satellite mode: pci_req_n[0] is an output indicating a request from this device. name type reset state status drive strength capability description table 1.3 pin description for rc32332 (part 2 of 6) rc32334 device overview pin description table ? rc32332 79rc32334/332 user reference manual 1 - 15 june 4, 2002 pci_gnt_n[2] output z 1 high pci bus grant #2 negated recommend external pull-up. host mode: pci_gnt_n[2] is an output indicating a grant to an external device. satellite mode: pci_gnt_n[2] is used as the pci_inta_n output pin. external pull-up is required. alternate function: pci_inta_n (satellite). pci_gnt_n[1] i/o x for 1 pci clock then h 2 high pci bus grant #1 negated recommend external pull-up. host mode: not used. satellite mode: used as pci_eprom_cs output pin for serial chip select for loading pci configuration reg- isters in the rc32332 reset initialization vector pci boot mode. defaults to the output direction at reset time. 1st alternate function: pci_eeprom_cs (satellite). 2nd alternate function: pio[7]. pci_gnt_n[0] i/o z high pci bus grant #0 negated host mode: pci_gnt_n[0] is an output indicating a grant to an external device. recommend external pull- up. satellite mode: pci_gnt_n[0] is an input indicating a grant to this device. requires external pull-up. pci_inta_n output open- collector zpci pci interrupt #a negated uses pci_gnt_n[2]. see the pci subsection. pci_lock_n input ? pci lock negated driven by the bus master to indicate that an exclusive operation is occurring. 1 z in host mode; l in satellite non-boot mode; z in satellite boot mode. 2 h in host mode; l in satellite non-boot mode; l in satellite boot mode. sdram control interface sdram_addr_12 output l high sdram address bit 12 and precharge all sdram mode: provides sdram address bit 12 (10 on the sdram chip) during row address and ?pre- charge all? signal during refresh, read and write command. sdram_ras_n output h high sdram ras negated sdram mode: provides sdram ras control signal to all sdram banks. sdram_cas_n output h high sdram cas negated sdram mode: provides sdram cas control signal to all sdram banks. sdram_we_n output h high sdram we negated sdram mode: provides sdram we control signal to all sdram banks. sdram_cke output h high sdram clock enable sdram mode: provides clock enable to all sdram banks. sdram_cs_n[3:0] output h high sdram chip select negated bus recommend external pull-up. sdram mode: provides chip select to each sdram bank. sodimm mode: provides upper select byte enables [7:4]. sdram_s_n[1:0] output h high sdram sodimm select negated bus sdram mode: not used. sdram sodimm mode: upper and lower chip selects. sdram_bemask_n [3:0] output h high sdram byte enable mask negated bus (dqm) sdram mode: provides byte enables for each byte lane of all dram banks. sodimm mode: provides lower select byte enables [3:0]. name type reset state status drive strength capability description table 1.3 pin description for rc32332 (part 3 of 6) rc32334 device overview pin description table ? rc32332 79rc32334/332 user reference manual 1 - 16 june 4, 2002 sdram_245_oe_n output h low sdram fct245 output enable negated recommend external pull-up. sdram mode: controls output enable to optional fct245 transceiver bank by asserting during both reads and writes to any dram bank. sdram_245_dt_r_n output z high sdram fct245 direction transmit/receive recommend external pull-up. uses cpu_dt_r_n. see cpu core specific signals below. on-chip peripherals dma_ready_n[0] i/o z low dma ready negated bus requires external pull-up. ready mode: input pin for general purpose dma channel 0 that can initiate the next datum in the current dma descriptor frame. done mode: input pin for general purpose dma channel 0 that can terminate the current dma descriptor frame. dma_ready_n[0] 1st alternate function pio[0]; 2nd alternate function: dma_done_n[0]. pio[7:0] i/o see related pins low programmable input/output general purpose pins that can each can be configur ed as a general purpose input or general purpose out- put. these pins are multiplexed with other pin functions: pci_gnt_n[1], spi_mosi, spi_miso, spi_sck, spi_ss_n, uart_rx[0], uart_tx[0], dma_ready_n[0]. note that pci_gnt_n[1], spi_mosi, spi_sck, and spi_ss_n default to outputs at reset time. the others default to inputs. uart_rx[0] i/o z low uart receive data bus uart mode: uart channel receives data. uart_rx[0] alternate function: pio[2]. uart_tx[0] i/o z low uart transmit data uart mode: uart channel send data. note that this pin defaults to an input at reset time and must be programmed via the pio interface before being used as a uart output. uart_tx[0] alternate function: pio[1]. spi_mosi i/o l low spi data output serial mode: output pin from rc32332 as an input to a serial chip for the serial data input stream. in pci satellite mode, acts as an output pin from rc32332 that connects as an input to a serial chip for the serial data input stream for loading pci configuration registers in the rc32332 reset initialization vector pci boot mode. defaults to the output direction at reset time. 1st alternate function: pio[6]. 2nd alternate function: pci_eeprom_mdo. spi_miso i/o z low spi data input serial mode: input pin to rc32332 from the output of a serial chip for the serial data output stream. in pci satellite mode, acts as an input pin from rc32332 that connects as an output to a serial chip for the serial data output stream for loading pci configuration registers in the rc32332 reset initialization vector pci boot mode. 1st alternate function: pio[3]. 2nd alternate function: pci_eeprom_mdi. spi_sck i/o l low spi clock serial mode: output pin for serial clock. in pci satellite mode, acts as an output pin for serial clock for loading pci configuration registers in the rc323332 reset initialization vector pci boot mode. defaults to the output direction at reset time. 1st alternate function: pio[5]. 2nd alternate function: pci_eeprom_sk. spi_ss_n i/o h low spi chip select output pin selecting the serial protocol device as opposed to the pci satellite mode eeprom device. alternate function: pio[4]. defaults to the output direction at reset time. name type reset state status drive strength capability description table 1.3 pin description for rc32332 (part 4 of 6) rc32334 device overview pin description table ? rc32332 79rc32334/332 user reference manual 1 - 17 june 4, 2002 cpu core specific signals cpu_nmi_n input ? cpu non-maskable interrupt requires external pull-up. this interrupt input is active low to the cpu. cpu_masterclk input ? cpu master system clock provides the basic system clock. cpu_int_n[1:0] input ? cpu interrupt requires external pull-up. these interrupt inputs are active low to the cpu. cpu_coldreset_n input l ? cpu cold reset this active-low signal is asserted to the rc32332 after v cc becomes valid on the initial power-up. the reset initialization vectors for the rc32332 are latched by cold reset. cpu_dt_r_n output z ? cpu direction transmit/receive this active-low signal controls the dt/r pin of an optional fct245 transceiver bank. it is asserted during read operations. 1st alternate function: mem_245_dt_r_n. 2nd alternate function: sdram_245_dt_r_n. jtag interface signals jtag_tck input ? jtag test clock requires external pull-down. an input test clock used to shift into or out of the boundary-scan register cells. jtag_tck is independent of the system and the processor clock with nominal 50% duty cycle. jtag_tdi, ejtag_dint_n input ? jtag test data in requires an external pull-up on the board. on the rising edge of jtag_tck, serial input data are shifted into either the instruction or data register, depending on the tap controller state. during real mode, this input is used as an interrupt line to stop the debug unit from real time mode and return the debug unit back to run time mode (standard jtag). requires an external pull-up on the board. this pin is also used as the ejtag_dint_n signal in the ejtag mode. jtag_tdo, ejtag_tpc output z high jtag test data out the jtag_tdo is serial data shifted out from instruction or data register on the falling edge of jtag_tck. when no data is shifted out, the jtag_tdo is tri-stated. during real time mode, this signal provides a non- sequential program counter at the processor clock or at a division of processor clock. this pin is also used as the ejtag_tpc signal in the ejtag mode. jtag_tms input ? jtag test mode select requires external pull-up. the logic signal received at the jtag_tms input is decoded by the tap controller to control test operation. jtag_tms is sampled on the rising edge of the jtag_tck. jtag_trst_n input l ? jtag test reset when neither jtag nor ejtag are being used, jtag_trst_n must be driven or pulled low, or the jtag_tms/ ejtag_tms signals must be pulled up and jtag_clk actively clocked. ejtag_dclk output z ? ejtag test clock processor clock. during real time mode, this signal is used to capture address and data from the ejtag_tpc signal at the processor clock speed or any division of the internal pipeline. name type reset state status drive strength capability description table 1.3 pin description for rc32332 (part 5 of 6) rc32334 device overview pin description table ? rc32332 79rc32334/332 user reference manual 1 - 18 june 4, 2002 ejtag_pcst[2:0] i/o z low ejtag pc trace status information 111 (stl) pipe line stall 110 (jmp) branch/jump forms with pc output 101 (brt) branch/jump forms with no pc output 100 (exp) exception generated with an exception ve ctor code output 011 (seq) sequential performance 010 (tst) trace is outputted at pipeline stall time 001 (tsq) trace trigger output at performance time 000 (dbm) run debug mode alternate function: modebit[2:0]. ejtag_debugboot input ? ejtag debugboot requires an external pull-down. the ejtag_debugboot input is used during reset and forces the cpu core to take a debug exception at the end of the reset sequence instead of a reset exception. this enables the cpu to boot from the ice probe without having the external memory working. this input signal is level sensitive and is not latched inter- nally. this signal will also set the jtagbrk bit in the jtag_control_register[12]. ejtag_tms input ? ejtag test mode select requires an external pull-up. the ejtag_tms is sampled on the rising edge of jtag_tck. debug signals debug_cpu_dma_n i/o z low debug cpu versus dma negated assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction was generated from the cpu. de-assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction was generated from dma. alternate function: modebit[6]. debug_cpu_ack_n i/o z low debug cpu acknowledge negated indicates either a data acknowledge to the cpu or dma. alternate function: modebit[4]. debug_cpu_ads_n i/o z low debug cpu address/data strobe negated assertion indicates that either a cpu or a dma transaction is beginning and that the mem_data[31:4] bus has the current block address. alternate function: modebit[5]. debug_cpu_i_d_n i/o z low debug cpu instruction versus data negated assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is a cpu or dma data transaction. de-assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is a cpu instruction transaction. alternate function: modebit[3]. name type reset state status drive strength capability description table 1.3 pin description for rc32332 (part 6 of 6) rc32334 device overview logic diagram ? rc32334 79rc32334/332 user reference manual 1 - 19 june 4, 2002 logic diagram ? rc32334 figure 1.5 logic diagram for rc32334 rc32334 logic symbol mem_cs_n[5:0] mem_oe_n mem_we_n[3:0] jtag_tck jtag_tms jtag_tdi v cc to i/o gnd mem_wait_n mem_245_oe_n jtag_tdo jtag_trst_n cpu_masterclk cpu_coldreset_n cpu core signals v cc i/o v ss local system jtag power / ground cpu_int_n[5:4],[2:0] cpu_dt_r_n mem_245_dt_r_n spi_mosi spi_miso spi_ss_n spi_sck sdram_addr[12] sdram_ras_n sdram_cas_n sdram_we_n output_clk timer_tc_n[0] uart_rx[1:0] uart_tx[1:0] debug_cpu_ack_n debug pci_ad[31:0] pci_cbe_n[3:0] pci_par pci_frame_n pci_trdy_n pci_irdy_n pci_stop_n pci_idsel pci_perr_n pci_serr_n pci_clk pci_rst_n pci_devsel_n pci_req_n[2:0] pci_gnt_n[2:0] interface pci_inta_n pci_lock_n pci_eeprom_mdi pci_eeprom_cs pci_eeprom_mdo pci_eeprom_sk dma_ready_n[1:0] pio[15:0] pci interface interface mem_addr[25:2] sdram_cke sdram_cs_n[3:0] sdram_bemask_n[3:0] sdram_s_n_[1:0] sdram_245_oe_n dma interface pio timer uart interface v cc to core v cc core sdram_245_dt_r_n mem_data[31:0] cpu_nmi_n debug_cpu_dma_n debug_cpu_ads_n spi interface sdram signals uart_cts_n[0] uart_rts_n[0] uart_dtr_n[0] uart_dsr_n[0] ejtag_tms ejtag_debugboot ejtag_dclk ejtag_pcst[2:0] ejtag debug_cpu_i_d_n sdram_addr[15:13] sdram_addr[11:2] ejtag_tpc v cc p v ss p rc32334 device overview logic diagram ? rc32332 79rc32334/332 user reference manual 1 - 20 june 4, 2002 logic diagram ? rc32332 figure 1.6 logic diagram for rc32332 rc32332 logic symbol mem_cs_n[5:0] mem_oe_n mem_we_n[3:0] jtag_tck jtag_tms jtag_tdi mem_wait_n mem_245_oe_n jtag_tdo jtag_trst_n cpu_masterclk cpu_coldreset_n cpu core signals local system jtag cpu_int_n[1:0] cpu_dt_r_n mem_245_dt_r_n spi_mosi spi_miso spi_ss_n spi_sck sdram_addr[12] sdram_ras_n sdram_cas_n sdram_we_n output_clk uart_rx[0] uart_tx[0] debug_cpu_ack_n debug pci_ad[31:0] pci_cbe_n[3:0] pci_par pci_frame_n pci_trdy_n pci_irdy_n pci_stop_n pci_idsel pci_perr_n pci_serr_n pci_clk pci_rst_n pci_devsel_n pci_req_n[0] pci_gnt_n[0] interface pci_inta_n pci_lock_n pci_eeprom_mdi pci_eeprom_cs pci_eeprom_mdo pci_eeprom_sk dma_ready_n[0] pio[7:0] pci interface interface mem_addr[22:2] sdram_cke sdram_cs_n[3:0] sdram_bemask_n[3:0] sdram_s_n_[1:0] sdram_245_oe_n dma interface pio uart interface sdram_245_dt_r_n mem_data[31:0] cpu_nmi_n debug_cpu_dma_n debug_cpu_ads_n spi interface sdram signals ejtag_tms ejtag_debugboot ejtag_dclk ejtag_pcst[2:0] ejtag debug_cpu_i_d_n sdram_addr[15:13] sdram_addr[11:2] ejtag_tpc pci_gnt_n[2] pci_req_n[2] v cc to i/o gnd v cc i/o v ss power / ground v cc to core v cc core v cc p v ss p rc32334 device overview typical rc32334 memory map 79rc32334/332 user reference manual 1 - 21 june 4, 2002 notes typical rc32334 memory map the rc32334 divides the physical address range into 12 distinctive regions and decodes the address generated by the cpu to determine which region is being accessed. the rc32334 integrated processor allows rearrangement of the memory map for parti cular embedded applications such as systems with sram main memory. typical rc32334 syst ems use the following memory map. rc32334 internal register map addresses and definitions important user?s note: if required, the internal register addresses listed below can be changed by the reset initialization mode?from base 1800_0000 to base 1900_0000. non-boot mode, pci-boot mode, and standard-boot mode sequence settings are provided in the reset gr oup of the rc32334 pin descrip- tions, table 1.2. this section does not include the rc32300 cpu core internal registers. for more details on the rc32300 cpu core registers, see chapter 2, which describes the registers inside of the cpu core. biu control registers the biu control registers are special interface r egisters used to control the bus access and bus error functions of the interface unit. physical address range max. size port size region 1 1. multiple memory regions may need to be placed with in the larger riscore 32300 port size regions. note: typical values are values a programmer might use. they are not necessarily the default values at reset. rc32334 region description 0000_0000 0ff f_ffff 256mb a,b,c,d dram 0,1,2,3 (16mb typical) 1000_0000 1 1ff_ffff 32mb e mem/io 2 (8mb typical) 1200_0000 13ff_ffff 32mb e mem/io 3 (8mb typical) 1400_0000 15ff_ffff 32mb f mem/io 4 (8mb typical) 1600_0000 17ff_ffff 32mb f mem/io 5 (8mb typical) 1800_0000 1bff_ffff 64mb g rc32334 internal registers 1c00_0000 1fff_ffff 64mb h mem/io 0 (4mb typical) 2000_0000 23ff_ffff 64mb i mem/io 1 (8mb typical) 4000_0000 5fff_ffff 512mb j pci memory space 1 (256mb typical) 6000_0000 7fff_ffff 512mb k pci memory space 2 (256mb typical) 8000_0000 ff1f_ffff 2034mb o reserved, undecoded. if accesses are made to this region, the rc32334 will return a bus error. ff20_0000 ff2f_ffff 1mb o reserved for rc3 2334 ejtag interface probe mem- ory. ff30_0000 ffff_ffff 13mb o reserved for rc32334 on-chip ejtag interface reg- isters. table 1.4 rc32334 typical memory map rc32334 device overview rc32334 internal register map addresses and definitions 79rc32334/332 user reference manual 1 - 22 june 4, 2002 notes base address and base mask registers these registers are used to select the address to be decoded for memory banks 0,1, 2 or 3. the base address registers determine the starting location of a par ticular memory chip select, and the mask registers are used for address bit comparison and chip select acti vation. functional descripti ons of these registers are provided in chapters 9 and 11. base address register function offset address effective address 1800_0000 bta register 00 base + offset address latch timing register 04 arbitration register 08 1800_0000 buserror control register 10 base + offset buserror address register 14 sysid register 18 table 1.5 internal address map for biu control registers base address register function offset address effective address 1800_0000 memory base address register for bank 0 80 base + offset memory base mask register for bank 0 84 memory base address register for bank 1 88 memory base mask register for bank 1 8c dram base address register for bank 0 c0 dram base mask register for bank 0 c4 dram base address register for bank 1 c8 dram base mask register for bank 1 cc dram base address register for bank 2 d0 dram base mask register for bank 2 d4 dram base address register for bank 3 d8 dram base mask register for bank 3 dc table 1.6 internal address map for memory and dram base address and base mask registers rc32334 device overview rc32334 internal register map addresses and definitions 79rc32334/332 user reference manual 1 - 23 june 4, 2002 notes memory control registers these registers provide c ontrol of the memory resource options, such as type, size, and wait-state assertion for banks 0 through 5. register definitions and descriptions are provided in chapter 10, memory controller. dram memory controller registers these registers direct control of the dram resources. resource specif ic definitions and descriptions are included in chapter 11, synchronous dram controller. expansion interrupt registers these register groups manage the interrupts. each grouping has 3 registers: interrupt pending, inter- rupt mask and interrupt clear. the r egister function is the same from group to group; however, each inter- rupt is group specific. register definitions are pr ovided in chapter 14, expansion interrupt controller. base address register function offset address effective address 1800_0200 memory control register bank 0 00 base + offset memory control register bank 1 04 memory control register bank 2 08 memory control register bank 3 0c memory control register bank 4 10 memory control register bank 5 14 table 1.7 internal address map for memory control registers base address register function offset address effective address 1800_0300 sdram control register 00 base + offset reserved 10 table 1.8 internal address map fo r dram memory controller registers base address register function offset address effective address 1800_0500 expansion interrupt pending register 0 00 base + offset expansion interrupt mask register 0 04 expansion interrupt clear register 0 08 1800_0500 expansion interrupt pending register 1 10 base + offset expansion interrupt mask register 1 14 expansion interrupt clear register 1 18 1800_0500 expansion interrupt pending register 2 20 base + offset expansion interrupt mask register 2 24 expansion interrupt clear register 2 28 table 1.9 internal address mapping of ex pansion interrupt registers (part 1 of 2) rc32334 device overview rc32334 internal register map addresses and definitions 79rc32334/332 user reference manual 1 - 24 june 4, 2002 notes 1800_0500 expansion interrupt pending register 3 30 base + offset expansion interrupt mask register 3 34 expansion interrupt clear register 3 38 1800_0500 expansion interrupt pending register 4 40 base + offset expansion interrupt mask register 4 44 expansion interrupt clear register 4 48 1800_0500 expansion interrupt pending register 5 50 base + offset expansion interrupt mask register 5 54 expansion interrupt clear register 5 58 1800_0500 expansion interrupt pending register 6 60 base + offset expansion interrupt mask register 6 64 expansion interrupt clear register 6 68 1800_0500 expansion interrupt pending register 7 70 base + offset expansion interrupt mask register 7 74 expansion interrupt clear register 7 78 1800_0500 expansion interrupt pending register 8 80 base + offset expansion interrupt mask register 8 84 expansion interrupt clear register 8 88 1800_0500 expansion interrupt pending register 9 90 base + offset expansion interrupt mask register 9 94 expansion interrupt clear register 9 98 1800_0500 expansion interrupt pending register 10 a0 base + offset expansion interrupt mask register 10 a4 expansion interrupt clear register 10 a8 1800_0500 expansion interrupt pending register 11 b0 base + offset expansion interrupt mask register 11 b4 expansion interrupt clear register 11 b8 1800_0500 expansion pci interrupt pending register 12 c0 base + offset expansion pci interrupt mask register 12 c4 expansion pci interrupt clear register 12 c8 1800_0500 expansion interrupt pending register 13 d0 base + offset expansion interrupt mask register 13 d4 expansion interrupt clear register 13 d8 1800_0500 expansion interrupt pending register 14 e0 base + offset expansion interrupt mask register 14 e4 expansion interrupt clear register 14 e8 base address register function offset address effective address table 1.9 internal address mapping of ex pansion interrupt registers (part 2 of 2) rc32334 device overview rc32334 internal register map addresses and definitions 79rc32334/332 user reference manual 1 - 25 june 4, 2002 notes programmable i/o registers these registers allow i/o progr ammability between internal peri pheral and general purpose functions. register definitions and user operat ions are provided in chapter 15, programmable i/o (p io) controller. timer controller registers these registers provide user programmability between the rc32334?s real-time and time-slice clock functions. five dedicated timer functions are also programmed through the separate count, compare and control registers. register definiti ons and functional overview informati on is provided in chapter 16, timer controller. base address register function offset address effective address 1800_0600 pio data register 0 00 base + offset pio direction control register 0 04 pio effect select control register 0 08 pio new feature register 0 0c 1800_0610 pio data register 1 00 pio direction control register 1 04 pio effect select control register 1 08 pio new feature register 1 0c table 1.10 internal address mappi ng of programmable i/o registers base address register function offset address effective address 1800_0700 timer control register 0 (32 bits) 00 base + offset timer count register 0 04 timer compare register 0 08 1800_0710 timer control register 1 (32-bits) 00 base + offset timer count register 1 04 timer compare register 1 08 1800_0720 timer control register 2 (32-bits) 00 base + offset timer count register 2 04 timer compare register 2 08 1800_0730 timer control register 3 for watchdog (32-bits) 00 base + offset timer count register 3 for watchdog 04 timer compare register 3 for watchdog 08 1800_0740 timer control register 4 for cpu bustimeout (buserror) (16-bits) 00 base + offset timer count register 4 for cpu bustimeout 04 timer compare register 4 for cpu bustimeout 08 table 1.11 internal address mapping of ti mer controller registers (part 1 of 2) rc32334 device overview rc32334 internal register map addresses and definitions 79rc32334/332 user reference manual 1 - 26 june 4, 2002 notes uart control registers these registers enable uart functionality such as interrupt indication, data flow modes, and data receive/transmit formats. progra mming the pio controller (see c hapter 15) enables the rc32334?s two identical 16550 compatible uarts. uart registers ar e defined and described in more detail in chapter 17, uart controller. 1800_0750 timer control register 5 for ip bustimeout (buserror) (16-bits) 00 base + offset timer count register 5 for ip bustimeout 04 timer compare register 5 for ip bustimeout 08 1800_0760 timer control register 6 for dramrefresh (16- bits) 00 base + offset timer count register 6 for dramrefresh 04 timer compare register 6 for dramrefresh 08 1800_0770 timer control register 7 for warmreset (8-bits) 00 base + offset timer count register 7 for warmreset 04 timer compare register 7 for warmreset 08 base address register function offset address effective address uart 0 1800_0800 receiver buffer register / transmitter holding register, dlab = 0 00 base + offset interrupt enable register, dlab = 0 04 baud divisor latch, ls, dlab = 1 00 baud divisor latch, ms, dlab = 1 04 interrupt identity register / buffer control register 08 line control register 0c modem control register 10 line status register 14 modem status register 18 scratch register 1c table 1.12 internal address mapping of uart 0 registers base address register function offset address effective address table 1.11 internal address mapping of ti mer controller registers (part 2 of 2) rc32334 device overview rc32334 internal register map addresses and definitions 79rc32334/332 user reference manual 1 - 27 june 4, 2002 notes note: table 1.13 does not apply to the rc32332. serial peripheral interface registers these registers enable spi functionality. for more det ailed information, see chapter 18, ?serial periph- eral interface.? dma control registers these registers determine channel usage, data transfer modes, and descriptor ownership of the four general purpose dma channels. as programmed, eac h channel can move data between the source and destination ports, such as system memory, pci, or i/o devices. chapter 13 pr ovides detailed programming information for the dma registers. base address register function offset address effective address uart 1 1800_0820 receiver buffer register / transmitter holding regis- ter, dlab = 0 00 base + offset interrupt enable register, dlab = 0 04 baud divisor latch, 8 lsb, dlab = 1 00 baud divisor latch, 8 msb, dlab = 1 04 interrupt identity register / buffer control register 08 line control register 0c modem control register 10 line status register 14 modem status register 18 scratch register 1c table 1.13 internal address mapping of uart 1 registers base address register offset address effective address 1800_0900 serial peripheral clock divisor/prescalar register (spcnt) 00 base + offset serial peripheral control register (spcntl) 04 serial peripheral status register (spsr) 08 serial peripheral data i/o register (spdr) 0c table 1.14 internal address mapping of spi registers rc32334 device overview rc32334 internal register map addresses and definitions 79rc32334/332 user reference manual 1 - 28 june 4, 2002 notes base address register function offset address effective address dma channel 0 1800_1400 ch0 configuration register 00 base + offset ch0 base descriptor address register 04 ch0 current address register 08 ch0 status/blocksize register 10 ch0 source address register 14 ch0 destination address register 18 ch0 next descriptor address register 1c table 1.15 internal address ma pping of dma channel 0 registers base address register function offset address effective address dma channel 1 1800_1440 ch1 configurationregister 00 base + offset ch1 base descriptor address register 04 ch1 current address register 08 ch1 status/blocksize register 10 ch1 source address register 14 ch1 destination address register 18 ch1 next descriptor address register 1c table 1.16 internal address mapping of dma channel 1 registers base address register function offset address effective address dma channel 2 1800_1900 ch2 configuration register 00 base + offset ch2 base descriptor address register 04 ch2 current address register 08 ch2 status/blocksize register 10 ch2 source address register 14 ch2 destination address register 18 ch2 next descriptor address register 1c table 1.17 internal address mapping of dma channel 2 registers rc32334 device overview rc32334 internal register map addresses and definitions 79rc32334/332 user reference manual 1 - 29 june 4, 2002 notes pci interface control registers these registers configure system functions or modes and provide acce ss to local memory via the pci bus. more detailed register definitions and descriptions are provided in chapter 12, pci interface controller. base address register function offset address effective address dma channel 3 1800_1940 ch3 configuration register 00 base + offset ch3 base descriptor address register 04 ch3 current address register 08 ch3 status/blocksize register 10 ch3 source address register 14 ch3 destination address register 18 ch3 next descriptor address register 1c table 1.18 internal address mapping of dma channel 3 registers base address register function offset address effective address 1800_0500 pci controller interrupt pending register 11 b0 base + offset 1800_0500 pci controller interrupt mask register 11 b4 1800_0500 pci controller interrupt clear register 11 b8 1800_0500 cpu to pci mailbox interrupt pending register 12 c0 1800_0500 cpu to pci mailbox interrupt mask register 12 c4 1800_0500 cpu to pci mailbox interrupt clear register 12 c8 1800_0500 pci to cpu mailbox interrupt pending register 13 d0 1800_0500 pci to cpu mailbox interrupt mask register 13 d4 1800_0500 pci to cpu mailbox interrupt clear register 13 d8 1800_2000 new feature register 0a0 1800_2000 pci target control register 0a4 1800_2000 pci memory and i/o space 1 base register 0b0 1800_2000 pci memory and i/o space 2 base register 0b8 1800_2000 pci memory and i/o space 3 base register 0c0 1800_2000 pci memory and i/o space 4 base register 0c8 1800_2000 pci arbitration register 0e0 1800_2000 pci cpu space1 base register 0e8 1800_2000 pci cpu space 2 base register 0f4 1800_2000 pci cpu space 3 base register 100 table 1.19 internal address mapping of pci interface control registers (part 1 of 2) rc32334 device overview rc32334 internal register map addresses and definitions 79rc32334/332 user reference manual 1 - 30 june 4, 2002 notes 1800_2000 pci cpu space 4 base register 10c base + offset 1800_2000 pci configuration address register cf8 1800_2000 pci configuration data register cfc base address register function offset address effective address table 1.19 internal address mapping of pci interface control registers (part 2 of 2) notes 79rc32334/332 user reference manual 2 - 1 june 4, 2002 chapter 2 rc32300 cpu core introduction targeted to a variety of software intensive em bedded applications, the rc32334 is a member of the integrated device technology, inc. (idt) riscontroll er series of embedded micr oprocessors. it is based on the rc32300 cpu core. the riscore 32300 cpu core continues idt? s tradition of high-performance through high-speed pipelines, high-bandwid th caches and bus interface, mi ps application specific architec- tural extensions. the rc32334 supports a wide variety of embedded proc essor-based applications, such as communica- tions equipment (low-end routers, gatew ays, switches, cellular base stat ions) and digital consumer systems (internet appliances). performance overview the rc32334 brings riscore 4000 family performance levels to lower cost systems. high performance is preserved by retaining large on-chip two-way se t-associative caches, a st reamlined high-speed pipeline, high-bandwidth and facilities such as early restart for data cache misses. an array of development tools as well as integrated in-circuit emulation suppor t facilitates rapid develop- ment of rc32334-based systems, allowing a wide vari ety of customers to take advantage of the processor?s high-performance capabilities while main taining short time-to-market goals. also, being upwardly software compatible with the riscore 3000 fa mily, the rc32334 will serve in many of the same applications. the rc32334 also supports applications that require integer digital signal processing (dsp) functions. rc32300 cpu core features ? high-performance embedded 32-bit riscore 32300 microprocessor ? based on enhanced mips-ii risc architecture ? scalar 5-stage pipeline mini mizes branch and load delays ? enhanced mips-ii instruction set architecture ? mips-iv compatible conditional move instructions ? mips-iv superset pref (prefetch) instruction ? fast multiplier with atomic multiply-add, multiply-sub ? count leading zero/one instructions ? large, efficient on-chip caches ? separate 8kb instruction cache and 2kb data cache ? 2-way set associative ? write-back and write-thr ough support on a per page basis ? optional cache locking, with per line resolu tion, to facilitate deterministic response ? simultaneous instruction and data fetch in each clock cycle ? flexible rc4000 compatible mmu with 32-page tlb ? variable page size ? enhanced write algorithm support ? variable number of locked entries ? no performance penalty for address translation ? improved real-time support ? fast interrupt decode ? low-power operation ? active power management: powers down inactive units ? enhanced jtag interface for system debug using exte rnal, low-cost in-circuit emulator (ice) equip- ment rc32300 cpu core rc32300 cpu overview 79rc32334/332 user reference manual 2 - 2 june 4, 2002 notes ? on-chip debug port (compatible with ejtag standard) ? mips architecture ensures applications software co mpatibility throughout the riscontroller series of embedded processors, and availability of a broad range of complementary hardware and soft- ware products from third parties. rc32300 cpu overview the rc32300 cpu core has a level of integr ation designed for high-performance and high bandwidth computing. key elements of the cpu core are illustr ated in the block diagram provided in figure 2.1. an overview on these features follow s, with more detailed explanations provided in subsequent chapters. figure 2.1 rc32300 cpu core block cpu registers the rc32300 cpu core includes thirty-two general-pur pose 32-bit registers. t hese registers are used for scalar integer operations and address calculation. the register file consists of tw o read ports and two write ports, and it is fully bypassed to minimize oper- ation latency in the pipeline. figure 2.2 rc32300 registers two of the cpu general purpose register s have the following assigned functions: r0 is hardwired to a value of zero and can be used as the target register for any instruction whose result is to be discarded. r0 can also be used as a source when a zero value is required. system control coprocessor (cp0) 2kb d-cache, 2-set, clock enhanced jtag (ice interface) tlb lockable, write-back/ generation unit write-through rc32300 cpu bus interface unit 8kb i-cache, lockable 2-set, riscore4000 compatible w/ mmu riscore 32300 integer cpu core r0 r1 r2 r31 multiply and divide registers program counter 0 0 0 hi lo 0 general purpose registers pc ? ? ? ? r29 r30 31 31 31 31 rc32300 cpu core rc32300 cpu overview 79rc32334/332 user reference manual 2 - 3 june 4, 2002 notes r31 is used as an implicit return destination addre ss register by the jal and bal series of instruc- tions. also, two multiply/divide registers (hi/lo) store the product of integer multiply operations or the quotient (in lo) and remainder (in hi) of integer divide oper ations. the riscore 32300 cpu core does not have a program status word (psw) register, so the functi on traditionally covered by psw is handled by the cause and status registers in the system control coproces sor (cpo). cpo also has a number of special purpose registers that are used in conjunction with t he memory management system and during exception processing. the riscore 32300 implements the enhanced mips-ii instru ction set architecture (isa) whose features include: pref operation, with various hint subfields conditional move instructions mad, mul and msub instructions incorporated in t he integer multiply units, used to perform multi- ply accumulate and multiply subtract operations count leading ones (clo) and count leadi ng zeros (clz) instructions. these features come together to make the controll er well suited to applicat ions requiring the use of some dsp algorithms. configuration during hardware reset, the rc32300?s byte or dering is configurable into either a big-endian or little- endian convention. when configured as a big-endian system, byte 0 is always the most significant (left- most) byte in a word (see figure 2.3). however, when configured as a little-endian system, byte 0 is always the least significant (rightmost) byte in a word (see figure 2.4). figure 2.3 big-endian byte ordering convention figure 2.4 little-endian byte ordering convention big-endian byte ordering 31 24 23 16 15 8 7 0 89ab 4587 0123 higher address lower address word address 8 4 0 * most significant byte (msb) is at lowest address ** word is addressed by byte address of msb little-endian byte ordering 31 24 23 16 15 8 7 0 ba98 7654 3210 higher address lower address word address 8 4 0 * least significant byte (lsb) is at lowest address ** word is addressed by byte address of lsb rc32300 cpu core cp0 considerations 79rc32334/332 user reference manual 2 - 4 june 4, 2002 notes cp0 considerations cp0 is responsible for address translation as we ll as cache attribute and exception management, and in the mips architecture, cp0 functions are allowed to vary by implementation. the rc32334 implements an riscore 4000 family compatible cp0. specific det ails on the cp0 registers implemented by the rc32300 are provided in chapter 6, cpu exception processing. memory management unit (mmu) the rc32334?s mmu is modeled after the mmu found in the riscore 4000 family and includes the translation lookaside buffer (tlb). this mmu offers the following advantages, relative to the traditional riscore 3000 family mmu: variable page size enhanced write algorithm support mapping of a larger portion of the virtual address space variable number of locked entries on-chip instruction and data caches the rc32300 cpu core incorporates separate instruct ion (i-cache) and data caches (d-cache) that can be accessed in a single processor cycle. each ca che has its own 32-bit data path and can be accessed in the same pipeline clock cycle. the rc32300 cpu core supports a cache-locking f eature, which is imple- mented on a ?per-line basis,? enabling the system designer to maximize the system?s cache efficiency. power reduction mode the riscore 32300 is a static design and supports a wait instruction that is designed to signal the rest of the chip that execution and clocking should be hal ted, reducing system power consumption during idle periods. standby mode operation executing the wait instruction enables interrupts and enters standby mode. when the wait instruction finishes the w pipe-stage, if the bus is currently idle , the internal clocks will shut down, thus freezing the pipeline. the pll, internal timer, and some of the input pins (cpu_nmi_n, cpu_int_n[5:4], [2:0], cpu_coldreset_n) will continue to run. if the internal ip bus is not idle when the wait instruction finishes the w pipe-stage, the wait is treated as a nop. once the cpu enters standby mode, any interrupt, including the internally generated timer interrupt, wi ll cause the cpu to exit standby mode. notes 79rc32334/332 user reference manual 3 - 1 june 4, 2002 chapter 3 cpu instruction set overview introduction this chapter provides a general over view on the three cpu instruction set formats of the mips architec- ture: immediate, jump, and register. for descriptions of the new instruction sets implemented in this device, refer to appendix a, rc32300 cpu core enhancements to mips ii isa, in this manual. for more details on a specific cpu core instruction, refer to the idt mips microprocessor family software devel- oper?s guide, version 1.0 , december 1998 . cpu instruction formats each cpu instruction consists of a single 32-bit opcode, aligned on a word (4-byte) boundary. as shown in figure 3.1, there are three cpu instruction formats: immediate (i-type) jump (j-type) register (r-type) limiting instruction format types to three simpli fies instruction decoding (thus higher frequency opera- tions) and allows the compiler to synthesize more complicated (and less freq uently used) operations and addressing modes. figure 3.1 cpu instruction formats key to figure: op 6-bit operation code rs 5-bit source register specifier rt 5-bit target (source/destination) register or branch condition immediate 16-bit immediate value, branch displacement or address displacement target 26-bit jump target address 0 15 16 20 21 25 26 31 0 15 16 20 21 25 26 31 0 25 26 31 op rs rt immediate op target funct op rs rt 11 10 6 5 rd sa r-type (register) j-type (jump) i-type (immediate) cpu instruction set overview load and store instructions (i-type) 79rc32334/332 user reference manual 3 - 2 june 4, 2002 notes for all mips processors, system c ontrol is implemented as coprocesso r 0 (cp0), the system control coprocessor. in the mips architecture, coproc essor instructions are implementation dependent. for detailed descriptions of individual copr ocessor 0 instructions, refer to the idt mips microprocessor family software developer?s guide . load and store instructions (i-type) load and store are immediate (i-type) instructions that move data between memory and the general registers. the only addressing mode that load and store instructions directly support is base register plus 16-bit signed immediate offset . scheduling a load delay slot a load instruction that does not allow its result to be used by the instruction immediately following is called a delayed load instruction . the instruction slot immediately fo llowing this delayed load instruction is referred to as the load delay slot . in the rc32334 processor, the instruction immediat ely following a load instruction can request the contents of the loaded register; however, in such case s, hardware interlocks may insert additional real cycles. consequently, scheduling l oad delay slots can be desirabl e, both for performance and rc3000 processor family (e.g., r3051) compatibility. however, the scheduling of load delay slots is not absolutely required. defining access types access type indicates the size of an rc32334 processor dat a item to be loaded or stored, set by the load or store instruction opcode. access types are defined in the idt mips microprocessor family software developer?s guide . regardless of access type or byte ordering (endianness), the address gi ven specifies the low-order byte in the addressed field. for a big-endian configuration, t he low-order byte is the most-significant byte; for a little-endian configuration, the low-order byte is t he least-significant byte. the access type, together with the three low-order bi ts of the address, define the bytes accessed within the addressed doubleword, which is shown in table 3.1. only the combinations shown in this table are permitted. other combinations wi ll cause address error exceptions. access type mnemonic ( value ) low order address bits bytes accessed big endian (31..........0) byte little endian (31............0) byte 210 word ( 3 ) 0 0 0 0123 3210 triplebyte ( 2 ) 000012 210 001 123 321 halfword ( 1 ) 00001 10 010 23 32 byte ( 0 ) 0000 0 001 1 1 010 2 2 011 33 table 3.1 permitted address combinations cpu instruction set overview computat ional instructions (r-type and i-type) 79rc32334/332 user reference manual 3 - 3 june 4, 2002 notes computational instructio ns (r-type and i-type) computational instructions can be in either the register (r-type) or i mmediate (i-type) formats. in the r- type format, both operands are registers; in the i-type format, one operand is a 16-bit immediate. computational instructions perform arithmetic, logical, sh ift, multiply, and divide operations on register values and fit in the following four categories: alu immediate instructions three-operand register-type instructions shift instructions multiply and divide instructions operations with 32-bit operands operands to 32-bit operand opcodes must be in si gn-extended form. 32-bit operand opcodes include all non-doubleword operations, such as: add, addu, sub, subu, addi, sll, srl, sra, sllv, etc. the result of operations that use incorrec t sign-extended 32-bit values is unpredictable. cycle timing for multiply and divide instructions if necessary, rc32334 hardware interlocks to allow complete execution of the multiply and divide instructions. for example, mfhi and mflo instructi ons are interlocked so that any attempt to read or execute them prior to the completi on of previously issued multiply or divide instructions will be delayed. table 3.2 lists the number of processor cycles (pcycl es) required to resolve an interlock or stall between various multiply or divide instructions and a subsequent mfhi or mflo instruction. specific details on the mfhi or mflo instructions are provided in the idt mips microprocessor fa mily software developer?s guide . jump & branch instructions (j-type and r-type) jump and branch instructions change a program?s control flow. all jump and branch instructions occur with a delay of one instruction: the instruction imm ediately following the jump or branch (known as the instruction in the delay slot ) always executes while the target in struction is being fetched from storage. overview of jump instructions subroutine calls in high-level languag es are usually implemented with jump or jump and link instruc- tions, both of which are j-type instructions. in the j- type format, the 26-bit target address shifts left 2 bits and combines with the high-order 4 bits of the current program counter to form an absolute address. opcode operand size latency 1 1. latency refers to the number of cycles before a result is available. repeat 2 2. repeat refers to the number of cycles before an operation can be re- issued. stall 3 3. stall refers to the number of cycles that the cpu delays the pipeline. mult/u, mad/u, msub/u 16-bit 3 2 0 32-bit 4 3 0 mul 16-bit 3 2 1 32-bit 4 3 2 div, divu any 36 36 0 clz 32-bit 1 1 0 clo 32-bit 1 1 0 table 3.2 performance levels of mul/div and new instructions cpu instruction set overview sp ecial instructions (r-type) 79rc32334/332 user reference manual 3 - 4 june 4, 2002 notes returns, dispatches, and large cross-page jumps are usually implemented with the jump register or jump and link register instructions (both of which are r-type instructions that take the 32-bit or 64-bit byte address contained in one of t he general purpose registers). overview of branch instructions a branch instruction is a jump to a specified me mory location and has an architectural delay of one instruction. all branch instruction target addresses ar e computed by adding the address of the instruction in the delay slot to the 16-bit offset (shifts left 2 bits and is sign-extended to 32 bits). when a branch is taken, the instruction immediately following the branch instruction, in the branch delay slot, is executed before the branch to the target instru ction takes place. there are two versions of condi- tional branches, and each one treats the instruction in the delay slot differently. t he ?branch? instructions will execute the instruction in the delay slot, but the ?branch likely? instructions do not. if a conditional branch likely is not taken, the instruction in the delay slot is nullified. for r egular conditional branches, the delay slot is always executed. special instruct ions (r-type) special instructions allow the software to initiate traps . trap instructions cause exceptions conditionally based upon the result of a comparison. these special in structions are always r-ty pe. for more information about special instructions, refer to the i ndividual instruction as described in the idt mips microprocessor family software developer?s guide . exception instructions exception instructions are extensions to the mips isa and cause an exception that will transfer control to a software exception handler in the kernel. syst em call and breakpoint instructions cause exceptions unconditionally. for more information about specific except ion instructions, refer to the individual instruction as described in the idt mips microprocessor family software developer?s guide . coprocessor instructions (i-type) coprocessor instructions perform operations in their re spective coprocessors . coprocessor loads and stores are i-type, and coprocessor computati onal instructions have coprocessor-dependent formats. cp0 instructions perform operations specifically on t he system control coproces sor registers to manip- ulate the memory management and exception handling facilities of the processor. summary of cpu suppor ted instruction sets the tables that follow list instructions support ed by the rc32300 cpu core. load and store instructions are listed in table 3.3, arithmetic instructions (alu immediate) in table 3.4, arithmetic instructions (3- operand, r-type) in table 3.5, multiply, divide and d sp instructions are in table 3.6, jump and branch instructions are in table 3.7, shift instructions are in table 3.8, coprocessor instructions are in table 3.9, special instructions are listed in table 3.10, except ion and cp0 instructions are listed in table 3.11 and table 3.12. opcode description mips isa level lb load byte i lbu load byte unsigned i lh load halfword i lhu load halfword unsigned i lw load word i table 3.3 load and store instructions (part 1 of 2) cpu instruction set overview summar y of cpu supported instruction sets 79rc32334/332 user reference manual 3 - 5 june 4, 2002 notes lwl load word left i lwr load word right i sb store byte i sh store halfword i sw store word i swl store word left i swr store word right i ll load linked ii sc store conditional ii sync sync ii pref prefetch iv opcode description mips isa level addi add immediate i addi add immediate unsigned i slti set on less than immediate i sltiu set on less than immediate unsigned i andi and immediate i ori or immediate i xori exclusive or immediate i lui load upper immediate i table 3.4 arithmetic instructions (alu immediate) opcode description mips isa level add add i addu add unsigned i sub subtract i subu subtract unsigned i slt set on less than i sltu set on less than unsigned i and and i or or i xor exclusive or i nor nor i movn move conditional on not zero iv movz move conditional on zero iv table 3.5 arithmetic instructions (3-operand, r-type) opcode description mips isa level table 3.3 load and store instructions (part 2 of 2) cpu instruction set overview summar y of cpu supported instruction sets 79rc32334/332 user reference manual 3 - 6 june 4, 2002 notes opcode description mips isa level mult multiply i multu multiply unsigned i div divide i divu divide unsigned i mfhi move from hi i mthi move to hi i mflo move from lo i mtlo move to lo i mul multiply with destination register writeb ack rc32364, rc4650, riscore 32300, rc64574/575 mad multiply add rc32364, rc4650, riscore 32300, rc64574/575 madu multiply add unsigned rc32364, rc4650, riscore 32300, rc64574/575 msub multiply subtract riscore 32300, rc32364, rc64574/575 msubu multiply subtract unsigned riscore 32300, rc32364, rc64574/575 clz count leading zeros riscore 32300, rc32364, rc64574/575 clo count leading ones riscore 32300, rc32364, rc64574/575 table 3.6 multiply, divide and dsp instructions opcode description mips isa level jjump i jal jump and link i jr jump register i jalr jump and link register i beq branch on equal i bne branch on not equal i blez branch on less than or equal to zero i bgtz branch on greater than zero i bltz branch on less than zero i bgez branch on greater than or equal to zero i bltzal branch on less than zero and link i bgezal branch on greater than or equal to zero and link i bczt branch on coprocessor z true i bczf branch on coprocessor z false i beql branch on equal likely ii bnel branch on not equal likely ii blezl branch on less than or equal to zero likely ii bgtzl branch on greater than zero likely ii bltzl branch on less than zero likely ii table 3.7 jump and branch instructions (part 1 of 2) cpu instruction set overview summar y of cpu supported instruction sets 79rc32334/332 user reference manual 3 - 7 june 4, 2002 notes bgezl branch on greater than or equal to zero likely ii bltzall branch on less than zero and link likely ii bgezall branch on greater than or equal to zero and link likely ii bcztl branch on coprocessor z true likely ii bczfl branch on coprocessor z false likely ii opcode description mips isa level sll shift left logical i srl shift right logical i sra shift right arithmetic i sllv shift left logical variable i srlv shift right logical variable i srav shift right arithmetic variable i table 3.8 shift instructions opcode description mips isa level lwcz load word to coprocessor z i swcz store word from coprocessor z i mtcz move to coprocessor z i mfcz move from coprocessor z i ctcz move control to coprocessor z i cfcz move control from coprocessor z i copz coprocessor operation z i table 3.9 coprocessor instructions opcode description mips isa level syscall system call i break break i dret debug exception return rc32364, riscore 32300 sdbbp software debug breakpoint rc32364, riscore 32300 table 3.10 special instructions opcode description mips isa level table 3.7 jump and branch instructions (part 2 of 2) cpu instruction set overview summar y of cpu supported instruction sets 79rc32334/332 user reference manual 3 - 8 june 4, 2002 notes opcode description mips isa level tge trap if greater than or equal ii tgeu trap if greater than or equal unsigned ii tlt trap if less than ii tltu trap if less than unsigned ii teq trap if equal ii tne trap if not equal ii tgei trap if greater than or equal immediate ii tgeiu trap if greater than or equal immediate unsigned ii tlti trap if less than immediate ii tltiu trap if less than immediate unsigned ii teqi trap if equal immediate ii tnei trap if not equal immediate ii table 3.11 exception instructions opcode description mips isa level mtc0 move to cp0 i mfc0 move from cp0 i tlbr read indexed tlb entry i tlbwi write indexed tlb entry i tlbwr write random tlb entry i tlbp probe tlb for matching entry i cache cache operation riscore 4000, riscore 32300 eret exception return riscore 4000, riscore 32300 wait enter standby mode riscore 4000, riscore 32300 table 3.12 cp0 instructions notes 79rc32334/332 user reference manual 4 - 1 june 4, 2002 chapter 4 cpu pipeline architecture introduction the riscore 32300 uses a 5-stage instruction pipeli ne, similar to the riscore 3000 and riscore 4000 families. the simplicity of this pipeline enables the processor to achieve high frequency while minimizing device complexity. the riscore 32300 core s upports limited out-of-order execution. the riscore 32300 pipeline also performs virtual-to- physical address translation in parallel with cache access. additional enhancements such as prefetch operations and two new inst ructions allow the rc32334 to be a lower cost and lower power device than super-scalar or super-pipelined processors. the 5-stage instruction pipeline is illustrated in figure 4.1. figure 4.1 instruction pipeline stages cpu pipeline stages this section describes each of the phases of the five pipeline stages. each stage has 2 phases: 1i - instruction fetch, phase one 2i - instruction fetch, phase two 1r - register fetch, phase one i 0 1i 2i 1r 2r 1a 2a 1d 2d 1w 2w i 1 1i 2i 1r 2r 1a 2a 1d 2d 1w 2w i 2 1i 2i 1r 2r 1a 2a 1d 2d 1w ??? i 3 1i 2i 1r 2r 1a 2a 1d ??? i 4 1i 2i 1r 2r 1a ??? one cycle key to figure: 1i-1r instruction cache access 2r instruction decode 1i-2i instruction virtual to physical address translation 1a-2a integer add, logical, shift 2a-2d data cache access and load align 1a data virtual address calculation 1d-2d data virtual to physical address translation 2a store align 2r register file read 1a branch decision 2r bypass calculation 2w register file write cpu pipeline architecture cpu pipeline stages 79rc32334/332 user reference manual 4 - 2 june 4, 2002 notes 2r - register fetch, phase two 1a - execution, phase one 2a - execution, phase two 1d - data fetch, phase one 2d - data fetch, phase two 1w - write back, phase one 2w - write back, phase two 1i - instruction fetch, phase one the instruction address transla tion begins during the 1i phase. 2i - instruction fetch, phase two during the 2i phase, the instruction cache fetc h begins and the instruction address translation continues. 1r - register fetch, phase one during the 1r phase, the following occurs: the instruction cache fetch finishes. the instruction cache tag is checked against the physical page frame number obtained from the address translation. 2r - register fetch, phase two during the 2r phase, the following occurs: the instruction decoder decodes the instruction. any required operands are fetched from the register file. make a decision to either issue or slip (for an interlock condition). for a branch, the branch address is calculated. 1a - execution, phase one during the 1a phase, one of the following occurs: any result from the a or d stages are bypassed. the arithmetic logic unit (alu) starts the in teger arithmetic, logical or shift operation. the alu calculates the data virtual address for load and store instructions. the alu determines whether the branch condition is true. 2a - execution, phase two during the 2a phase, one of the following occurs: the integer arithmetic, logical or shift operation will complete. a data cache access will start. store data is shifted to the specified byte position(s). the data virtual to physical address translation will start. 1d - data fetch, phase one during the 1d phase, one of the following occurs: the data cache access will continue. the data address translation completes. cpu pipeline architecture branch delay 79rc32334/332 user reference manual 4 - 3 june 4, 2002 notes 2d - data fetch, phase two during the 2d phase, the data cache access will finish and the data is then shifted down and extended. the data cache tag is checked against the physical address for any data cache access. 1w - write back, phase one the processor uses this phase internally to resolv e all exceptions in preparation for the register file write. 2w - write back, phase two for register-to-register and load instru ctions, the result is written back to the register file during the 2w stage. branch instructions perfo rm no operation during this stage. figure 4.2 shows the activities o ccurring during each alu pipeline st age, for load, store, and branch instructions. figure 4.2 pipeline activities branch delay the cpu pipeline has a branch delay of one cycle and a load delay of one cycle. the one-cycle branch delay is a result of the branch decision logic operat ing during the 1a pipeline phase of the branch instruc- tion. this allows the branch target address calculated in the previous phase to be used for the instruction access in the following ?1i? phase. branch 1i 2i 1r 2r 1a 2a 1d 2d 1w 2w itm icd ica dcad dcaa dcla dtc rf idec bac ex1 dva sa wb itc wb ifetch and decode alu load/store ex2 stage clock key to figure: icd instruction cache address decode ica instruction cache array access itm instruction translation match rf register operand fetch itc instruction tag check ex1 operation stage 1 idec instruction decode wb write back to register file ex2 operation stage 2 dcad data cache address decode dva data virtual address calculation dcla data cache load align dcaa data cache array access dtm data translation match dtc data tag check sa store align dcw data cache write bac branch address calculation dtm dcw cpu pipeline architecture load delay 79rc32334/332 user reference manual 4 - 4 june 4, 2002 notes the pipeline will begin the fetch of the branch path as well as the fall-through path in the cycle following the delay slot. after the branch decisi on is made, the processor will continue with the fetch of either the branch path (for a taken branch) or the fall-through path (for the non-taken branch). figure 4.3 illustrates the branch delay. figure 4.3 cpu pipeline branch delay load delay the completion of a load at the end of the 2d pipeline phase produces an operand that is available for the 1a pipeline phase of the instruction following the load delay slot. figure 4.4 shows the load delay of one pipeline cycle. figure 4.4 cpu pipeline load delay interlock and exception handling when cache misses or exceptions occur or w hen data dependencies are detected, smooth pipeline flow is interrupted. these interrupti ons are either handled through hardwar e or software methods. software- managed interruptions are known as exceptions; hardware-handled inte rruptions?such as cache misses? are referred to as interlocks and oc cur as either stalls or slips. resolving a stall requires halting t he pipeline; slips require the back end of the pipeline to advance while the front end of the pipeline is held static. during all active instructions, exception and interloc k conditions are checked for at each pipeline cycle. because each exception or interloc k condition corresponds to a particula r pipeline stage, a condition can be traced back to the particular instruction in the except ion/interlock stage. for instance, a reserved instruc- tion (ri) exception is raised in the execution (a) stage. 1i 2i 1r 2r 1a 2a 1d 2d 1w 2w 1i 2i 1r 2r 1a 2a 1d 2d 1w 2w 1i 2i 1r 2r 1a 2a 1d 2d 1w 2w 1i 2i 1r 2r 1a 2a 1d 2d 1w 2w one cycle one cycle one cycle one cycle one cycle branch delay * branch and fall-through address calculated ** address selection made * ** 1i 2i 1r 2r 1a 2a 1d 2d 1w 2w 1i 2i 1r 2r 1a 2a 1d 2d 1w 2w 1i 2i 1r 2r 1a 2a 1d 2d 1w 2w one cycle one cycle one cycle one cycle one cycle load delay cpu pipeline architecture interlock and exception handling 79rc32334/332 user reference manual 4 - 5 june 4, 2002 notes exception conditions when an exception condition occurs, the relevant in struction and all instructions that follow are cancelled. accordingly, any sta ll conditions?and any later exception conditions that may have referenced this instruction?are inhibited; there is no benefit in servicing stalls for a cancelled instruction. when an exceptional condition is detected for an instru ction, the rc32334 kills it and all instructions that follow. when this instruction reaches the w stage, the exception flag causes it to write various cp0 regis- ters with the exception state, change the current pc to the appropriate exception vector address, and clear the exception bits of earlier pipeline stages. this implementation allows all preceding instructi ons to complete execution and prevents all subse- quent instructions from completing. thus, the value in the epc is sufficient to restart execution. it also ensures that exceptions are taken in the order of ex ecution; an instruction taking an exception may itself be killed by an instruction further down the pipeli ne that takes an exception in a later cycle. figure 4.5 shows the exception detection procedure (f or example, a reserved instruction exception). figure 4.5 exception detection stall conditions stalls are used to stop the pipeli ne for conditions detected after the r pipe-stage. when a stall occurs, the processor will resolve the condition and then the pipeline will continue. figure 4.6 illustrates a data cache miss stall. figure 4.6 data cache miss 1i 2i 1r 2r 1a 2a 1d 2d 1w 2w 1i 2i 1r 2r 1a 2a 1d 2d 1w 2w 1i 2i 1r 2r 1a 2a 1d 2d 1w 2w 1i 2i 1r 2r 1a 2a 1d 2d 1w 2w 1i 2i 1r 2r 1a 2a 1d 2d 1w 2w exc i1 i2 i3 exception vector exception vector address kill ira d ww www iradd dddw iraa aaadw irr rrradw detect cache miss 12 3 4 1 2 3 4 start moving dirty cache line data to write buffer get first doubleword into cache and restart pipeline load remainder of cache line into cache ... ... ... ... cpu pipeline architecture interlock and exception handling 79rc32334/332 user reference manual 4 - 6 june 4, 2002 notes as shown, the data cache miss is detected in the d pipe stage. if the cache line to be replaced is dirty? the w bit is set?the data is moved to t he internal write buffer in the next cycle. the first doubleword of data is returned to the ca che in 3 and the pipeline will then restart. the remainder of the cache line is returned in the s ubsequent cycles. the data to be written back will be returned to memory some time after the entire new cache line is returned. slip conditions during the 2r and 1a pipe-stages, inter nal logic will determine whether it is possible to start the current instruction in this cycle. if all of the source operands are available (either from the register file or via the internal bypass logic) and all the hardware resources nece ssary to complete the instruction will be available at the necessary time(s), then the instruction ?i ssues?; otherwise, the instruction will ?slip?. slipped instructions are retried on subsequent cycles until they issue. the back end of the pipeline (stages d and w) will advance normall y during slips in an attempt to resolve the conflict. ?nops? will be inserted into the bubble in the pipeline. instructions killed by branch likely instru ctions, eret or exceptions will not cause slips. figure 4.7 shows an instruction cache miss. figure 4.7 instruction cache miss as shown in figure 4.7, instruction cache misses ar e detected in the r stage and the pipeline slips in its a stage. there can never be a write-back required fo r an instruction cache miss since dirty data can not exist in the i cache. writes are not allowed to the i-cache. note that early restart is not employed for instruction cache misses. the requested cache line will be loaded into the ca che in its entirety and, after that, the pipeline will restart. i rrrrr a dw iradw iradw detect cache miss 1 23 1 2 3 get entire cache line into cache continue pipeline iradw iradw iradw *nop *nop *nop *nop *nop - inserted nop instructions adw radw w dw cycle issue slip issue slip slip slip issue issue issue previous instructions notes 79rc32334/332 user reference manual 5 - 1 june 4, 2002 chapter 5 memory management introduction the memory management unit (mmu) of the rc32334 is modeled after the mmu found in the r4000 families and generates typical translati on lookaside buffer (tlb) exceptions such as tlb refill, tlb invalid, and tlb modified to the integer unit and offers the fo llowing advantages (relative to the traditional 32-bit r3000 style mmu): variable page size enhanced write algorithm support mapping of a larger portion of the virtual address space variable number of locked entries virtual-to-physical address translation figure 5.1 illustrates the virtual-to-physical address translation of a 32-bit virtual address. the top section of the drawing shows a virtual addres s with a 12-bit?or 4kbyte?page size labelled offset . the remaining 20 bits of the address represent the virtual page number (vpn) and index the 1m-entry page table. the lower section of the drawing shows a virtual address with a 24-bit?or 16mbyte?page size labelled offset . the remaining 8 bits of the address represent the vpn and index a 256-entry memory-resident page table. figure 5.1 overview of a 32-b it virtual address translation 28 11 0 20 12 29 31 vpn offset 32 39 asid 8 virtual address with 1m (2 20 ) 4-kbyte pages 23 0 8 24 offset 39 virtual address with 256 (2 8 )16-mbyte pages 8 bits = 256 pages 20 bits = 1m 12 asid 8 28 29 31 32 vpn 24 virtual-to- physical transla- tion in tlb bits 31, 30 and 29 of the virtual address select user, super- visor, or kernel address spaces. offset passed unchanged to physical memory virtual-to-physical- translation in tlb tlb tlb 31 0 pfn offset 32-bit physical address offset passed unchanged to physical memory. memory management tlb management 79rc32334/332 user reference manual 5 - 2 june 4, 2002 notes tlb management for fast virtual-to-physical addres s decoding, the rc32334 tlb is a fully associative on-chip memory device that contains 16 entries, to provide mapping to 16 odd and even page pairs of sizes varying from 4 kbytes to 16 mbytes. each entry logically occupies a portion of a 128-bit frame work. each field of a tlb entry has a corresponding field in the entryhi, entrylo0, entrylo1, or pagemask registers. the rc32334?s tlb also contains information to control the cache coherency protocol for each page. specifically, each page has attribute bits to det ermine whether the coherenc y algorithm is uncached, noncoherent write-back, or non-coherent write-through no write-allocate. figure 5.2 tlb register format field description mask page comparison mask vpn2 virtual page number divided by two (maps to two pages) asid address space id g global. if this bit set, then ignore the asid pfn page frame number. upper bit of physical address c specifies the cache algorithm to be used, as shown below: d dirty bit. this bit serves as a ?write protect? bit v valid bit. it set, tlb is valid. otherwise a tlb miss occurs mcat memory controller attributes. reserved in rc32334 and must be written as ?0?. table 5.1 tlb register field descriptions mask 127 121 120 109 108 96 vpn2 g _ asid 95 77 76 75 72 71 64 712 13 19 1 48 _ pfn c d v _ 63 58 57 38 37 35 34 33 32 6 20 3 1 1 1 _ pfn c dv _ 6 20 3 111 31 26 25 6 532 0 1 mcat mcat c value page coherency attribute 0 cacheable, noncoherent, write-through, no write allocate 1 cacheable, noncoherent, write-through, write allocate 2 uncached 3 cacheable, noncoherent, write-back 4:7 reserved memory management mmu register descriptions 79rc32334/332 user reference manual 5 - 3 june 4, 2002 notes mmu register descriptions the cp0 registers required to implement the rc32334 memory management unit are listed in table 5.2. for each register, format illustrations and complete descriptions follow the table. index register (0) the index register is a 32-bit, read/write r egister containing six bits to index an entry in the tlb. the high-order bit of the regist er shows the success or fa ilure of a tlb probe (tlbp) instruction. the index register also specifies the tlb entry affected by tlb read (tlbr) or tlb write index (tlbwi) instructions. note that the rc32334 contains a 16 entry tlb, while the index register contai ns the capability to point to 64 tlb entries. in programming, the value written to the index register must be in the valid range of the number of entries of the current device. rc32334 implements additional bi ts in anticipation of derivative pr oducts. figure 5.3 shows the format of the index register; table 5.3, which follows the figure, describes the contents of the index register fields. figure 5.3 index register format number register description 0 index programmable pointer into tlb array 1 random pseudorandom pointer into tlb array (read only) 2 entrylo0 low half of tlb entry for even virtual page (vpn) 3 entrylo1 low half of tlb entry for odd virtual page (vpn) 4 context pointer to kernel virtual page table entry (pte) 5 pagemask tlb page mask to support variable page size. 6 wired number or wired tlb entries 8 badvaddr bad virtual address 10 entry hi holds the high-order bits of a tlb entry for tlb read and write oper- ations and is accessed by the tlb probe, tlb write random, tlb write indexed, and tlb read indexed instructions. table 5.2 rc32334 mmu registers field description p probe failure. set to 1 when the previous tlbprobe (tlbp) instruction was unsuccessful. index index to the tlb entry affected by the tlbread and tlbwrite instructions 0 reserved. must be written as zeroes, returns zeroes when read. table 5.3 index register field descriptions 31 1 30 6 5 0 25 6 index p 0 memory management mmu register descriptions 79rc32334/332 user reference manual 5 - 4 june 4, 2002 notes random register (1) the random register is a read-only regist er of which 4 bits index an entry in the tlb. this register decrements as each instruction executes, and it s values range between an upper and a lower bound, as follows: a lower bound is set by the number of tlb entries reserved for exclusive use by the operating sys- tem (the contents of the wired register). an upper bound is set by the total number of tlb entries. thus the upper bound is 15 (the tlb entries are numbered from 0 to 15). note: the rc32334 implements this register differently from the 64-bit family of riscontrollers. the rc4000, rc5000, and rc645xx cpus count both valid and invalid instructions. however, the rc32334 counts only valid instructions. the random register specifies the entry in the tlb that is affected by the tlb write random instruc- tion. the register does not need to be read for this purpos e (it is implicit in the instruction itself); however, the register is readable to verify proper operation of the processor. to simplify testing, the random register is set to the value of the upper bound upon system reset. this register is also set to the upper bound when the wired register is written. figure 5.4 shows the format of the random register. table 5.4 describes the contents of the random register fields. figure 5.4 random register format entrylo0 (2), and entrylo1 (3) registers the entrylo register consists of two regi sters with identical formats: entrylo0 is used for even virtual pages. entrylo1 is used for odd virtual pages. the entrylo0 and entrylo1 registers are read/write register s. they hold the physical page frame number (pfn) of the tlb entry for even and odd pages, respectively, when performing tlb read and write operations. figure 5.5 shows the format of this register. table 5.5 provides descriptions for the fields of this register. figure 5.5 entrylo0 and entrylo1 register formats field description random tlb random index 0 reserved. must be written as zeroes, and returns zeroes when read. table 5.4 random register field descriptions 31 43 0 28 4 random 0 d 31 0 20 pfn 26 25 6 cv 311 1 2 3 5 6 g 1 0 memory management mmu register descriptions 79rc32334/332 user reference manual 5 - 5 june 4, 2002 notes the tlb page coherency attribute ( c ) bits specify whether referenc es to the page should be cached. if cached, the algorithm selects between several coherency attributes. table 5.6 lists the coherency attributes that can be selected by the c bits. context register (4) the context register is a read/write register that contai ns the pointer to an entry in the page table entry (pte) array. this array is an operating system data st ructure that stores virtual -to-physical address transla- tions. when there is a tlb miss, the cpu loads the tl b with the missing translation from the pte array. normally, the operating system uses the context register to address the current page map that resides in the kernel-mapped segment. the context register duplicates some of the information provided in the badvaddr register, but the information is arranged in a form that is more useful for a software tlb excep- tion handler. figure 5.6 illustrates the format of the context register. table 5.7 provides the descriptions of the context register fields. figure 5.6 context register format field description pfn page frame number: the upper bits of the physical address. c specifies the tlb page coherency attribute. d dirty. if this bit is set, the page is marked as dirty and, therefore, writable. this bit is actually a write- protect bit that software can use to prevent alteration of data. v valid. if this bit is set, it indicates that the tlb entry is valid; otherwise, a tlbl or tlbs miss occurs. g global. if this bit is set in both lo0 and lo1, then the processor ignores the asid during tlb lookup. 0 reserved. must be written as zeroes, returns zeroes when read. table 5.5 entrylo0 and entrylo1 register field descriptions c value page coherency attribute 0 cacheable, noncoherent, write-through, no write allocate 1 cacheable, noncoherent, write-through, write allocate 2 uncached 3 cacheable, noncoherent, write-back 4:7 reserved table 5.6 tlb page coherency attributes field description badvpn2 this field is written by hardware on a miss. it contains the virtual page number (vpn) pair of the most recent virtual address that did not have a valid translation. ptebase this field is a read/write field for use by the operating system. it is normally written with a value that allows the operating system to use the context register as a pointer into the current pte array in memory. table 5.7 context register field descriptions 23 22 4 3 31 0 9 ptebase badvpn2 19 4 0 memory management mmu register descriptions 79rc32334/332 user reference manual 5 - 6 june 4, 2002 notes the 19-bit badvpn2 field contains bits 31:13 of the virtual address that caused the tlb miss. bit 12 is excluded because a single tlb entry maps to an even /odd page pair. for a 4-kbyte page size, this format can directly address the pair-table of 8-byte ptes. for other page and pte sizes, shifting and masking this value produces the appropriate address. pagemask register (5) the pagemask register is a read/write register used for r eading from or writing to the tlb; it holds a comparison mask that sets the variable page size fo r each tlb entry, as shown in the following table. tlb read and write operations use this register as either a source or a destination. when virtual addresses are presented for translation into physical address, the corresponding bits in the tlb identify which virtual address bits, among bits 24:13, are to be used in the comparison. when the mask field is not one of the values shown below, the operation of the tlb is undefined. figure 5.7 pagemask register format note: for the rc32334 the memory controller attri butes (mcat) fields perform no user valid function. for this device, these bit fields must be written as ?0?. wired register (6) the wired register is a read/write register that specifies the boundary between the wired and random entries of the tlb, as shown in figure 5.8. ?w ired? entries are nonreplaceable entries, which cannot be overwritten by a tlb write random operation. ?random? entries can be overwritten. thus, the wired register specifies the smallest va lue taken by the random register. note: the index register is not affected by the wired register. the index register can still point to and be used to overwrite either ?random? or ?wired? tlb entries. pagesize bit 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 4 kbytes 0 0 0 0 0 0 0 0 0 0 0 0 16 kbytes 0 0 0 0 0 0 0 0 0 011 64 kbytes 0 0 0 0 0 0 0 01111 256 kbytes 0 0 0 0 0 0111111 1 mbyte 0 0 0 011111111 4 mbytes 0 01111111111 16 mbytes 111111111111 field description mask page comparison mask mcat memory controller attributes. table 5.8 pagemask register field descriptions 12 31 13 0 mask 7 25 24 13 12 mcat mcat memory management mmu register descriptions 79rc32334/332 user reference manual 5 - 7 june 4, 2002 notes figure 5.8 diagram showing range s of wired and random entries the wired register is set to 0 upon system reset. wr iting to this register also sets the random register to the value of its upper bound (see random register format in figure 5.4 and table 5.4). figure 5.9 shows the format of the wired register, and table 5.9 lists the contents of this register?s fields. figure 5.9 wired register format note that the riscore 32300 cpu core contains a 16 entry tlb and that the wired register contains the capability of indicating up to 64 tlb entries. in programmi ng, the value written to t he wired register must be within the valid range of the number of entries of the cu rrent device. for future versions of this core, the riscore 32300 cpu core implements additional bits. bad virtual address register (badvaddr) (8) the bad virtual address register ( badvaddr ) is a read-only register that displays the most recent virtual address that caused one of the following exceptions: address error (for example, unaligned access) tlb invalid tlb modified tlb refill virtual coherency data access virtual coherency instruction fetch the processor does not write to the badvaddr register when the exl bit in the status register is set to 1. figure 5.10 shows the format of the badvaddr register. field description wired tlb wired boundary (the number of wired tlb entries) 0 reserved. must be written as zeroes, and returns zeroes when read. table 5.9 wired register field descriptions 15 wired range of ?random? entries 0 tlb register range of ?wired? entries 31 65 0 26 6 wired 0 memory management kernel/user operating modes and addressing 79rc32334/332 user reference manual 5 - 8 june 4, 2002 notes figure 5.10 bad virtual addr ess register (badvaddr) format note: the badvaddr register does not retain information fo r bus errors, since bus errors are not addressing errors. entryhi register (10) the entryhi register holds the high-order bits of a tlb entry for tlb read and write operations and is accessed by the tlb probe, tlb write random, tlb wr ite indexed, and tlb read indexed instructions. when either a tlb refill, tlb invalid, or tlb modified exception occurs, the entryhi register is loaded with the virtual page number pair (vpn2) and the asid of the virtual address that did not have a matching tlb entry. table 5.10 shows the entry hi register format and lists the field content descriptions. figure 5.11 entryhi register format kernel/user operating modes and addressing the rc32300 cpu core supports both the kernel and user operating modes. the operating system uses kernel mode for privileged pr ograms; user mode executes non- privileged programs. the cpu enters kernel mode whenever an exception occurs and remains in this mode until the eret (exception return) instruction is executed. user mode the cpu is in user mode when the stat us register has the following values: um bit is 1 exl bit is 0 erl bit is 0 while in user mode, a single, uniform virtual addre ss space of 2 gbytes is available for the user?s program. all references to th is address space are mapped by t he virtual address mapping mechanism described earlier. the cacheability is contro lled by ?cache mode? bits in the tlb. field description vpn2 virtual page number divided by two (maps to two pages). asid address space id field. an 8-bit field that lets multiple processes share the tlb; each process has a distinct mapping of otherwise identical virtual page numbers. 0 reserved. must be written as zeroes, returns zeroes when read. table 5.10 entryhi register field content descriptions 31 0 32 bad virtual address 31 vpn2 19 0 5 8 asid 12 13 87 0 memory management kernel/user operating modes and addressing 79rc32334/332 user reference manual 5 - 9 june 4, 2002 notes figure 5.12 illustration of rc32334 user mode address space kernel mode the cpu is in kernel mode when t he status register contains any one of the following bit-settings: um bit is 0 exl bit is 1 erl bit is 1 while in kernel mode, the virtual address spac e is partitioned into the following segments: kuseg this virtual address space is selected if the most significant bit of the virtual address is cleared. this space covers the full 2 gbytes of the cu rrent user address space. the virtual address is extended with the contents of the asid field to form unique virtual addresses. kseg0 this virtual address space is selected if the most significant three bits of virtual address are 100 2 . references to kseg0 are not ?mapped?; the ph ysical address is calculated by subtracting 0x8000_0000 from the virtual address. cacheability and coherency are controlled by the k0c field of the configuration register. kseg1 this virtual address space is selected if the most significant three bits of virtual address are 101 2 . references to kseg1 are not mapped; the physi cal address is calculated by subtracting 0xa000_0000 from the virtual address. caches are alwa ys disabled for accesses to this space, and physical memory (or memory-mapped i/o devic e registers) are accessed directly. kseg2 this virtual address space is selected if the most significant 8 bits of virtual address are from c0 16 to fe 16 . this space covers the upper 1008 mbytes of ker nel virtual address space. the virtual address is extended with the contents of the asid field to form unique virtual addresses. these addresses are translated to a physical address through the tlb. on-chip/ice registers (if the configur ation register bit 3 is set to 0) the upper-most 16 mbytes of the virtual address is reserved for memory-mapped on-chip registers and in-circuit emulator space. on-chip memory controller and peripheral have their register set mapped into this address space. if the configuration register bit 3 is set to 1, this space is considered as kseg2. 2gb translated address error 0x0000 0000 0x7ffff ffff 0x8000 0000 0xffff ffff useg rc32334 user mode memory management kernel/user operating modes and addressing 79rc32334/332 user reference manual 5 - 10 june 4, 2002 notes figure 5.13 illustration of rc32334 kernel mode address space for complete field and content descriptions as well as virtual address locations for the port width and bus turnaround control registers, re fer to chapter 8 of this manual. 16mb uncached, unmapped 1008 mb mapped, cached 512 mb uncached, unmapped 512 mb cached, unmapped 2gb mapped, cached 0x0000_0000 0x7fff_ffff 0x8000_0000 0x9fff_ffff 0xa000_0000 0xbfff_ffff 0xc000_0000 0xfeff_ffff 0xff00_0000 0xffff_ffff on-chip registers/ice kseg2 kseg1 kseg0 kuseg rc32334 kernel mode (if config [3] is0) notes 79rc32334/332 user reference manual 6 - 1 june 4, 2002 chapter 6 cpu exception processing introduction the cpu exception process begins when the processo r receives and detects exceptions from sources such as address translation errors, arithmetic overflows, i/o interrupts, and system calls. once an interrupt is detected, the processor suspends the normal instruction sequence and enters kernel mode (information on system operating modes is located in chapter 5). t he processor then disables interrupts and forces execution of a software excepti on processor (known as a handl er), which is located at a fixed address. the handler may save the context of the processor? including the program count er contents, the current operating mode (user or kernel mode), and the interrupt status (enabled or disabl ed)?so it can be restored when the exception has been serviced. the rc32300 cpu core supports the following basic exc eptions, which are listed from the highest to the lowest priority order: reset in-circuit emulation soft reset nonmaskable interrupt (nmi) address error caused by instruction fetch watch exception caused by instruction fetch cache error caused by instruction fetch bus error caused by instruction fetch integer overflow, trap, system call, breakpoin t, reserved instruction, coprocessor unusable address error caused by data access cache error caused by data access watch exception caused by data access bus error caused by data access interrupt exception processing registers support for the basic exceptions listed above is implemented through the cp 0 exception processing registers, which assist by retaini ng address, cause and status information. for example, when an exception oc curs, the cpu loads register 14?the exception program counter (epc) register?with a location from which executi on can restart after the exception has been handled. the restart location loaded into the epc register is either the address of the instruction that caused the excep- tion or the address of the branch instruction immediat ely preceding the delay slot, if the instruction was executing in a branch delay slot. a list of basic cp0 registers is given in table 6.1. following the table, a brief operational description of each exception register is provided. those listed as mmu registers are discu ssed further in chapter 5, ?memory management.? cpu exception processing exception processing registers 79rc32334/332 user reference manual 6 - 2 june 4, 2002 notes count register (9) the count register is a read/write register that acts as a timer, incrementing at a constant rate?half the maximum instruction issue rate?whether or not an instru ction is executed, retired, or any forward progress is made through the pipeline. this register can be written to fo r either diagnostic purposes or system initialization; for example, to synchronize processors. figure 6.1 shows the format of the count register. figure 6.1 count register format number register description 0 - 8 ___ used for mmu registers. (see chapter 5 for register descriptions) 9 count timer count 10 ___ used for mmu. (see chapter 5 for register descriptions) 11 compare timer compare 12 status status register 13 cause cause of last exception 14 epc exception program counter 15 prid processor revision identifier 16 config configuration register 17 ___ reserved 18 iwatch instruction breakpoint virtual address 19 dwatch data breakpoint virtual address 20-21 ___ reserved 22 iepc imprecise exception program counter 23 depc debug exception program counter 24 debug debug control/status register. 25 ? reserved 26 ecc primary cache parity 27 cacheerr cache error and status register 28 taglo cache tag register 29 ___ reserved 30 errorepc error exception program counter 31 ___ reserved table 6.1 basic cp0 registers 31 0 32 count cpu exception processing exception processing registers 79rc32334/332 user reference manual 6 - 3 june 4, 2002 notes compare register (11) the compare register acts as a timer (also see the count register), and it maintains a stable value that does not change on its own. when the value of the count register equals the value of the compare register, interrupt bit ip(7) in the cause register is set to initiate a timer interrup t, which causes an interrupt as soon as it?s enabled. writing a value to the compare register clears the timer inte rrupt. for diagnostic purposes, the compare register is both a read and write register . however, during normal operations, the compare register is a write only. the format of the compar e register is shown in figure 6.2. figure 6.2 compare register format status register (12) the status register (sr) is a read/wri te register that contains t he operating mode, interrupt enabling, and the diagnostic states of the processor. figure 6.3 shows the format of the entire register. the following bulleted items provide details on the more important status register fields: the 8-bit interrupt mask (im) field controls the individual enabling of eight interrupt conditions. inter- rupts must be generally enabled before they can c ause the exception (ie set), and the correspond- ing bits are set in both the interrupt mask field of the status register and the interrupt pending (ip) field of the cause register (for more information, refer to the interrupt pending (ip) field of the cause register).im[1:0] are the masks for the two software interrupts and im[7:2] correspond to int[5:0]. the 4-bit coprocessor usability (cu) field controls the us ability of 4 possible coprocessors. regardless of the cu0 bit setting, cp0 is always usable in kernel mode. for all other cases, an instruction for or access to an unus able coprocessor causes an exception. the 9-bit diagnostic status (ds) field (status[24:16]) is us ed for self-testing and checks the cache and virtual memory system. the reverse-endian (re) bit, bit 25, reverses the endianness of the machine. at system reset, the processor can be configured as ei ther little-endian or big-endian. th is selection is always used in kernel and supervisor modes, and also in user mode when the re bit is 0. setting the re bit to 1 inverts the user mode endianness. figure 6.3 status register format table 6.2 lists the descriptions fo r the status register?s fields. 31 0 32 compare cu 4 im [7:0] 31 15 28 27 25 24 16 8 7 5 4 32 1 0 um erl exl ie 8111 (cu3:.cu0) re 26 1 0 0 3 1 1 1 1 0de ce 0 0 sr 0 bev 1111111 23 22 21 20 19 18 17 ds 0 dl il 1 1 cpu exception processing exception processing registers 79rc32334/332 user reference manual 6 - 4 june 4, 2002 notes field description cu controls the usability of each of the four coprocessor unit numbers. cp0 is always usable when in kernel mode, regardless of the setting of the cu 0 bit. 1 usable 0 unusable re reverse-endian, valid in user mode. dl data cache lock enable. this bit enables the data cache lock function. if this bit is set during data cache fill, the cache line at that particular set will be locked. please refer to the ?cache operation? section for more detail 0 disable data cache locking 1 enable data cache locking il instruction cache lock enable. this bit enables the instruction cache lock function. if this bit is set during instruction cache fill, the cache line at that particular set will be locked. please refer to the ?cache operation? section for more detail 0 disable instruction cache locking 1 enable instruction cache locking bev controls the location of tlb refill and general exception vectors. 0 normal 1 bootstrap sr 1 indicates a soft reset or nmi has occurred. ce contents of the ecc register set or modify the check bits of the caches when ce = 1; see description of the ecc register. de specifies that cache parity errors cannot cause exceptions. 0 parity remains enable 1 disables parity 0 reserved. must be written as zeroes, and returns zeroes when read. im interrupt mask: controls the enabling of each of the external, internal, and software interrupts. an interrupt is taken if interrupts are enabled, and the corresponding bits are set in both the interrupt mask field of the sta- tus register and the interrupt pending field of the cause register. im[7:2] correspond to interrupts int[5:0] and im[1:0] to the software interrupts. 0 disabled 1 enabled um user mode bits 1 user 0 kernel erl error level 0 normal 1 error exl exception level 0 normal 1 exception note: when going from 0 to 1, ie should be disabled (0) first. this would be done when preparing to return from the exception handler, such as before executing the eret instruction. ie interrupt enable 0 disable interrupts 1 enables interrupts table 6.2 status register field descriptions cpu exception processing exception processing registers 79rc32334/332 user reference manual 6 - 5 june 4, 2002 notes status register modes and access states fields of the status register set the modes and access states as described in the following sections: interrupts are enabled when all of the following conditions are true: ie = 1 exl = 0 erl = 0 if these conditions are met, the settings of the ip bits identify the interrupt. note: setting the ie bit may be delayed by up to 3 cycles. if performing nested interrupts, re- enable the ie bit first. data cache locking is enabled when all of the follow ing conditions are true: dl = 1 exl = 0 erl = 0 if these conditions are met, the filled data cache li ne at the currently selected set will be locked. note: setting the dl bit may be delayed by as many as 3 cycles. instruction cache locking is enabled when all of the following conditions are true: il = 1 exl = 0 erl = 0 if these conditions are met, the fill ed instruction cache line at the currently selected set will be locked. note: setting the il bit may be delayed by as much as 3 cycles. for user and kernel modes, the following cpu status register bit sett ings are required: the processor is in user mode when the user mode, exception lev el and error level bits are set as follows: um = 1 and exl = 0 and erl = 0 when the user mode, exception level and error level bits are set as foll ows, the processor is in kernel mode: um = 0 or exl = 1 or erl = 1 access to the kernel address space is allowed when the processor is in kernel mode. access to the user address space is allowed in any of the three operating modes. at reset, the contents of the status register are undefined, except for the following bits: erl = 1 bev = 1 the sr bit distinguishes between reset and soft reset (nonmaskable interrupt [nmi]). cause register (13) the 32-bit read/write cause register describes the cause of the mo st recent exception. figure 6.4 shows the fields of this register, and t able 6.3 describes the contents of the cause register fields. as listed in table 6.3, a 5-bit exception code ( exccode ) indicates the cause of the most recent exception. all bits in th e cause register?with the exception of the ip(1:0) bits?are read-only. the ip(1:0) bits are used for software interrupts. cpu exception processing exception processing registers 79rc32334/332 user reference manual 6 - 6 june 4, 2002 notes figure 6.4 cause register format field description bd indicates whether the last exception taken occurred in a branch delay slot. 1 delay slot 0 normal ce coprocessor unit number referenced when a coprocessor unusable exception is taken. dw on a watch exception, indicates that the dwatch regi ster matched. on other exceptions this field is undefined. iw on a watch exception, indicates that the iwatch register matched. on other exceptions this field is undefined. iv enable the dedicated interrupt vector. 1 interrupts use new exception vector (200) 0 interrupts use dedicated common exception vector (180) ip indicates an interrupt is pending. 1 interrupt pending 0 no interrupt exccode exception code field 0 reserved. must be written as zeroes, and returns zeroes when read. table 6.3 cause register field descriptions exception code value mnemonic description 0 int interrupt 1 mod tlb modification exception 2 tlbl tlb exception (load or instruction fetch) 3 tlbs tlb exception (store) 4 adel address error exception (load or instruction fetch) 5 ades address error exception (store) 6 ibe bus error exception (instruction fetch) 7 dbe bus error exception (data reference: load or store) 8 sys syscall exception 9 bp breakpoint exception 10 ri reserved instruction exception 11 cpu coprocessor unusable exception 12 ov arithmetic overflow exception 13 tr trap exception 14 ? reserved 15:22 ? reserved 23 watch watch exception 24:31 ? reserved table 6.4 cause register exccode field 1 ip [7:0] 31 15 27 16 2 7 876 2 0 8 12 5 1 0 exc code 1 0 0 28 29 30 bd 0 ce 0 11 26 ipe dw iw iv 1 1 1 25 24 23 22 cpu exception processing exception processing registers 79rc32334/332 user reference manual 6 - 7 june 4, 2002 notes exception program counter (epc) register (14) the exception program counter ( epc ) is a read/write register that contains the address from which processing resumes after an exception has been serviced. for synchronous exceptions, the epc register contains either: the virtual address of the instruction that was the direct cause of the exception, or the virtual address of the immediately preceding branc h or jump instruction (when the instruction is in a branch delay slot, and the branch dela y bit in the cause register is set). for an imprecise exception, epc contains the inst ruction of the address that recognized the excep- tion and the address at which execution may be resumed. when the exl bit in the status register is set to 1, the processor does not write to the epc register. figure 6.5 shows the format of the epc register. figure 6.5 epc register format processor revision identifier (prid) register (15) the 32-bit, read-only processor revision identifier ( prid ) register contains information identifying the implementation and revision level of the cpu and cp0. figure 6.6 illustrates the format of the prid register. figure 6.6 prid register format table 6.5 describes the contents of the prid register fields. the low-order byte (bits 7:0) of the prid register is interpreted as a revision number, and the high-order byte (bits 15:8) is interpreted as an implementation number. the implementation number of the rc32334 processor is 0x18. the content of the high-order halfword (bits 31:16) of the register is reserved and will retu rn ?0? when read. the revision number is stored as a value in the form y.x , where y is a major revision number in bits 7:4 and x is a minor revision number in bits 3:0. the revision number can distinguish some chip revisions; however, there is no guarantee that changes to the chip will be reflected in the prid register, or that changes to t he revision number necessarily reflects software-visible chip changes. for th is reason, these values are not listed and software should not rely on the revision number in the prid register to characterize the chip. cert ain attributes, such as cache size, are independent of implementation number. field description imp implementation number rc32334: imp = 0x18 rev revision number. rw = 0 0 reserved. must be written as zeroes, returns zeroes when read. table 6.5 prid register field descriptions 31 0 epc 32 16 15 31 0 16 imp 88 0 8 rev 7 cpu exception processing exception processing registers 79rc32334/332 user reference manual 6 - 8 june 4, 2002 notes config register (16) the config register specifies various configuration options selected on the rc32334 processor. some configuration options, as defined by config bits 31:3, are set by the hardware during reset and are included in the config register as read-only status bits for so ftware access. the k0 field is the only read/ write field (as indicated by config register bits 2:0) and is controlled by software. on reset, these fields are undefined. figure 6.7 shows the format of the config register. figure 6.7 config register format table 6.6 describes the contents of the config register fields. field description ice in-circuit emulator existence 0 no ice hardware connected to the cpu 1 ice hardware connected to the cpu these states are determined through an ejtag control register bit. ec external clock: indicates the relationship of the execution core pipeline clock to the input system clock, as determined at reset: 0 system clock frequency multiplied by 2 1 system clock frequency multiplied by 3 2 system clock frequency multiplied by 4 3 system clock frequency multiplied by 5 4 system clock frequency multiplied by 6 5 system clock frequency multiplied by 7 6 system clock frequency multiplied by 8 7 reserved be big endian memory. 0 little endian 1 big endian the endianness is determined at reset. ic primary i-cache size (i-cache size = 2 9+ic bytes). in the rc32334 controller, this is set to 8 kbytes (ic = 4) dc primary d-cache size (d-cache size = 2 9+dc bytes). in the rc32334 controller, this is set to 2 kbytes (dc = 2) ib primary i-cache line size 0 16 bytes (4 words) db primary d-cache line size 0 16 bytes (4 words) dom disable on-chip register mapping 0 use the upper-most 16mb of virtual address as memory-mapped on chip register. 1 use the upper-most 16mb of virtual address as kseg2. k0 kseg0 coherency algorithm (uses same encodings as entrylo0 and entrylo1 registers, as described in chapter 5, ?memory management?.) others reserved. returns indicated values when read. should be written with indicated values. table 6.6 config register field content descriptions 31 5 1 1 0 0000 1 18 16 17 8 15 13 db ib 1 420 ice ec 13 30 28 27 4 24 23 22 00000 1 be 1 14 1 1 13 1 1 0 12 1 11 ic 3 96 dc 53 3 1 dom k0 0 cpu exception processing exception processing registers 79rc32334/332 user reference manual 6 - 9 june 4, 2002 notes iwatch register (18) the iwatch register is a read/write regi ster that specifies an instructio n virtual address that causes a watch exception. when vaddr 31..2 of an instruction fetch matches ivaddr of this register, and the i bit is set, a watch exception is taken. matches that occur w hen exl=1 or erl=1 do not take the exception immedi- ately and are instead postponed until both exl and erl are cleared. the priority of an iwatch exception is just below an instruction address error exc eption. figure 6.8 shows the format of the iwatch register. figure 6.8 iwatch register format table 6.7 describes the iwatch register fields dwatch register (19) the dwatch register is a read/write register that specif ies the data virtual address that caused a watch exception. when vaddr 31..3 of a load matches dvaddr of this register and the r bit is set, or when vaddr 31..3 of a store matches dvaddr of this register and t he w bit is set, a data watch exception is taken. matches that occur when exl=1 or erl=1 do not im mediately take the exception but are instead post- poned until both exl and erl are cleared. the priority of a dwatch exception is just below a data address error exception. dwatch exceptions do not occur on cache operations. the format of the dwatch register is shown in figure 6.9. figure 6.9 dwatch register format table 6.8 lists the contents of the dwatch register?s fields. field description ivaddr instruction virtual address that causes a watch exception [bit 31:2]. i 0 ---> iwatch disable, 1 ---> iwatch enable. 0 reserved for future use. note: iwatch.i is cleared on reset. table 6.7 watch register field description field description dvaddr data virtual address that causes a watch exception. r 0 ---> dwatch disable for loads 1 ---> dwatch enable for loads. w 0 ---> dwatch disable for stores 1 ---> dwatch enable for stores. 0 reserved for future use. note: dwatch.r and dwatch.w are cleared on reset. table 6.8 dwatch register field descriptions iwatch register 31 0 30 ivaddr 0 i 1 2 1 1 31 0 29 dvaddr w 0 1 2 1 1 3 r 1 cpu exception processing exception processing registers 79rc32334/332 user reference manual 6 - 10 june 4, 2002 notes debug exception program counter (debugepc) register (23) this register contains the address of the instructi on to resume after the ice debug exception is handled. debug register (24) this register contains status and control bits for the ice debug operation. error checking and correcting (ecc) register (26) the 8-bit error checking and correcting ( ecc ) register reads or writes prim ary-cache data parity bits for cache initialization, cache diagnostics, or cache er ror processing. (tag parity is loaded from and stored to the taglo register). the ecc register is loaded by the index load tag cache operation. the value of the ecc register is: written into the primary data cache on store instru ctions (instead of the computed parity) when the ce bit of the status register is set substituted for the computed instruction parity for the cache operation fill to force a cache parity value, use the status ce bit and the ecc register. figure 6.10 shows the format of the ecc register. figure 6.10 ecc register format table 6.9 describes the contents of the ecc register fields cache error (cacheerr) register (27) the 32-bit read-only cacheerr register processes parity errors in the primary cache. parity errors cannot be corrected automatically. the cacheerr register holds cache index and status bits t hat indicate the source and nature of the error. this register is loaded when a cache error excepti on is asserted. when a read response returns with bad parity this exception is also asserted. figure 6.11 shows the format of the cacheerr register. figure 6.11 cacheerr register table 6.10 provides descripti ons on the contents of the cacheerr register fields. field description ecc an 8-bit field specifying the parity bits read from or written to a primary cache. 0 reserved. must be written as zeroes and returns zeroes when read. table 6.9 ecc register field descriptions field description er indicates the type of reference as follows: 0 instruction 1 data table 6.10 cache error register field descriptions (part 1 of 2) 31 24 8 80 7 0ecc 31 0 19 20 er es 1 30 28 25 1 24 23 22 21 0 11 2 eb ee 1 1 1 et ed ec 11 26 27 29 1 0 sidx pidx 3 0 cpu exception processing exception processing registers 79rc32334/332 user reference manual 6 - 11 june 4, 2002 notes taglo register (28) the taglo register is a 32-bit read/write register t hat holds the primary cache tag and parity during cache initialization, cache diagnosti cs, or cache error processing. the taglo register is written by the cache and mtc0 instructions. the p field of this register is ignor ed on index store tag operations. parity is computed by the store operation. figure 6.12 shows the format of the taglo register, for primary cache operations. figure 6.12 taglo register format table 6.11 lists the field definitions of the taglo register. ec cache level of the error 0 primary ed indicates if a data field error occurred 0 no error 1 error et indicates if a tag field error occurred 0 no error 1 error es reserved ee reserved eb set if a data error occurred in addition to the instruction error (indicated by the remainder of the bits). if so, this requires flushing the data cache after fixing the instruction error. 0 no additional data error 1 additional data error sidx physical address 21:3 of the reference that encountered the error. pidx virtual address 13:12 of the double word in error. to be used with sidx to construct a virtual index for the primary caches. only the lower two bits (bits 1 and 0) are vaddr; the high bit (bit 2) is zero. 0 reserved. must be written as zeroes and returns zeroes when read. field description ptaglo in the case of data cache , the ptaglo field specifies the physical address bits 31:9. in the case of instruction cache (8kbytes), the ptaglo field specifies the physical address bits 31:11. the 2 least significant bits are undefined. pstate specifies the primary cache state. p specifies the primary tag even parity bit. f the fifo bit used to implement fifo refill of the cache. for software, there is no particular use of this bit. rsvd reserved. must be written as zeroes. l lock bit used to implement cache line lock function. table 6.11 taglo register field descriptions field description table 6.10 cache error register field descriptions (part 2 of 2) taglo 31 1 0 23 p 87 pstate 65 1 3 2 ptaglo f 2 3 l rsvd 1 1 0 1 cpu exception processing processor exceptions 79rc32334/332 user reference manual 6 - 12 june 4, 2002 notes error exception program counter (error epc) register (30) the register is similar to the epc register, except that errorepc is used on parity error exceptions (exl set) and is also used to store the program count er (pc) on reset, soft reset, and nonmaskable interrupt (nmi) exceptions. the read/write errorepc register contains the virtual address at which instruction processing can resume after servicing an error. this address can be: the virtual address of the instruction that caused the exception the virtual address of the immedi ately preceding branch or jump inst ruction, when this address is in a branch delay slot. there is no branch delay slot indication for the errorepc register. figure 6.13 shows the format of the errorepc register. figure 6.13 errorepc register processor exceptions this section describes the proce ssor exceptions: the cause of each exception, its processing by the hardware, and servicing by a handler (software). the types of excepti on, with exception processing opera- tions, are described in the next section. exception types this section gives sample exception handler operations for the following exception types: reset soft reset nonmaskable interrupt (nmi) cache error remaining processor exceptions when the exl bit in the status register is 0, either user or ke rnel operating mode is specified by the um bits in the status register. when the exl bit or the erl bit is a 1, the processor is in kernel mode. when the processor takes an exception, the exl bit is set to 1, which means the system is in kernel mode. after saving the appropriate state, t he exception handler typically resets the exl bit back to 0. when restoring the state and restarting, the handler sets the exl bit back to 1, to inhibit subsequent interrupts. returning from an exception also resets the exl bit to 0. in the following sections, sample hardware proce sses for various exceptions, are shown together with the servicing required by the handler (software). value cache state attribute 0 invalid 1 shared 2 clean exclusive 3 dirty exclusive table 6.12 primary cache state values 31 0 errorepc 32 cpu exception processing processor exceptions 79rc32334/332 user reference manual 6 - 13 june 4, 2002 notes general exception process figure 6.14 shows the process used for exceptions ot her than reset, soft reset, nmi, and cache error. figure 6.14 general exception process priority of exceptions although more than one exception can occur for a single instruction, only the ex ception with the highest priority will be reported. after the highest priority exceptions have been se rviced, if lower priority exception conditions remain, they will be si gnalled and serviced at that time. the remainder of this chapter describes exceptions?in the order of their priority?as shown in table 6.13. generally speaking, the exceptions that will be described in the following sections are handled (?processed?) by hardware; these exc eptions are then serviced by software. exception vector locations the reset, soft reset, and nmi exceptions are al ways vectored to location 0xbfc0 0000 (virtual address), corresponding to kseg1 . the debug exception for in-circuit emulator (ice) is vectored to location 0xff20_0200 (virtual address), corresponding to ice space, if the ice hardware is connec ted to the cpu (i.e. configuration register ice bit is set). otherwise, this excepti on is vectored to location 0xbfc0_0480. addresses for all other exceptions are a combination of a vector offset and a base address . the base address is determined by the bev bit of the status register, as shown in table 6.16. table 6.14 lists the vector offset that is added to the base address to create the exception address. exception priority 1reset (highest priority) 11 bus error ?? instruction fetch 2 debug (ice) 12 integer overflow, trap, system call, breakpoint, reserved instruction, coprocessor unusable, or floating-point exception 3 soft reset 13 address error ?? data access 4 nonmaskable interrupt (nmi) 14 tlb refill ?? data access 5 imprecise bus error 15 tlb invalid ?? data access 6 address error ?? instruction fetch 16 tlb modified ?? data write 7 tlb refill ?? instruction fetch 17 cache error ?? data access 8 tlb invalid ?? instruction fetch 18 watch -- data access 9 watch -- instruction fetch 19 bus error ?? data ac cess (precise) 10 cache error ?? instruction fetch 20 interrupt (lowest priority) table 6.13 exception priority order (highest to lowest) t: cause bd || 0 || ce || 0 12 || cause 15:8 || 0 || exccode || 0 2 if sr 1 = 0 then /* system in user mode with no current exception */ epc pc endif sr sr 31:2 || 1 || sr0 / + set exl */ if sr 22 = 1 then /* what is the bev bit setting */ pc 0xbfc0 0200 + vector /* access to uncached space */ else pc 0x8000 0000 + vector /* access to cached space */ endif cpu exception processing processor exceptions 79rc32334/332 user reference manual 6 - 14 june 4, 2002 notes as shown in table 6.15, when bev = 0, the vector base for the cache error exception changes from kseg0 (0x8000 0000) to kseg1 (0xa000 0000). when bev = 1, the vector base for the cache error exception is 0xbfc00200. this is an uncached and unmapped space, allowing the exception to bypass the cache and tlb. reset exception cause : the reset exception occurs when the cpu_col dreset_n signal is asserted and then deasserted. processing : the cpu provides a special exception ve ctor for this exception of: 0xbfc0 0000 the reset vector resides in unmapped and uncac hed cpu address space, so the hardware need not initialize the tlb or the cache to process this exce ption. it also means the processor can fetch and execute instructions while the caches and virtual memory are in an undefined state. maskable : no bev normal exception base cache error base 0 0x8000 0000 0xa000 0000 1 0xbfc0 0200 0xbfc0 0200 table 6.14 base address vector offset exception rc32334 processor vector offset tlb refill, exl = 0 0x000 cache error 0x100 interrupt 1 1. if cause.iv = 1. otherwise interrupts use general vector offset. 0x200 others 0x180 table 6.15 list of rc32334 exception vectors exception bev exl iv ice rc32334 processor vector reset, soft reset, nmi x x x x 0xbfc0 0000 debug (ice) x x x 1 0xff20 0200 debug (ice) x x x 0 0xbfc0 0480 tlb refill 1 0 x x 0xbfc0 0200 tlb refill 1 1 x x 0xbfc0 0380 tlb refill 0 0 x x 0x8000 0000 tlb refill 0 1 x x 0x8000 0180 cache error 1 x x x 0xbfc0 0300 cache error 0 x x x 0xa000 0100 interrupt 1 x 1 x 0xbfc0 0400 interrupt 1 x 0 x 0xbfc0 0380 interrupt 0 x 1 x 0x8000 0200 interrupt 0 x 0 x 0x8000 0180 others 1 x x x 0xbfc0 0380 others 0 x x x 0x8000 0180 note : x means don?t care table 6.16 rc32334 exception vectors cpu exception processing processor exceptions 79rc32334/332 user reference manual 6 - 15 june 4, 2002 notes the contents of all registers in the cpu are undef ined when this exception occurs, except for the following register fields: in the status register, sr is cleared to 0, and erl and bev are set to 1. all other bits are unde- fined. the random register is initialized to the value of its upper bound. the wired register is initialized to 0. iwatch.i,dwatch.w and dwatch.r are cleared. some of the config register bits are initialized from the boot-time mode stream. the reset exception is serviced by: initializing all processor registers, coproces sor registers, caches, and the memory system performing diagnostic tests bootstrapping the operating system the reset exception process is as shown in figure 6.15. figure 6.15 process of the reset exception debug exception cause: the debug exception occurs either when the ic e breakpoint signal is asserted from the ice hardware or when the processor executes the sdbbp instruction. processing: the cpu provides a special except ion vectors for this exception at: 0xff20 0200 if the ice hardware is connected to the cpu. 0xbfc0 0480 if the ice hardware is not connected to the cpu. the debug exception vectors reside in unmapped an d uncached cpu address space, so the hardware need not initialize the tlb or the cache to process th is exception. it also means the processor can fetch and execute instructions while the caches and virtual memory are in an undefined state. servicing: the debug exception is serviced by the ice softw are, to assist the user in a system level debug. maskable: no soft reset exception cause: the soft reset exception occurs in response to the reset* input signal (internal to cpu core), and execution begins at the reset vector when reset* is deasserted. processing: the reset exception vector is used for this exception, located within unmapped and uncached address space so that the cache and tlb need not be initialized to process this exception. when a soft reset occurs, the sr bit of the status register is set to distinguish this exception from a reset excep- tion. the primary purpose of the soft reset exception is to reinitialize the processor after a fatal error during normal operations. unlike an nmi, all cache and bus state machines are reset by this exception. like reset, soft reset can be used on the processor in any state. the caches, tlb, and normal excep- tion vectors need not be properly initialized. t: undefined random tlbentries?1 wired 0 config <- ice || ec || ep || 00000000 || be || 110 || 100 || 010 || 0 || 0 || 0 || 000 errorepc pc sr sr 31:23 || 1 || 0 || 0 || sr 19:3 || 1 || sr 1:0 / * erl 1, bev 1 * / pc 0xbfc0 0000 cpu exception processing processor exceptions 79rc32334/332 user reference manual 6 - 16 june 4, 2002 notes when this exception occurs, the contents of all registers are preserved except for: errorepc register, which contains the restart pc erl bit of the status register, which is set to 1 sr bit of the status register, which is set to 1 bev bit of the status register, which is set to 1 because the soft reset can abort cache and bus operations, cache and memory state is undefined when this exception occurs. servicing : the soft reset exception is serviced by sa ving the current processor state for diagnostic purposes, and reinitializing for the reset exception. maskable: no the soft reset and nmi exception proc esses are as shown in figure 6.16. figure 6.16 process of the soft reset and nmi exceptions nonmaskable interrupt (nmi) exception cause: the nonmaskable interrupt (nmi) exception oc curs in response to the asserting edge of the nmi pin. unlike all other interrupts, this interrupt is not maskable; it occurs regar dless of the settings of the exl , erl , and the ie bits in the status register. processing: the reset exception vector is used for this exception. this vector is located within unmapped and uncached address space so that the cac he and tlb need not be initialized to process an nmi interrupt. when an nmi exception occurs, the sr bit of the status register is set to differentiate this exception from a reset exception. because an nmi can occur in the midst of another exception, it is not normally possible to continue program execution after servicing an nmi. unlike reset and soft reset, but like other exceptions, nmi is taken only at instruction boundaries. the state of the caches and memory system are preserved by this exception. to terminate a pending read that has hung the best approach is to return a bus error. however, if you wish to use a cpu exception to indicate a hung read, soft reset is preferable to nmi. when this exception occurs, the contents of all r egisters are preserved except for the following: errorepc register, which contains the restart pc erl bit of the status register, which is set to 1 sr bit of the status register, which is set to 1 bev bit of the status register, which is set to 1 servicing: the nmi exception is serviced by saving the current processor state for diagnostic purposes, and reinitializing the system for the reset exception. maskable: no. address error exception cause: the address error exception occurs when an atte mpt is made to execute one of the following: load, fetch, or store a word that is not aligned on a word boundary (except for use of special instruc- tion) load or store a halfword that is not aligned on a halfword boundary reference the kernel addres s space from user mode t: errorepc pc sr sr 31:23 || 1 || 0 || 1 || sr 19:3 || 1 || sr 1:0 /* bev 1, sr 1, erl 1 */ pc 0xbfc0 0000 cpu exception processing tlb exceptions 79rc32334/332 user reference manual 6 - 17 june 4, 2002 notes processing: the common exception vect or is used for the address error exception. if the adel or ades code in the cause register is set, this indicates how the instruction (shown by the epc register and the bd bit in the cause register) caused the exception: through an instruction reference, a load operation, or a store operation. when this exception occurs, the badvaddr register retains the virtual address that was not properly aligned or had referenced protected addr ess space. the contents of the vpn field of the context and entryhi registers are undefined, as are the contents of the entrylo register. the epc register contains the address of the instructi on that caused the exception, unless this instruc- tion is in a branch delay slot. if it is in a branch delay slot, the epc register contains the address of the preceding branch instruction and the bd bit of the cause register is set as indication. servicing: typically, the process executing at the ti me is handed a segmentati on violation signal. this error is usually fatal to the process incurri ng the exception. to resume execution, the epc register or the load/store target address must be alte red so that the unaligned reference instruction does not re-execute; this is accomplished by adding a value of 4 to the epc register ( epc register + 4) before returning. if an unaligned reference instruction is in a branch delay slot, interpretation of the branch instruction is required to resume execution. maskable: no tlb exceptions this section explains the tlb exceptions. three types of tlb exceptions can occur: tlb refill occurs when there is no tlb entry that matches an attempted reference to a mapped address space. tlb invalid occurs when a virtual address reference ma tches a tlb entry that is marked invalid. tlb modified occurs when a store operation virtual addr ess reference to memory matches a tlb entry which is marked valid but is not dirty (the entry is not writable). for specifics on the exceptions listed here, refer to the appropriate subsection. tlb refill exception cause: the tlb refill exception occurs when there is no tlb entry to match a reference to a mapped address space. processing: this exception sets the tlbl or tlbs code in the exccode field of the cause register. this code indicates whether the instruction, as shown by the epc register and the bd bit in the cause register, caused the miss by an instruction re ferenced load operation or by a store operation. when this exception occurs, the badvaddr , context , and entryhi registers hold the virtual address that failed the address translation. the entryhi register also contains the asid from which the translation fault occurred. the random register normally suggests a valid locati on in which to place the replacement tlb entry. the contents of the entrylo registers are undefined. the epc register contains the address of the instruction that caused the exception, unless this instru ction is in a branch delay slot, in which case the epc register contains the address of t he preceding branch instruction and the bd bit of the cause register is set. servicing: to service this exception, the content of the context register is used as a virtual address to fetch memory locations containing the physical page fram e and access control bits for a pair of tlb entries. the two entries are placed into the e ntrylo0/entrylo1 register; the entryhi and entrylo registers are written into the tlb, typically with a tlbwr instruction. it is possible that the virtual addr ess used to obtain the physical address and access control information is on a page that is not resident in the tlb. this condi tion is processed by allowi ng a tlb refill exception in the tlb refill handler. this second exception goes to the common exception vector because the exl bit of the status register is set. maskable: no. cpu exception processing tlb exceptions 79rc32334/332 user reference manual 6 - 18 june 4, 2002 notes tlb invalid exception cause : the tlb invalid exception occurs when a virtual address reference matches a tlb entry that is marked invalid (tlb valid bit cleared). processing: the common exception vector is used for this exception. the tlbl or tlbs code in the exccode field of the cause register is set, which indicates w hether the instruction?shown by the epc register and bd bit in the cause register?caused the miss by an inst ruction referenced load operation or by a store operation. when this exception occurs, the badvaddr , context , and entryhi registers contain the virtual address that failed address translation. the entryhi register also contains the asi d from which the translation fault occurred. the random register normally contains a valid loca tion in which to put the replacement tlb entry. the contents of the entrylo registers are undefined. the epc register contains the address of the instructi on that caused the exception unless this instruc- tion is in a branch delay slot, in which case the epc register contains the address of the preceding branch instruction and the bd bit of the cause register is set. servicing: a tlb entry is typically marked in valid when one of the following is true: a virtual address does not exist the virtual address exists, but is not in main memory (a page fault) a trap is desired on any reference to the page (for example, to maintain a reference bit or during debug) after servicing the cause of a tlb invalid exception, the tlb entry is located with tlbp (tlb probe), and replaced by an entry with that entry?s valid bit set. maskable: no. tlb modified exception cause: the tlb modified exception oc curs when a store operation virtual address reference to memory matches a tlb entry that is marked valid but is not dirty and therefore is not writable. processing: the common exception vector is used for this exception, and the mod code in the cause register is set. when the tlb modified exception occurs, the badvaddr , context , and entryhi registers contain the virtual address that failed address translation. the entryhi register also contains the asid from which the translation fault occurred. the contents of the entrylo registers are undefined. the epc register contains the address of the instructi on that caused the exception unless that instruc- tion is in a branch delay slot, in which case the epc register contains the address of the preceding branch instruction and the bd bit of the cause register is set. servicing: the kernel uses the failed virtual addre ss or virtual page number to identify the corre- sponding access control information. the page identifi ed may or may not permit write accesses; if writes are not permitted, a write pr otection violation occurs. if write accesses are permitted, the page frame is ma rked dirty/writable by the kernel in its own data structures. the tlbp instruction places the index of the tlb entry that must be altered into the index register. the entrylo register is loaded with a word containi ng the physical page frame and access control bits (with the d bit set), and the entryhi and entrylo registers are written into the tlb. maskable: no cache error exception cause: the cache error exception occurs when a primary cache parity error is detected. processing: the processor sets the erl bit in the status register, saves the exception restart address in errorepc register, and then transfers to a special vector in uncached space: if the bev bit = 0, the vector is 0xa000 0100. if the bev bit = 1, the vector is 0xbfc0 0300. cpu exception processing tlb exceptions 79rc32334/332 user reference manual 6 - 19 june 4, 2002 notes no other registers are changed. servicing: all errors should be logged. to correct cac he parity errors, the system uses the cache instruction to invalidate the cache block, overwrites the old data through a cache miss, and resumes execu- tion with an eret. other errors are not correctable and are likely to be fatal to the current process. maskable: yes, by the de bit of the status register. the cache error exception proces s is as shown in figure 6.17. figure 6.17 process of the cache error exception bus error exception cause: a bus error exception is raised by board-level circuitry for events such as bus time-out, back- plane bus parity errors, and invalid physical memory addr esses or access types. a bus error exception will occur only when a cache miss refill or uncached refe rence occurs synchronously. a bus error exception resulting from a buffered write transaction must be reported using the general interrupt mechanism. processing: the common interrupt vector is used for a bus error exception. the ibe or dbe code in the exccode field of the cause register is set, signifying whether the instruction (as indicated by the epc register and bd bit in the cause register) caused the exception by an instruction referenced load operation or store operation. the epc register contains the address of the instruction that caused the exception, unless it is in a branch delay slot, in which case the epc register contains the address of the preceding branch instruction and the bd bit of the cause register is set. servicing: the physical address at which the fault occu rred can be computed from information avail- able in the cp0 registers. if the ibe code in the cause register is set (indicating an instruct ion fetch reference), the virtual address is contained in the epc register. if the dbe code is set (indicating a load or store reference), then the instruction that caused the exception is lo cated at the virtual address contained in the epc register (or 4+ the contents of the epc register if the bd bit of the cause register is set). note: the ipe bit should be checked first. if this bit is set, refer to the servicing section for the imprecise bus error exception. the virtual address of the load and store reference c an then be obtained by interpreting the instruction. the physical address can be obtained by us ing the tlbp instruction and reading the entrylo register to compute the physical page number. the process that is ex ecuting at the time of this exception is handed a bus error signal, which is usually fatal. maskable: no. integer overflow exception cause: an integer overflow excepti on occurs when an add, addi, sub 1 , or instruction results in a 2?s complement overflow. processing: the common exception vector is used for this exception, and the ov code in the cause register is set. 1. see appendix a for instruction description. t: errorepc pc cacheerr er || ec || ed || et || es || ee || eb || 0 25 sr sr 31:3 || 1 ||sr 1:0 /* set erl */ if sr 22 = 1 then /* what is the bev bit setting */ pc 0xbfc0 0200 + 0x100 /* access boot-prom area */ else pc 0xa000 0000 + 0x100 /* access main memory area */ endif cpu exception processing tlb exceptions 79rc32334/332 user reference manual 6 - 20 june 4, 2002 notes the epc register contains the address of the instruction that caused the exception unless the instruction is in a branch delay slot, in which case the epc register contains the address of the preceding branch instruction and the bd bit of the cause register is set. servicing: the process executing at the time of the exception is handed a floating-point exception/ integer overflow signal. this error is usually fatal to the current process. maskable: no. trap exception cause: the trap exception occurs when a tge, tgeu , tlt, tltu, teq, tne, tgei, tgeui, tlti, tltui, teqi, or tnei 1 instruction results in a true condition. processing: the common exception vector is used for this exception, and the tr code in the cause register is set. the epc register contains the address of the instructi on causing the exception unless the instruction is in a branch delay slot, in which case the epc register contains the address of the preceding branch instruc- tion and the bd bit of the cause register is set. servicing: the process executing at the time of a tr ap exception is handed a floating-point exception/ integer overflow signal. this error is usually fatal. maskable: no. system call exception cause: the execution of the syscall instructi on causes a system call exception to occur. processing: the common exception vector is used for this exception, and the sys code in the cause register is set. the epc register contains the address of the syscall inst ruction unless it is in a branch delay slot, in which case the epc register contains the address of the preceding branch instruction. if the syscall instruction is in a branch delay slot, the bd bit of the status register is set; otherwise, this bit is cleared. servicing: when this exception occurs, control is tr ansferred to the applicable system routine. to resume execution, the epc register must be altered so that the syscall instruction does not re-execute; this is accomplished by adding a value of 4 to the epc register ( epc register + 4) before returning. if a syscall instruction is in a branch delay slot, a more complicated algorithm, beyond the scope of this description, may be required. maskable: no. breakpoint exception cause: a breakpoint exception occurs when an attempt is made to execute the break instruction. processing: the common exception vector is used for this exception, and the bp code in the cause register is set. the epc register contains the address of the br eak instruction unless it is in a branch delay slot, in which case the epc register contains the address of t he preceding branch instruction. if the break instruction is in a branch delay slot, the bd bit of the status register is set, otherwise the bit is cleared. servicing: when the breakpoint exception occurs, c ontrol is transferred to the applicable system routine. additional distinctions can be made by analyzing the unused bits of the break instruction (bits 25:6), and loading the contents of the instruction whose address the epc register contains. a value of 4 must be added to the contents of the epc register (epc register + 4) to locate the instruction if it resides in a branch delay slot. to resume execution, the epc register must be altered so that the break instruction does not re- execute. this is accomplished by adding a value of 4 to the epc register ( epc register + 4) before cpu exception processing tlb exceptions 79rc32334/332 user reference manual 6 - 21 june 4, 2002 notes returning. if a break instruction is in a branch delay sl ot, interpretation of the branch instruction is required to resume execution. maskable: no. reserved instruction exception cause: the reserved instruction exception occurs when one of the following conditions occurs: an attempt is made to execute an instruction with an undefined major opcode (bits 31:26) an attempt is made to execute a special instruction with an undefined minor opcode (bits 5:0) an attempt is made to execute a regimm instru ction with an undefined minor opcode (bits 20:16) an attempt is made to execute a 64-bit operation processing: the common exception vector is used for this exception, and the ri code in the cause register is set. the epc register contains the address of the rese rved instruction unless it is in a branch delay slot, in which case the epc register contains the address of the preceding branch instruction. servicing: no instructions in the rc32300 cpu core are in terpreted. the process executing at the time of this exception is handed an illegal instruction/rese rved operand fault signal. this error is usually fatal. maskable: no. coprocessor unusable exception cause: the coprocessor unusable exception occurs when an attempt is made to execute a copro- cessor instruction for either: a corresponding coprocessor unit t hat has not been marked usable, or cp0 instructions, when the unit has not been mark ed usable and the process executes in user mode. processing: the common exception vector is used for this exception, and the cpu code in the cause register is set. the contents of the coprocessor usage error field of the coprocessor control register indi- cate which of the four coprocessors was referenced. the epc register contains the address of the unus- able coprocessor instruction unless it is in a branch delay slot, in which case the epc register contains the address of the preceding branch instruction. servicing: the coprocessor unit to which an attempt ed reference was made is identified by the copro- cessor usage error field, which results in one of the following situations: if the process is entitled access to the coproces sor, the coprocessor is marked usable and the cor- responding user state is restored to the coprocessor. if the process is entitled access to the coprocessor, but the coprocessor does not exist or has failed, interpretation of the coprocessor instruction is possible. if the bd bit is set in the cause register, the br anch instruction must be interpreted; then the copro- cessor instruction can be emul ated and execution resumed with the epc register advanced past the coprocessor instruction. if the process is not entitled acce ss to the coprocessor, the proc ess executing at the time is handed an illegal instruction/privileged instruction f ault signal. this erro r is usually fatal. maskable: no. interrupt exception cause: the interrupt exception occurs when one of the ei ght interrupt conditions is asserted. the signif- icance of these interrupts is dependent upon the specific system implementation. processing: the rc32334 may use the common exception vector or a dedicated vector for this excep- tion, determined by the cause register iv bit. the int code in the cause register is set. the ip field of the cause register indicates current interrupt requests. it is possible that more than one of the bits can be simultaneously set (or even no bits may be set if the interrupt is asserted and then deasserted before this register is read). cpu exception processing tlb exceptions 79rc32334/332 user reference manual 6 - 22 june 4, 2002 notes servicing: if the interrupt is caused by one of the two software-generated exceptions ( sw1 or sw0 ), the interrupt condition is cleared by setting the corresponding cause register bit to 0. if the interrupt is hard- ware-generated, the interrupt condition is cleared by correcting the conditi on causing the interrupt pin to be asserted. maskable: yes. each of the eight interrupts can be masked by clearing the corresponding bit in the int- mask field of the status register, and all of the eight interrupt s can be masked at once by clearing the ie bit of the status register. note: due to the write buffer, a store to an external device will not necessari ly occur until after completion of other instructions in the pipeline. thus, the user must ensure that the store occurs before the return from exception (eret) instruct ion is executed; otherwise, the interrupt may be serviced again, although there should be no interr upt pending. the sync instruction can be used to achieve this. dwatch exception cause: dwatch is a read-write register that specifies a data virtual address that causes a watch excep- tion. this exception occurs either when the progr am does a load and the target address matches dwatch and dwatch.r is set or when the program does a store and the target address matches dwatch and dwatch.w is set. processing: the common exception vector is used for this exception. the watch code of the cause register is set with the dw bit set. servicing: this exception is typically used during system debug. servicing is system-specific. maskable: no. enabled or disabled through bits in the dw atch register (19). refer to table 6.8 for settings and descriptions. iwatch exception cause: iwatch is a read-write register that specifies an instruction vi rtual address that causes a watch exception. the exception occurs when the program address matches the iwatch register, and iwatch.i is set. processing: the common exception vector is used for this exception. the watch code of the cause register is set with the iw bit set. servicing: typically, this exception is used duri ng system debug. servicing is system-specific. maskable: no. enabled or disabled through bits in the iw atch register (18). refer to table 6.7 for settings and descriptions. exception handling and servicing flowcharts the remainder of this chapter cont ains flowcharts for the exceptions described in table 6.13 as well as guidelines for their handlers. in general, exceptions are handled by hardw are (hw) and serviced by software (sw). figure description figure 6.18 figure 6.19 general exceptions and their exception handler (hw) general exceptions and their exception handler (sw) figure 6.20 figure 6.21 tlb miss exception and their exception handler (hw) tlb refill exception servicing guideline (sw) figure 6.22 cache error exception and its handler figure 6.23 reset, soft reset and nmi exceptions, and a guideline to their handler. table 6.17 list of exception handling flowchart types cpu exception processing tlb exceptions 79rc32334/332 user reference manual 6 - 23 june 4, 2002 notes figure 6.18 general exception handling (hw) * 200 for interrupts if cause.iv is set. pc 0x8000 0000 exl 1; 0 pc 0xbfc0 0200 bev =1 (bootstrap) =0 to general exception servicing guidelines (unmapped, cached) (unmapped, uncached) note: interrupts can be masked by ie or ims (normal) exl (sr1) =1 =0 epc pc instr. in yes no epc (pc - 4) br.dly. slot? exl (sr1) =1 =0 set badva set badva cause 31 (bd) 1 cause 31 (bd) 0 set cause register enhi vpn2, asid context vpn2 exccode, ce exception another exception tlb- invalid, modified, & refill exceptions + 180* + 180* is disabled comments check if exception within processor forced to kernel mode, badva is set only for tlb- invalid, modified, note: not set if bus error refill- and vced/i exceptions interrupt exceptions other than reset, soft reset, nmi, cacheerr or first-level tlb miss *enhi, context are set only for cpu exception processing tlb exceptions 79rc32334/332 user reference manual 6 - 24 june 4, 2002 notes figure 6.19 general exception servicing guideline (sw) mfc0 context epc status cause exl 0 check cause reg. & jump to appropriate service code exl = 1 mtc0 epc status eret * unmapped vector so tlbmod, tlbinv, tlb refill exceptions not possible * exl=1 so interrupt exceptions disabled *only cacheerr, reset, soft reset, nmi * os/system to avoid all other exceptions * after exl=0, all exceptions allowed. (except interrupt if masked by ie or im and cacheerr if masked by de) comments exceptions possible. ksu 00 (optional - only to enable interrupts while keeping kernel mode) mtc0 (set status bits:) & ie=1 * pc epc; exl 0 * llbit 0 * eret is not allowed in the branch delay slot of * processor does not execute the instruction which is in the eret?s branch delay slot another jump instruction service code service code cpu exception processing tlb exceptions 79rc32334/332 user reference manual 6 - 25 june 4, 2002 notes figure 6.20 tlb refill exception handling (hw) exl (sr bit 1) exl 1 =1 =0 pc 0xbfc0 0200 pc 0x8000 0000 =0 (normal) =1 to tlb exception servicing guidelines (unmapped, cached) (unmapped, uncached) bev (sr bit 22) vec. off. = 0x000 vec. off. = 0x180 instr. in yes processor forced to kernel mode & check to see if exception is within (bootstrap) br.dly. slot? exl (sr bit 1) =1 =0 points to general exception points to refill exception no set cause reg. enhi vpn2, asid context vpn2 exccode, ce and cause bit 31 (bd) 1 set cause reg. enhi vpn2, asid context vpn2 exccode, ce and cause bit 31 (bd) 0 epc pc epc (pc - 4) set badva set badva another exception interrupt disabled + vec.off. + vec.off. cpu exception processing tlb exceptions 79rc32334/332 user reference manual 6 - 26 june 4, 2002 notes figure 6.21 tlb refill exception servicing guideline (sw) mfc0 context service code eret * unmapped vector so tlbmod, tlbinv, tlb refill or vc ep exceptions * exl=1 so interrupt exceptions disabled *only cacheerr, reset, soft reset, nmi * os/system to avoid all other exceptions * pc epc; exl 0 * llbit 0 comments exceptions possible. * there could be a tlb mi ss again during the mapping not possible of the data or instruction address. the processor will jump to the general exception vector since the exl is 1. (option to complete the first level refill in the general * load the mapping of the virtual address in context reg. move it to enlo and write into the tlb * eret is not allowed in the branch delay slot of * processor does not execute the instruction which is in the eret?s branch delay slot another jump instruction exception handler or eret to the original instruction and take the exception again) cpu exception processing tlb exceptions 79rc32334/332 user reference manual 6 - 27 june 4, 2002 notes figure 6.22 cache error exception hand ling (hw) and servicing guidelines (sw) set cacheerr reg. erl 1 pc 0xbfc0 0200 bev pc 0xa000 0000 =1 =0 (unmapped, uncached) (unmapped, uncached) note: can be masked/disabled by de (sr16) bit = 1 (bootstrap) (normal) errepc pc instr. in yes no errepc (pc - 4) br. dly. slot? service code eret * eret is not allowed in the branch delay slot of * unmapped uncached vector so tlb related & cache error exception not possible * erl=1 so interrupt exceptions disabled *only reset, soft reset, nmi * os/system to avoid all other exceptions * processor does not execute the instruction which is * pc errorepc; erl 0 * llbit 0 comments exceptions possible. in the eret?s branch delay slot another jump instruction + 100 + 100 servicing guidelines (sw) cache error exception handling (hw) cpu exception processing tlb exceptions 79rc32334/332 user reference manual 6 - 28 june 4, 2002 notes figure 6.23 reset, soft reset & nmi exception handling (hw) and servicing guidelines (sw) reset, soft reset & nmi exception handling (hw) random tlbentries - 1 wired 0 config update(31:6)|| undef(5:0) status: bev 1 sr 0 erl 1 errorepc pc pc 0xbfc0 0000 status: bev 1 sr 1 erl 1 soft reset or nmi exception reset exception nmi service code soft reset service code nmi? reset service code yes no status bit 20 = 1 =0 eret (optional) note: there is no indication from the processor to differentiate between there must be a system level indication. (sr) reset, soft reset & nmi servicing guidelines (sw) nmi & soft reset; notes 79rc32334/332 user reference manual 7 - 1 june 4, 2002 chapter 7 cache organization, operation, and coherency introduction caches are small, high speed memories used to buffe r the central processing unit from slower, larger storage devices such as those found in main memory. ca ches are used to store the data or instructions that a program is currently using while the majority of t he data remains in the slower memory, thus providing quick, temporary storage. in the logical memory hierarchy, caches resi de between the cpu and main memory. the increased memory access speed made possible through caches is usually transparent to the programmer. each functional block shown in figure 7.1 has the capacity to hold more data than the block above it. for example, physical main memory has a larger c apacity than the primary cache. however, each func- tional block requires longer access ti mes than any block above it; therefore, it takes longer to access data in main memory than in the cpu on-chip registers. figure 7.1 logical hierarchy of memory cache operation overview to support high-performance risc des igns, the primary cache is made up of an instruction cache (holds instructions) and a data ca che (holds data). this arrangement allows the processor simultaneous access to both instructions and data, thereby doubling the effective cache-memory bandwidth. in general, during cache operations, the processor accesses cache-re sident instructions/data when the on-chip cache controller detects va lid information in the cache by an address match. figure 7.4 shows the primary cache lookup sequence. if valid instruction or data is present, the processor retrieves it from cache memory and is then known as a primary-cache hit. if the instruction/data is not present, a cache miss has occurred. the cache line must then be retrieved from slower main memory. registers registers main memory primary cache rc32334 cpu i-cache d-cache increasing data capacity disk, cd-rom, tape, etc. registers caches memory peripherals faster access time cache organization, operation, and coherency rc32334 cache description 79rc32334/332 user reference manual 7 - 2 june 4, 2002 notes for a cache hit, the processor retrieves the instruct ion/data from the (high-speed) primary cache and the operation continues. in the case of a cache miss, th e processor can restart the pipeline after the first doubleword is retrieved (the one at the miss address) and continues the cache line refill in parallel. it is possible for the same data to simultaneously be in main memory and primary cache. the data is kept consistent through the use of either a write-back or a write-through methodology. for a write-back cache, the modified data is not written back to memory until the cache line is replaced. in a write-through cache, the data is written to memory as the cached data is modified (with a possible delay due to the write buffer). rc32334 cache description details of the rc32334?s cache memory are provided in the remainder of this chapter. throughout this text, the following term inology will be used: the primary cache may also be referred to as the p-cache the primary data cache may also be referred to as the d-cache the primary instruction cache may also be referred to as the i-cache. these terms will also be used interchangeably throughout the manual. rc32334 cache attributes table 7.1 highlights the user attributes of the rc32334 caches. cache organization and accessibility this section describes the organization of the pr imary cache, including the manner in which it is mapped, the addressing used to index the cache, and co mposition of the cache lines. the primary instruc- tion and data caches are indexed with a virtual address (va). 1 organization of the primary instruction cache (i-cache) each line of primary i-cache data (a lthough the field actually contains an instruction, it is referred to as data to distinguish it from the tag field) has an as sociated 25-bit tag that cont ains a 21-bit physical address, a single valid bit, a single parity bit, a lock bit, and t he fifo replacement bit. word parity is used on i-cache data. attribute instruction data size 8kb 2kb organization 2-way set-associative 2-way set associative line size 16 bytes 16 bytes read unit 32-bits 32-bits write policy n.a. write-back or writ e-through, as specified in cp0. line transfer order sub-block order sub-block order miss restart after transfer of entire line miss word cache-locking per line per line parity per-word per-byte table 7.1 rc32334 cache attributes 1. because the size of one set of primary caches is 8kb for icache and 2kb for dcache, the virtual offset equals the physical offset. logically, however, the cache index is pre-translation and thus considered virtual. cache organization, operation, and coherency cache organization and accessibility 79rc32334/332 user reference manual 7 - 3 june 4, 2002 notes the primary i-cache of the rc32334 proces sor has the following characteristics: two-way set associative indexed with a virtual address checked with a physical tag organized with 4-word (16-byte) cache line lockable on a per-line basis. figure 7.2 shows the format of a primary i-cache r egister, and table 7.2 lists field content descriptions. figure 7.2 primary i-cache line format note: the physical tag field contains 21 bits (bit [31:11]) of the physical address to support the smaller i-cache size of 4kb (2kb per set) in the future. for the current version of 3200 core with 8kb of i-cache, just bits [31: 12] are valid, bit 11 is ignored. organization of the primary data cache (d-cache) each line of primary d-cache data has an associated 30-bit tag that contains a 23-bit physical address, 2-bit cache line state, a wr ite-back bit, a parity bit for the physical address and cache state fields, a parity bit for the write-back bit, the fifo replacement bit, and a lock bit. the primary d-cache of the rc32334 proce ssor has the following characteristics: write-back or write-through on a per-page basis two-way set associative indexed with a virtual address checked with a physical tag organized with 4-word (16-byte) cache line lockable on a per-line basis. field description ptag physical tag (bits 31:11 of the physical address) f fifo replacement bit. complemented on refill vvalid bit p even parity for the ptag and v fields l lock bit datap even parity; 1 parity bit per word of data data cache data table 7.2 primary i-cache line field descriptions 21 22 0 1 p 20 21 fptag 1 1 0 31 32 32 datap data data datap data datap data datap l 1 23 v 1 24 cache organization, operation, and coherency cache organization and accessibility 79rc32334/332 user reference manual 7 - 4 june 4, 2002 notes figure 7.3 shows the format of a pr imary d-cache line; table 7.3 provi des the field content descriptions. figure 7.3 primary d-cache line format note: the physical tag field contains 23 bits (bits [31:9]) of the physical address to support the smallest d-cache size of 1kb (512b per set) in the future. for the current version of 3200 core with 2kb of d-cache, just bits [31:10] are valid, bit 9 is ignored. in the rc32334 , the w (write-back) bit?not the cache state?i ndicates whether or not the primary cache contains modified data that must be written back to memory. note: there is no hardware support for cache coher ency. the only cache states used are dirty exclusive and invalid. field description ptag physical tag (bits 31:9 of the physical address) f fifo replacement bit cs primary cache state: 0 = invalid, 1 = shared, 2 = clean exclusive, 3 = dirty exclusive p even parity for the ptag and cs fields llock bit w write-back bit (set if cache line has been written) w write-back bit (set if cache line has been written) datap even parity for the data; 1-bit per byte data cache data table 7.3 primary d-cache line field description 23 27 0 1 l 25 26 pptag 1 f cs 1 2 23 22 4 35 0 31 32 32 datap data data datap data datap data datap data datap data datap data 36 1 w 24 37 w? 1 cache organization, operation, and coherency accessing the primary caches 79rc32334/332 user reference manual 7 - 5 june 4, 2002 notes figure 7.4 conceptual primary cache lookup sequence accessing the primary caches figure 7.5 shows the virtual address (va) index into the primary caches. for the rc32334 the instruc- tion cache is 8kb and the data cache is 2kb. figure 7.5 primary cache data and tag organization select select translation lookaside buffer(tlb) asid tag tag present? asid match? valid? data data ? data cache hit tlb miss asid tag tag data data ? = = virtual address tags va(9:4) va(9:4) data state data 32 tag line data line tag p w w cache organization, operation, and coherency primary cache states 79rc32334/332 user reference manual 7 - 6 june 4, 2002 notes primary cache states the terms below are used to describe the state of a cache line 1 : exclusive : a cache line that is present in exactly one cache in the system is exclusive. this is always the case for the rc32334. all cache lines are in an exclusive state. dirty : a cache line that contains data that has c hanged since it was loaded from memory is dirty. clean : a cache line that contains data that has not changed since it was loaded from memory is clean. shared : a cache line that is present in more than one cache in the system. the rc32334 does not provide for hardware cache coherency. this state will not occur during normal operations. the rc32334 supports the four cache states shown in table 7.4. under normal operations, the only states that will occur in the rc32334, ar e the dirty exclusive and invalid states. note: although valid data is in the dirty exclusive stat e, it may still be consistent with memory. one must look at the dirty bit, w, to determine if the cache line is to be written back to memory when it is replaced. each primary cache line in the rc32334 system is in one of the states described in table 7.4. primary cache states each primary data cache line is normally in one of the following states: invalid dirty exclusive. each primary instruction cache line is in one of the following states: invalid valid. cache line ownership the processor is the owner of a cache line when it is in the dirty exclusive state, and is responsible for the contents of that line. there c an only be one owner for each cache line. the ownership of a cache line is set and maintained through the rules described below. a processor assumes ownership of the cache line if the state of the primary cache line is dirty exclusive. 1. a cache line is the smallest unit of information that can be fetched from memory to be filled into the cache. a primary cache line is 16 bytes (4 words) in length and is represented by a single tag. upon a cache miss in the primary cache, the missing cache line is loaded from main memory into the primary cache. cache line state description invalid a cache line that does not contain valid information must be marked invalid, and cannot be used. a cache line in any other state than invalid is assumed to contain valid information. shared a cache line that is present in more than one cache in the system is shared. this state will not occur for normal operations. clean exclusive a clean exclusive cache line contains valid information and this cache line is not present in any other cache. the cache line is consistent with memory and is not owned by the proces- sor (see ?cache line ownership? on page 7-6 in this chapter). this state will not occur for normal operations. dirty exclusive a dirty exclusive cache line contains valid information and is not present in any other cache. the cache line may or may not be consistent with memory and is owned by the pro- cessor (see ?cache line ownership? on page 7-6 in this chapter). use the w bit to deter- mine if the line must be written back on replacement. table 7.4 primary cache states cache organization, operation, and coherency cache write policy 79rc32334/332 user reference manual 7 - 7 june 4, 2002 notes a processor that owns a cache line is responsible for writing the cache line back to memory if the line is replaced during the executi on of a write-back or write-back invalidate cache instruction if the line is in a write-back page. the cache instruction is explained in appendix a. memory always owns clean cache lines the processor gives up ownership of a cache li ne when the state of the cache line changes to invalid. therefore, based on these rules and that any valid dat a cache line is in the dirty exclusive state (under normal operating conditions), t he processor is considered to be the owner of the cache line. cache write policy the rc32334 caches use the same write algorithms defined for t he rc4700. these algorithms are specified by the ?c? bits 1 of a tlb entry or through the k0 field of the status register. the rc32334 processor manages its primary data cache by using either a write- back or a write-through policy selected on a per-page basis through the tlb. in a write-back cache, the dat a is not written back to memory until the cache line is replaced. a write-through policy means the store data is writt en to the cache and to memory. due to the write buffer, the write of the data to memory may not occur at the same time as the write to cache. for a write-back entry, if the cache line is valid and has been modified (the w bit is set), the processor writes this cache line back to memory when the line is replaced, either in the c ourse of satisfying a cache miss or during the execution of a write-back or write-back invalidate cache instruction. for a write-through entry, whenever a store hits in the cache line, the data is also written to memory via the write buffer. the store will not set or clear the w bit for a write-through cache line. this is to allow a different virtual address that maps to the same physi cal address and with a write-back policy to still set the w bit. for a miss to a write-through line, the action taken will be determined by the writ e-allocation policy. for a write-allocate entry, the cache line is first retrieved from memory and the store wi ll then continue. a no write- allocate entry will just post the write to the system inte rface, via the write buffer, in the same manner as an uncached write. store buffer to implement the write-back cache, the store instru ctions to cacheable memory operation must include a read/write sequence to the cache; the read first de termines whether the line is cache resident; the subse- quent write updates the appropriate bytes, dirty bit, and parity bits. to allow back-to-back data cache access, the rc32334 implements the same store buffer concept included with idt?s 64-bit riscontroller. this avoids extra stalls after st ore instructions to complete the read-modify-write sequence requi red to update the cache line. cache replacement policy the rc32334 uses the following algor ithm to select a cache line from the available sets for replace- ment: if both lines are invalid, select set a. if only one set is marked invalid, select that set. if one set is locked, select the other set. if both sets are locked, select set a 2 . if both sets are valid and unlocked, select the line which has been in the cache the longest. each cache line contains a ?fifo? bit to help det ermine which line was least recently replaced. 1. see table 5.1 in chapter 5 of this manual for bit values and attribute assignment. 2. this is an erroneous condition; however, the rc32334 handles this case deterministically. cache organization, operation, and coherency cache initialization 79rc32334/332 user reference manual 7 - 8 june 4, 2002 notes cache initialization the rc32334 includes 2kb of 2-way set associativ e data cache that corresponds to an address range between 0x000 and 0x7fc. the cache index offset for set a is 0x000, while the cache index offset for set b is 0x1000. to avoid any cache initialization problems, please select one of the following two initialization methods: 1. initialize index location 0x000-0x3f c for set a and then 0x1000-0x13fc for set b. or 2. initialize as if the data cache were at least 8k large. the i-cache tag should also be initialized using "c ache op" instruction with the index location 0x0000- 0x0ffc for set a, and then 0x1000-0x1ffc for set b. cache locking the rc32334 also supports a cache-locki ng feature that can be used to lock critical sections of code and/or data into on-chip ca ches to guarantee quick access. a portion of a cache is said to be locked when a particular piece of code or data is loaded into a cache location that will not be selected later for refill by other data. the locking feature of the rc32334 is on a per- line basis; that is, the kernel may set status register control bits that allow individual cache lines to be locked in the cache. locked cache lines can be changed by any of the following operations or conditions: cache operations store operations to cached virtual address if they become valid. when to use cache locking cache locking is useful in the following cases: a portion of code must reside in cache permanently (for example, time-critical exception vectors) for real-time performance a given section of code is executed frequently and c an fit inside a portion of the instruction cache a given section of data is accessed frequently and can fit inside the data cache (for example, tables containing routing information in an embedded network application). in the rc32334, both the instruction and data cache ar e two-way set associative, with set a and set b. by setting the dl or il bit in the status register of cp0, a refilled cache line of a selected set, at that time, can be locked in the appropriate cache; therefore, a futu re fill into this cache line will always use the other set. furthermore, if one set of a cache line has already been locked, the second attempt to lock this cache line will be ignored. as previously noted, a data store operation to locked data will update the d-cache contents; locking merely prevents the cache line contents from being repl aced by the contents of a different physical location. the locked cache line can be unlocked by using a cac he operation to invalidate that line. anytime the valid bit of a cache line is cleared, the lock bit is cleared simultaneously. t he basic algorithm presented here consists of the following three steps. 1. set the appropriate cache-lock enable bit(s). 2. load the critical code/data into the cache(s). 3. clear the appropriate cache lock enable bit(s). example: data cache locking for this example, assume an application in which a table must be kept in cache. after completing the initialization of data structures, etc., in the start-up code, the dl bit in the status register can be set to enable the cache line locking, perform reads thr ough cached addresses to load the data into the data cache, and then?to prevent further cache locking? cl ear the dl bit. a sample code fragment for the data cache locking operation follows: cache organization, operation, and coherency cache locking 79rc32334/332 user reference manual 7 - 9 june 4, 2002 notes .set noreorder jal flush_cache /* flush the cache */ mfc0 a0, c0_sr /* get old sr value */ li a1, sr_set_dl /* sr_set_dl = 0x00100000 */ or a0, a0, a1 mtc0 a0, co_sr /* set the lock bit for data cache */ nop nop nop /* 3 nops: safety agai nst cp0 hazard */ la t0, critical_table /* this table should always be in cache */ li t1, table_size /* size of table in bytes */ li t2, 0 /* number of bytes read into cache */ 1: lw a0, 0(t0) addiu t2, 4 bneq t2, t1, 1b /* loop back till done */ addiu t0, 4 /* bump read address */ mfc0 a0, c0_sr /* get old sr value */ li a1, sr_clr_dl /* sr_clr_dl = 0xffefffff */ and a0, a0, a1 mtc0 a0, c0_sr /* clear the lock bit for data cache */ nop nop nop /* 3 nops: safety ag ainst cp0 hazard */ example: instruction cache locking for this example, assume an applicat ion in which a critical function mu st be kept in cache. also assume that the size of the function is known. (if not known, the size can be det ermined by generating a disas- sembly of the object file.) after completing the initialization of data structures, etc., in the start-up code, the il bit of the status register can be set to enable cache line locking, per form the fill operation in the cache instruction that will fill the instruction cache with the critical func tion, and then?to prevent further cache locking?clear the il bit. a sample code fragment for the instru ction cache locking operation follows: .set noreorder jal flush_cache /* flush the cache */ la t0, 1f /* get address of label ?1? */ li t1, 0xa0000000 or t0, t0, t1 jr t0 /* uncached execution from now onwards */ nop 1: la t0, func_start_addr /* start address of critical code */ cache organization, operation, and coherency cache locking 79rc32334/332 user reference manual 7 - 10 june 4, 2002 notes li t1, func_size /* critical code size */ li t2, 0 /* number of words read into cache */ mfc0 a0, c0_sr /* get old sr value */ li a1, sr_set_il /* sr_set_il = 0x00080000 */ or a0, a0, a1 mtc0 a0, c0_sr /* set lock bit for instruction cache */ nop nop nop 2: cache fill_i, 0(t0) /* fill operation */ addiu t2, 4 bneq t2, t1, 2b /* loop back till done */ addiu t0, 4 /* bump read address */ mfc0 a0, c0_sr /* get old sr value */ li a1, sr_clr_il /* sr_clr_il = 0xfff7ffff */ and a0, a0, a1 mtc0 a0, c0_sr /* clear lock bit for instruction cache */ nop nop nop nop nop /* 5 nops: safety against cp0 hazard */ la v0, 3f jr v0 nop 3: /* resume execution in mode as linked */ notes 79rc32334/332 user reference manual 8 - 1 june 4, 2002 chapter 8 rc32334 internal bus introduction the rc32334 is an integrated processor which is logi cally an integration of two discrete existing idt devices; the rc32364 standalone cpu and the rc32134 system controller. the bus that connects the two discrete devices together, is replaced internally in the rc32334 integrated processor, referred to in this manual as the rc32300 cpu bus. although this bus in not visible external to t he rc32334, there are certain registers that need to be configured by the user. this c hapter discusses these aspects. generally, the rc32300 cpu bus features a multiplexed address/data bus and a number of associated control signals. a device controll er module latches and decodes the addr ess information originating from the rc32300 cpu core to determine which memory, i/o or peripheral module is being accessed, per the internal address map of the rc32334. list of features for rc32300 cpu bus internal 32-bit physical addressing internal 32-bit data bus internal command/data protocol internal generic read/write and burst read/write protocols internal bus arbitration modes internal chip select generation block diagram figure 8.1 ip bus bridge block diagram ipbus mem_addr[25:2] ip bus arbitration ip master/ address address reset, ack, buserr, transceiver control decode slave module control registers add mux/ demux gen address latching cpu core i/f rc3200 cpu bus rc32300 cpu core rc32334 internal bus functional overview 79rc32334/332 user reference manual 8 - 2 june 4, 2002 notes functional overview the rc32334?s internal bus bridge provides a trans lation from the rc32300 cpu biu interface control/ address bus to the internal ip bus. the rc32334?s internal ip bus is a synchronous command oriented bus that connects multiple dma masters and all of the peripheral slaves. the bri dge also provides address decoding and generates all address lines to the exter nal memory and i/o peripherals. the internal bus bridge contains the follo wing three main components: address module data module control module. address module the address module of the internal bus bri dge translates either the rc32300 cpu core generated addresses or addresses generated by internal modules (dma controller, pci interface) to the primary address lines, for use by the external memory syst em and i/o peripherals. the address module also gener- ates decoding for all external chip and internal module chip selects. address incrementer the system address that is used to interface to ex ternal memory such as prom or dram is incre- mented after each word (32-bit) access. rc32300 cp u core initiated reads must be incremented with subblock ordering, which is shown in figure 8.2. other accesses?inc luding those generated from the dma controller and pci bridge interface as well as all writes?increment addres ses with linear ordering. figure 8.2 subblock ordered data retrieval the rc32334 makes a system simplification and assume s that all accesses are 32-bit. thus, both the 8- and 16-bit proms must connect addr[3:2], be_n[1], and be_n[0] directly to the rc32334 if mem_addr[3.2] are used, in accordance with the tabl e within table 1.2, pin descriptions. the rc32334 will inadvertently increment (in subbloc k order) mem_addr[3:2] on each cpu byte access. for more informa- tion, refer to the using 8- or 16-bit boot pr oms section of chapter 10 for more information. address mux the rc32334 uses the first set of address lines (m em_addr[25:2]) to provide the address to external memory (rom, eprom, sram) and i /o peripherals. sdram, the address lines (mem_addr[15:2]) provide the dram row and dram column addresses. an address mux is implemented to map the address of the transaction on the proper address lines. more details on the address mapping convention for these operations are provided in the memory controll er section in chapter 10 and the synchronous dram controller section in chapter 11. w0 w1 w2 w3 w0 taken third w1 taken fourth w2 taken first w3 taken second 2 3 0 1 order of retrieval doubleword quadword rc32334 internal bus data module 79rc32334/332 user reference manual 8 - 3 june 4, 2002 notes address decode address decode takes the internally latched addr ess and generates both external chip selects and internal module chip selects, based on the memory map. some of the external chip selects are fixed to a particular physical address range. the address range of the other external chip selects is software programmable via the memory base address regist ers, memory base mask registers, dram base address registers, and dram base mask registers. these registers are described in the memory-io and dram chapters of this manual. also, the reset init ialization requires that the address latch timing register be setup to optimize timi ng by choosing a 1 clock or 2 clock address decode, as described later in this chapter. during the first clock of a trans action, the rc32334 decodes the address and compares it to the base address registers/constants from sdram, memory, pci, other peripherals, and c ontroller register banks. furthermore, on transactions selecting memory spac es within the sdram and memory controllers, each compare bit is masked to determine whether that bit is involved in the compare. the mask operation allows multiple banks of memory to be in a linear contiguous address space. note: in figure 8.3 through 8.5, cpu_ale_n and cpu_ad[ 31:0] signals are internal to the rc32334 and are shown for reference only. they are generated by the rc32300 cpu core. figure 8.3 address latch time with fast decode setting figure 8.4 address latch time with slow decode setting data module during read or write transactions to external memory and peripherals generated by the internal rc32300 cpu core, the rc32334 bus generates all c ontrol and address signals. thus, the rc32334 provides sufficient control signals to enable data driven from memory. cpu read/write operations during the data phase of a write operation, the rc32334 is the master of the bus and drives the data on cpu_ad[31:0] bus (see timing in figure 8.5). however, during the data phase of a read operation, external memory or i/o becomes bus master and drives the data on the mem_data[31:0] which is latched internally inside the rc32334 onto the cpu_ad[31:0] bus. idle addr/decode bus cycle idle addr data cpu_masterclk cpu_ale_n cpu_ad[31:0] mem_cs_n[0] mem_oe_n idle addr decode bus cycle idle addr data cpu_masterclk cpu_ale_n cpu_ad[31:0] mem_cs_n[0] mem_oe_n rc32334 internal bus dma read/write operations 79rc32334/332 user reference manual 8 - 4 june 4, 2002 notes figure 8.5 rc32334 cpu_ad[31:0] data phase dma read/write operations during dma operations, or when the pci bus is ac cessing main memory, the rc32300 cpu core is not involved in the transaction and the rc32334 is master of the internal cpu_ad[31:0] bus. during dma write operations, the rc32334 drives the address and the control signal to the memory and i/o peripherals and drives the data on the mem_data[31:0] bus. during dma read operations, the rc32334 drives the address and control signals to the memory or i/o periphera ls, which in turn returns the data to the rc32334 by driving the mem_data[31:0] bus. arbitration the rc32300 cpu core is the default bus master on the internal cpu_ad[31:0] bus. a rc32334 on-chip peripheral module requests the bus from the cpu co re when dma operations occur, or when the pci bridge reads or writes to the main memory. the rc32334 implements an internal arbi ter to arbitrate for the cpu_ad[31:0] bus in the following two options: 1. fixed (cpu, (0,1,2,3,pci)) 2. round robin after each grant: (cpu,( 0,1,2,3,pci)), (cpu,(1,2,3,pci,0)), (cpu,(2,3,pci,0,1)),... the cpu_ad[31:0] bus protocol enables the cpu core to request the bus after it has been granted by de- asserting the busgnt_n signal (an inter nal signal not visible to devices and external to the rc32334). thus, between any two dma accesses, the cpu will typica lly issue an access. however, if a dma request is pending, the cpu will always give the bus up after its present transaction completes. memory port sizing the rc32334 divides the physical memory space into 12 regions. the port width of each region can be configured in the rc32334?s port-width control regist er. physical memory space in the rc32334 is divided into 12 distinctive regions (typical mapping of the physical regions is shown in table 1.4). the port-width sizes of the dram (a,b,c,d) and pci (j & k) regions are al ways 32-bit; however, the port-width sizes of the memory and i/o regions (h & i) are programmable through the port-width field of the memory controller register, as described later in this chapter. bus turnaround (bta) register the rc32364 biu core includes a bta register that s pecifies, per memory region, the number of clock cycles the cpu core will wait before issuing a new tr ansaction after completing a read operation. a similar bta feature is included in the rc32334 peripheral controller. this bta feature allows slow-to-disable-data devic es such as eprom to share a data bus with other devices. rc32334 does not allow a transaction to fo llow a read in less than the bta value setup per address block. similar to the rc32300 cpu core bt a register, all rc32334 bta settings in the peripheral controller are set to their maximum of ?3? at rese t. the software operating system kernel should program this register immediately as part of the power-up/reset boot sequenc e. a field description table (table 8.8) and format diagram (figure 8.8) for this register ar e provided in the register descriptions section of this chapter. idle addr data idle addr data cpu_masterclk cpu_ale_n cpu_ad[31:0] mem_oe_n rc32334 internal bus watchdog timer 79rc32334/332 user reference manual 8 - 5 june 4, 2002 notes watchdog timer as part of the timer module, a watchdog timer is included that works as a safeguard mechanism to assist in detecting runaway software. the watchdog time r will issue an internal cpu_reset_n (warm reset) to the cpu core if the watchdog timer rolls over. when the rc32334 issues a warm reset, it does not affect the rc32334 reset boot-mode settings. normally, the software operating system kernel must occasionally reset the timer count register (to 0x0000_0000 ) so that the rollover does not occur. in standard-boot mode, the watchdog timer func- tion is enabled at reset. if the os kernel chooses not to implement this function, the boot code must, at a minimum, disable this function by wr iting to the buserror control regi ster of the ip bridge. a watchdog timer status bit indicates if the last reset was caused by the watchdog timer. in pci-boot mode, the watchdog timer is disabled at reset. bus time-out counters two 16-bit software programmable bus time-out counters are also prov ided, each with its own compar- ator: software programmable abort, in cluding externally generated wait -states. there is a software programmable enable/disable bit. in addi tion to the abort, an internal inte rrupt is generated. a bus time-out terminates the present data of a memory transacti on, causing buserror_n and ack_n (both signals internal to the rc32334 interconnecting the system controller to the cpu) to be returned. the bus time-out setting is typically calculated from the maximum burst lengt h of the rc32334 at 4 words using its slowest transac- tion. typically, an 8-bit boot eprom burst transfer of 4 words (16 bytes) is the longest possible transfer. when a bus time-out occurs, the present physical address is latched into the bus error register. bus error timers the rc32334 includes two bus error timers. the first is used for rc32364 biu core bus time-outs and will time-out if the cpu bus is held too long. beca use the present implementation of rc32334 always gets the cpu bus when an ip access is in process, a cpu bus time-out also causes an internal ip bus time-out. for systems that must distinguish between cpu and ip accesses, an optional ip bus time-out timer is provided. this timer will only assert if the ip bus is held too long, regardless of the cpu bus time-out. most systems will not need to use this timer and can reassi gn the timer for general purpose usage. if used, the ip bus time-out timer is typically set to 1 more than the cpu bus time-out, so that the two cases can be distin- guished by the bus error status bits. register descriptions address register ffff_e200 cpu port width register ffff_e204 cpu bta register ffff_e208 cpu buserror address register table 8.1 cpu bus interface control registers address register 1800_0000 bta register 1800_0004 address latch timing register 1800_0008 arbitration register table 8.2 cpu to ip register addr esses and descriptions (part 1 of 2) rc32334 internal bus interface control registers 79rc32334/332 user reference manual 8 - 6 june 4, 2002 notes interface control registers the following three interface cont rol registers are used in the rc32334: the cpu port-width control register controls attr ibutes of the various memory systems and is used to interface the rc32334 to va rying width memory regions. the cpu bus turnaround (bta) control register cont rols the bus turnaround cycle(s) for the various memory systems. the rc32334 divides the physica l address space into various sub-regions, each of which features independently programmable bus turnaround cycle(s). the cpu bus error address register holds the ph ysical address of the transfer that signalled the most recent bus error. cpu port-width control register: virtual address 0xffff_e200 the rc32334 divides the physical address space into va rious sub-regions, each of which features inde- pendently programmable port widths. at reset, all memory widths are set to the width of the boot prom. soft- ware may then re-program the widths of various regions to meet the actual system implementation. using the port width control register allows softw are to be fully independent of the actual system imple- mentation; software may then treat all references as if the memory was 32-bits wide and relies on the rc32334 to manage the bus interaction with the ac tual memory system to satisfy this model. the format of the cpu port width control register is shown in figure 8.6. table 8.3 lists the register?s fields and content descriptions. note: region g should always be programmed to 32-bit port width during boot code initialization before the system controller registers are used. figure 8.6 format of cpu port width control register 1800_0010 buserror control register 1800_0014 buserror address register 1800_0018 sysid register field description 0reserved regiona width of region regiona regionb width of region regionb regionc width of region regionc regiond width of region regiond regione width of region regione table 8.3 port width control register field definition (part 1 of 2) address register table 8.2 cpu to ip register addr esses and descriptions (part 2 of 2) 31 2 2 0 2 30 29 28 region a 27 26 region b 25 24 region c 23 22 region d 21 20 region e 19 18 region f 17 16 region g 15 14 region h 13 12 region i region j 11 10 2 2 2 2 22 22 6432 mem region f region k region l region m 9 8 7 region o 510 2222 2 region n rc32334 internal bus interface control registers 79rc32334/332 user reference manual 8 - 7 june 4, 2002 notes width fields are encoded as shown in table 8.4. the address ranges served by each nam ed region are listed in table 8.5. the memory space is divided as follows: the 512mb of kseg0/1 are divided into eight 64m b sub-regions, each of which can have indepen- dent widths. thus, four widths can be reached cacheably, and four widths can be reached uncache- ably. the cache management algorithm for kseg0 is spec ified in the k0 field of the status register. the remaining memory space?3.5gb?is divided into seven equal sections of 512mb, each of which can have independent widths. in addition, the ca che attributes of each page within the region can be controlled using the tlb. regionf width of region regionf regiong width of region regiong regionh width of region regionh regioni width of region regioni regionj width of region regionj regionk width of region regionk regionl width of region regionl regionm width of region regionm regionn width of region regionn regiono width of region regiono width(1) (msb) width(0) (lsb) port width 0 0 8 bits 0 1 16 bits 1 0 32 bits 11reserved table 8.4 encoding of 8-, 16-, and 32-bit port widths region name physical address (31:26) comments regiona 0000 00 64mb regionb 0000 01 64mb regionc 0000 10 64mb regiond 0000 11 64mb regione 0001 00 64mb regionf 0001 01 64mb regiong 0001 10 64mb regionh 0001 11 64mb regioni 001x xx 512mb regionj 010x xx 512mb regionk 011x xx 512mb table 8.5 memory region address ranges (part 1 of 2) field description table 8.3 port width control register field definition (part 2 of 2) rc32334 internal bus interface control registers 79rc32334/332 user reference manual 8 - 8 june 4, 2002 notes cpu bus turnaround (bta) control register: virtual address 0xffff_e204 at reset, all memory sub-regions will be programmed to the maxi mum of 3 turnaround cycles, and soft- ware may then re-program this register to achieve maximum system performance. the format of the bta register is shown in figure 8.7. this register?s fields and content descriptions are listed in table 8.6. note: region g should always be programmed to a bt a=1 during boot code initialization. in general, most regions can use bta=1. note that the t recovery cycle, shown in figure 8.9, is used by the rc32334 to pre-charge the mem_dat a bus during cpu-generated accesses. thus, the bta=0 setting should never be used unless proper bus isolation techniques are utilized, such as with q-logic transceivers. figure 8.7 cpu bus turnaround (bta) control register format regionl 100x xx 512mb regionm 101x xx 512mb regionn 110x xx 512mb regiono 111x xx 512mb field definition 0reserved 0reserved regiona turnaround cycle(s) of region regiona regionb turnaround cycle(s) of region regionb regionc turnaround cycle(s) of region regionc regiond turnaround cycle(s) of region regiond regione turnaround cycle(s) of region regione regionf turnaround cycle(s) of region regionf regiong turnaround cycle(s) of region regiong regionh turnaround cycle(s) of region regionh regioni turnaround cycle(s) of region regioni regionj turnaround cycle(s) of region regionj regionk turnaround cycle(s) of region regionk table 8.6 cpu bus turnaround (bta) control re gister field descriptions (part 1 of 2) region name physical address (31:26) comments table 8.5 memory region address ranges (part 2 of 2) 31 2 2 0 1 30 0 29 28 region a 27 26 region b 25 24 region c 23 22 region d 21 20 region e 19 18 region f 17 16 region g 15 14 region h 13 12 region i region j 11 10 12 2 2 2 22 22 6432 mem region f region k region l region m 9 8 7 region o 510 2222 2 region n rc32334 internal bus interface control registers 79rc32334/332 user reference manual 8 - 9 june 4, 2002 notes the turnaround cycle(s) is encoded as shown in table 8. 7. after a read access, it indicates the minimum number of turnaround clock cycles that must occur befor e the next read or write access can occur. figure 8.9 shows the timing of the bta cycle. note the clock cycle denoted by the t ta symbol indicates the minimum number of turnaround cycles that must occur after a read access. cpu bus error address register (read only): virtual address 0xffff_e208 this is a read only register that holds the address that caused the bus error. any attempts to write to this register will not change its value, which is not defined before the bus error is sampled. bta control register note: although this register exists, it is not functional. refer to the rc32334/rc32332 device errata, located at www.idt.com, for additional information. bus turnaround time refers to that period of time after a read transaction ends before the next transac- tion can begin. this time period allows the memory, or it s transceiver just read, to tri-state its data from the ad bus before the next address is driven out by the cpu as shown in figure 8.9 on page 8-11. on the rc32334, the bta register is used within dm a transactions, whenever a read occurs, and does not allow a transaction to follow a read in less than the bta value setup per address block. at reset, all memory subregions are programmed to the maximu m of 3 turnaround cycles, and software should then reprogram this register to achieve maximum sy stem performance. a setting of ?1? is typical. after a dma descriptor burst read, no bus tur naround (bta) clocks are inserted and a cpu address may appear on the mem_data [] bus as soon as 2 clocks after the dma descriptor read. note: region g, which sets the bta for the rc 32334 internal register space, must be programmed to a setting of ?1? or greater. the format of the bta control register is shown in fi gure 8.8. this register?s fields and content descrip- tions are listed in figure 8.8. the regions shown correspond to the bta regions described in the rc32334?s bta register. regionl turnaround cycle(s) of region regionl regionm turnaround cycle(s) of region regionm regionn turnaround cycle(s) of region regionn regiono turnaround cycle(s) of region regiono ta(1) (msb) ta(0) (lsb) turnaround cycle(s) 0 0 0 cycle 0 1 1 cycle 1 0 2 cycles 1 1 3 cycles table 8.7 width encoding of bus turnaround cycles field definition table 8.6 cpu bus turnaround (bta) control re gister field descriptions (part 2 of 2) rc32334 internal bus interface control registers 79rc32334/332 user reference manual 8 - 10 june 4, 2002 notes figure 8.8 bus turnaround (bta) control register format the turnaround cycle(s) is encoded as shown in table 8.9. figure 8.9 shows the timing of the bta cycle. field definition 0 reserved 0 reserved region a turnaround cycle(s) of region region a region b turnaround cycle(s) of region region b region c turnaround cycle(s) of region region c region d turnaround cycle(s) of region region d region e turnaround cycle(s) of region region e region f turnaround cycle(s) of region region f region g turnaround cycle(s) of region region g 1 1. it is mandatory to program region g for at least 1 cycle turnaround. region h turnaround cycle(s) of region region h region i turnaround cycle(s) of region region i region j turnaround cycle(s) of region region j region k turnaround cycle(s) of region region k region l turnaround cycle(s) of region region l region m turnaround cycle(s) of region region m region n turnaround cycle(s) of region region n region o turnaround cycle(s) of region region o table 8.8 bus turnaround (bta) cont rol register field descriptions ta(1) (msb) ta(0) (lsb) turnaround cycle(s) 0 0 0 cycle 0 1 1 cycle 1 0 2 cycles 1 1 3 cycles (default) table 8.9 width encoding of bus turnaround cycles 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 region a region b region c region d region e region f region g 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 region h region i region j region k region l region m region n region o rc32334 internal bus address latch timing register 79rc32334/332 user reference manual 8 - 11 june 4, 2002 notes figure 8.9 timing of bus turnaround cycle(s) (example of 1 cycle bta) these are internal signals and are sh own here for reference purposes only. address latch timing register the address latch timing register delays initial address decode from the rc32300 cpu core biu by 1 clock until the first rising clock edge after the internal cpu_ale asserts. this mode pipelines the address decode such that 50mhz and faster systems have ample setup time to properly select a register/memory before a synchronous clock edge. at reset, the default is to take the delay. thus systems that are running at less than 50mhz must reprogram the memory contro ller address latch timing bit to ?decode address? so that performance is increased. the address latch ti mes with fast and slow decode settings are shown in figures 8.3 and 8.4. figure 8.10 address latch timing register bit field name description 31:3 reserved 2 dram controller address latch timing 1 memory controller address latch timing 0 ip register controller address latch timing reserved to 1 to delay the address decode by 1 clock. table 8.10 address latch timing bit field descriptions cpu_masterclk cpu_ad[31:0] cpu_ack_n cpu_cip_n cpu_last_n t recovery t data t addr t data data addr data t ta ip controller address timing memory controller address latch timing dram controller address latch timing reserved 31 3 2 1 0 setting bus frequency 1 delay address decode by 1 clock for sys- tems running at > 67 mhz 0 don?t delay address decode by 1 clock, for systems running at 67 mhz (default) setting description 1 delay address decode by 1 clock, for sys- tems running at 50 mhz (default) 0 decode address on falling edge of ale, for systems running at < 50 mhz rc32334 internal bus address latch timing register 79rc32334/332 user reference manual 8 - 12 june 4, 2002 notes arbitration register the arbitration register is used to select the arbitration method used for prioritizing access to the cpu bus by the cpu core, the pci bridge and the dma controll er channels. for the specific details of this oper- ation, refer to the dma controllers section in chapter 13. figure 8.11 arbitration register field buserror control register the bus error register stores the current addres s of any transaction?read, write, cpu generated, dma generated, or pci generated. bus errors occur if a bus time-out occurs and no memory space is selected. for cpu generated transactions, the rc32334 will assert the buserr_n to the cpu and will termi- nate the transaction. the fields of the buserror register are shown in figure 8.12. the function of each field is listed in table 8.12. note: if the pci-boot mode is selected at reset time, the cpu buserror, ip buserror, and watchdog bits are disabled. figure 8.12 buserror control register fields buserror address register rc32334?s buserror address regist er (see figure 8.13) is simila r to the rc32334 on-chip cpu bus error address register, and for cp u generated transactions, the value s hould be the same in both regis- ters. the rc32334 bus error register is also used on dma operations and bus time -out errors. the inter- rupt pending register is used to fi rst determine whether an error occurred as a result of a bus error (non- decoded address) or a bus time-out (acknowledge never returned). the def ault value of this register is 0x0000_0000. note: on bus errors, if the cpu transaction was a r ead, a bus exception is generated in addition to an interrupt. if the cpu transaction was a write, an interrupt is generated but no bus exception is taken. this behavior occurs because the cpu write buffer cannot re-align the original store instruction issuance with the bus error. figure 8.13 buserror address register value description 1 round robin arbitration 0 fixed priority arbitration (default) table 8.11 arbitration field values and action description 0 31 1 round robin vs. fixed reserved watchdog enable watchdog status cpu bus time-out enable ip bustimeout enable cpu source status ip source status rd/wr bus time-out status "0" reserved 31 8 7 6 5 4 3 2 1 0 buserr exception 0 31 bus error address rc32334 internal bus address latch timing register 79rc32334/332 user reference manual 8 - 13 june 4, 2002 notes bits field name description 31:8 reserved to "0" for future compatibility, must be written as "0". 7 buserror read exception dis- able on a buserror, if this bit is low, a physical bus error and an interrupt (if enabled) to the cpu is generated on cpu accesses, thus terminating the cpu access. also, on a phys- ical bus error, cpu reads take an exception/interrupt, while cpu writes take an interrupt. if this bit is high, then neither a bus error nor a bus error read exception is generated, the access is terminated, and an interrupt (if enabled) is generated. 6 watchdog enable when watchdog enable is enabled, when the watchdog timer reaches its compare count and overflows, a warm reset will be generated to the cpu core. to prevent the watchdog timer from generating a reset, rc32334 systems must have enough os ker- nel support to occasionally zero out the watchdog timer count register or to disable the watchdog function from resetting the cpu. 5 watchdog reset status when a warm reset is caused by the watchdog timer overflowing, the watchdog reset status bit field is set to?1?. the status bit may be reset by a software write to the register changing that bit value as a ?0?. 4 cpu buserror enable if the cpu buserror enable is set, then if the cpu buserror timer reaches its compare count and thus overflows, a buserror and an interrupt (if enabled) will be generated to the cpu core. this buserror is caused either by the cpu core taking too long or by the cpu core generating an undecodable address. see the buserror exception disable (bit 7) for more information. table 8.12 buserror control register field descriptions (part 1 of 2) value description 1disabled 0 enabled (default) value description 1 enabled (default) 0disabled value description 1 watchdog reset occurred 0 watchdog reset has not occurred (default) value description 1 enabled (default) 0disabled rc32334 internal bus address latch timing register 79rc32334/332 user reference manual 8 - 14 june 4, 2002 notes sysid register the sysid register can be used by boot os software to recognize the type of system controller being used and to initialize it accordingly.the sysid is unique to each type of idt system controller. it can be used to differentiate between a system consis ting of the discrete rc32364 cpu and rc32134 system controller parts versus the fully integrated rc32334 par t. the sysid register can also be used to differen- tiate between any hardware silicon revision upgrade improv ements that might occur in the future. for soft- ware users, the sysid is similar and can be used in conjunction with the cpu core cp0 processor revision id register (prid). for hardware and hardware debug s ystems, the sysid is also similar in concept and can be used in conjunction with the jtag device id register and the ejtag deviceid register. figure 8.14 sysid register fields 3 ip bustimeout enable if the ip buserror enable is set, then if the cpu buserror timer reaches its compare count and thus overflows, an ip buserror and an interrupt (if enabled) will be generated to the ip bus and if an on-chip peripheral module or the cpu core owns the cpu bus, a buserror will be generated to the cpu core. this buserror is caused either by dma tak- ing too long or by dma generating an undecodable address. see the buserror excep- tion disable (bit 7) for more information. note that the ip bus timeout value (in nsec) must be greater than the pci retry timeout multiplied by the trdy timeout value (in nsec). . 2 cpu source if a cpu buserror is caused by the cpu buserror timer overflowing, then the cpu buserror status bit field is set. the status bit may be unset by a software write to the register with that bit value as a ?0?. 1 ip source if an ip buserror is caused by the ip buserror timer overflowing, then the ip buserror status bit field is set. the status bit may be unset by a software write to the register with that bit value as a ?0?. in the present rc32334 implementation, a cpu bus error also sets the ip buserror status bit. 0 read/write type bits field name description table 8.12 buserror control register field descriptions (part 2 of 2) value description 1 enabled (default) 0 disabled value description 1 cpu buserror occurred from a cpu transaction 0 cpu buserror did not occur (default) value description 1 ip buserror occurred from an ip transaction 5 mhz 0 ip buserror did not occur (default) value description 1 buserror occurred on a read 0 buserror occurred on a write (default) implementation id / part id major revision minor revision vendor id 31 20 19 8 7 4 3 0 rc32334 internal bus address latch timing register 79rc32334/332 user reference manual 8 - 15 june 4, 2002 notes bits field name description 31:20 vendor id vendor is idt (0x000) 19:8 implementation id/part id part id is rc32334 (0x002) part id is rc32332 (0x004) 7:4 major revision major revision: rev z silicon is (0x0) rev y silicon is (0x1) reserved for future major revisions (0x2?0xf) 3:0 minor revision minor manufacturing revision number within a major revision. base minor revision (0x0) 1st minor revision (0x1) reserved for future minor revisions (0x2?0xf) table 8.13 sysid register field descriptions rc32334 internal bus address latch timing register 79rc32334/332 user reference manual 8 - 16 june 4, 2002 notes notes 79rc32334/332 user reference manual 9 - 1 june 4, 2002 chapter 9 external local bus interface introduction as described at the beginning of chapter 8, the rc 32334 integrated processor is a logical integration of two components, a stand-alone cpu core prev iously implemented in the rc32364 device and a companion rc32134 system controller. this chapter des cribes the bus (called local bus) that is used to connect external devices to the rc32334. the local bus includes the following: separate address and data busses control signals (chip selects, wait signal, etc.) debug signals for logic analyses figure 9.1 external local bus interface unit block diagram operation the rc32334 local bus interface unit combines the internal busses from the cpu core and from the system controller. the local address bus, mem_addr[25:2] 1 , is formed by the internal system controller latching the address on the rc32300 and then redriving it out. it also shifts the address signals appropri- 1. in the rc32332, this local address bus is mem_addr[22:2]. boundary scan cells boundary scan cells cpu system controller boot vector muxing, mem_we_n muxing boundary scan cells boundary scan cells mem_addr[] mem control sdram control dma control pio control spi control uart control timer control mem_data[] pci bus cpu_coldreset_n ejtag_tms jtag_tms, jtag control cpu bus control cpu_reset_n cpu_masterclk pll ejtag rst timer ad bus ad bus bidirectional multiplexer cells external local bus interface variable port-width interface 79rc32334/332 user reference manual 9 - 2 june 4, 2002 notes ately during sdram ras cycles. mem_addr[1:0] are fo rmed by multiplexing the cpu address signals [1:0] onto the mem_we_n signals. the rc32334 local bus inte rface unit also combines the internal data busses from the cpu and from the system controller via a transceiver . the transceiver implementation does not carry internally tristated components, but uses multiplexing instead. similarly, common signals between the cpu and system controller internal components are combined. other output only signals, such as cpu_dt_r_n, c an be an output from both the cpu and the system controller. during cpu controlled cycl es, it is driven from the cpu, and during system controller controlled cycles, it is driven from the system controller. duri ng idle bus cycles, cpu_dt_r_n tristates on the local bus and thus requires an external pull-up resistor. similarly, jtag_tdo, the jtag output drives dat a from the system controller boundary scan register when the appropriate jtag command is scanned via jt ag_tms and drives data from the cpu ejtag when the appropriate ejtag command is scanned via ejtag_t ms. the use of jtag_tdo assumes that both jtag and ejtag are not programmed simultaneously. the reset boot mode vectors are formed by multip lexing inputs onto the appropriate cpu and system controller inputs during cold reset. variable port-width interface the rc32334 supports a variable port-width interface. the technique used to determine the port width is a start-up and software mechanism that assigns attri butes to a region of physical (not virtual) memory. the rc32334 reset-mode initialization interface s upports the setting of the boot-prom port width. to simplify design, the rc32334 elects to use the same data lines, for a given width of memory, regard- less of memory byte-ordering (endianness 1 ). table 9.1 lists which byte lanes are used and table 9.2, table 9.3, and table 9.4 list the data transfer s equences for 8-, 16-, and 32-bit port widths. 1. little/big-endian byte ordering conventions are discussed in chapter 1 of this manual. port width data lines 8-bit d(7:0) 16-bit d(15:0) 32-bit d(31:0) table 9.1 port width assignments to data lines port width transfer size byte address endianness data lines 8-bit 1 byte 0, 1, 2, 3 big d(7:0) 8-bit 2 bytes 0, 2 big d(7:0) 2 times 8-bit 3 bytes 0, 1 big d(7:0) 3 times 8-bit 4 bytes 0 big d(7:0) 4 times 8-bit 16 bytes 0 big d(7:0) 16 times 8-bit 1 byte 0, 1, 2, 3 little d(7:0) 8-bit 2 bytes 1, 3 little d(7:0) 2 times 8-bit 3 bytes 3, 2 little d(7:0) 3 times 8-bit 4 bytes 3 little d(7:0) 4 times 8-bit 16 bytes 3 little d(7:0) 16 times table 9.2 data transfer sequences for 8-bit port width external local bus interface variable port-width interface 79rc32334/332 user reference manual 9 - 3 june 4, 2002 notes port width transfer size byte address endianness data lines 16-bit 1 byte 0, 2 big d(15:8) 16-bit 1 byte 1, 3 big d(7:0) 16-bit 1 byte 0, 2 little d(7:0) 16-bit 1 byte 1, 3 little d(15:8) 16-bit 2 bytes 0, 2 big d(15:0) 16-bit 2 bytes 0, 2 little d(15:0) 16-bit 3 bytes 0 big d(15:0), d(15:8) 16-bit 3 bytes 1 big d(7:0), d(15:0) 16-bit 3 bytes 0 little d(15:0), d(7:0) 16-bit 3 bytes 1 little d(15:8), d(15:0) 16-bit 4 bytes 0 big d(15:0) 2 times 16-bit 4 bytes 0 little d(15:0) 2 times 16-bit 16 bytes 0 big d(15:0) 8 times 16-bit 16 bytes 0 little d(15:0) 8 times table 9.3 data transfer sequences for 16-bit port width port width transfer size byte address endianness data lines 32-bit 1 byte 0 big d(31:24) 32-bit 1 byte 1 big d(23:16) 32-bit 1 byte 2 big d(15:8) 32-bit 1 byte 3 big d(7:0) 32-bit 1 byte 0 little d(7:0) 32-bit 1 byte 1 little d(15:8) 32-bit 1 byte 2 little d(23:16) 32-bit 1 byte 3 little d(31:24) 32-bit 2 bytes 0 big d(31:16) 32-bit 2 bytes 2 big d(15:0) 32-bit 2 bytes 0 little d(15:0) 32-bit 2 bytes 2 little d(31:16) 32-bit 3 bytes 0 big d(31:8) 32-bit 3 bytes 1 big d(23:0) 32-bit 3 bytes 0 little d(23:0) 32-bit 3 bytes 1 little d(31:8) 32-bit 4 bytes 0 big d(31:0) 32-bit 4 bytes 0 little d(31:0) 32-bit 16 bytes 0 big d(31:0) 4 times 32-bit 16 bytes 0 little d(31:0) 4 times table 9.4 data transfer sequences for 32-bit port width external local bus interface debug signals 79rc32334/332 user reference manual 9 - 4 june 4, 2002 notes debug signals the rc32334 provides a set of debug signals for logic analyzer use. the four signals debug_cpu_ads_n, debug_cpu_ack_n, debug_cpu_dma_n and debug_cpu_i_d_n are used as reset mode bits during the assertion of cpu_col dreset_n as shown in figure 19.9. these four signals begin driving from the rc32334 after cpu_coldreset_n de- asserts. debug_cpu_ads_n, debug_cpu_ack_n and debug_cpu_dma_n become valid 2 clocks after cpu_coldreset_n de-asserts. debug_i_d_n does not become valid until the first debug_ads_n asserts. during a bus transaction, debug_cpu_ads_n will asse rt low for 1.0 clock. debug_cpu_ads_n asserts for both cpu generated transactions and for dm a generated transactions. whenever debug_cpu_ads_n asserts, debug_cpu_dma_n will indicate th e source of the transaction as be ing from the cpu or from dma and whether the source is for an instruction or for data via the debug_cpu_i_d_n signal. during all dma, debug_cpu_i_d_n will always indica te data as being the source. also when debug_cpu_ads_n asserts, mem_data[31:4] bus will contain the physical address of the quad-word block where the transaction is occurring. if the transaction is from dma, then mem_data[3:2] will also indicate the word address from which the transaction is occurring. if the transaction is from the cpu, then the mem _addr[3:2] lines must be used to determine the word address. depending on the address latch timing regi ster and memory versus sdram cas cycle occur- ring, the earliest strobe point for mem_addr[3:2] ma y vary. if an 08-bit wide or 16-bit wide transaction is performed via the memory controller, then address bits 1 and/or 0 may be taken off of mem_we_n bus. after debug_cpu_ads_n asserts, 1.0 clock later and th roughout the transaction, cpu_dt_r_n indicates whether the transaction is a write or when asserted, a read. note that cpu_dt_r_n may assert earlier than 1.0 clock after debug_cpu_ads_n, especially during a cp u transaction, but definitely not during a dma transaction. finally, after the appropriate number of internal wait-states has occurred, debug_cpu_ack_n will assert to indicate that data is being latched on a read, or t hat data is finished being transmitted on a write. note that on a burst transaction, debug_cpu_ac k_n will assert for each datum. external local bus interface debug signals 79rc32334/332 user reference manual 9 - 5 june 4, 2002 notes figure 9.2 debug signals during a read in figure 9.2, the debug signals are shown for a si ngle word read, starting with the assertion of debug_cpu_ads_n. a 32-bit wide memory read of 1 word is shown. note that the exact number of clocks between debug_cpu_ads_n and mem_cs_n[x] (sdram_cs_n[x]) may vary depending on such factors as the address latch delay setting and on the ex act source of a cpu/dma transaction. 1 2 3 4 5 6 cpu or dma instruction or data 40000 40000 read data 1111 1111 1111 tdo3, tdo3, tdo20, tdo20, tdo20, tdo20, tdo20, tdo20, tdo20, tdo20, thld tsu cpu_masterclk debug_cpu_ads_n debug_cpu_dma_n debug_cpu_i_d_n mem_addr[25:2]<<2 mem_data[31:4]<<4 debug_cpu_ack_n mem_cs_n[0] mem_oe_n mem_we_n[3:0] cpu_dt_r_n mem_245_oe_n mem_wait_n tdoh20 tdoh20 tdoh20 tdoh20 tdoh20 tdoh20 tdoh20 tdoh20 tdoh3 tdoh3 external local bus interface debug signals 79rc32334/332 user reference manual 9 - 6 june 4, 2002 notes figure 9.3 debug signals during a write. in figure 9.3, the debug signals are shown for a si ngle word write, starting with the assertion of debug_cpu_ads_n. a 32-bit wide memory write of 1 word is shown. note that the exact number of clocks between debug_cpu_ads_n and mem_cs_n[x] (sdram_cs_n[x]) may vary depending on such factors as the address latch delay setting and on the ex act source of a cpu/dma transaction. 1 2 3 4 5 6 7 cpu or dma instruction or data 40000 40000 write data 1111 0000 1111 tdo3, tdoh3 tdo3, tdoh3 tdo20, tdo20, tdo20, tdo20, tdo20, tdo20, tdo20, tdo20, thld tsu cpu_masterclk debug_cpu_ads_n debug_cpu_dma_n debug_cpu_i_d_n mem_addr[25:2]<<2 mem_data[31:4]<<4 debug_cpu_ack_n mem_cs_n[0] mem_oe_n mem_we_n[3:0] cpu_dt_r_n mem_245_oe_n mem_wait_n tdoh20 tdoh20 tdoh20 tdoh20 tdoh20 tdoh20 tdoh20 tdoh20 notes 79rc32334/332 user reference manual 10 - 1 june 4, 2002 chapter 10 memory controller introduction the rc32334 memory controller provides the cont rol signals, address lines, and wait-state engine for interfacing rc32334 integrated processor to standard sram, prom, flash and i/o. it also includes the boot-prom interface. six individual chip selects are al so available, providing di rect support of 8-, 16-, and 32-bit wide memory and i/os. the first two chip selects have highly configurable address ranges, allowing the selection of support for various memory types and widths. the last 4 ch ip selects have fixed address ranges. the rc32334 can interface directly to 8-/16-/32-bit boot-prom widt h support, and has extra write protection for flash as well as a programmable number of wait-states for various speeds of memory and i/os. for systems that require fast signalling with large loads, rc32334 also has controls for optional external data transceivers. list of features ? six chip selects ? 2 highly configurable addres s range decoders, 64kb to 64mb 1 each, anywhere within 4gb ? 4 fixed address range decoders, 32 mb each 1 ? 8-/16-/32-bit memory and i/o support selectable sram, two different i/o s, and dual-port protocol modes programmable number of wait-states single word read/write and burst read/write support external wait-state pin for debug emul ator memory or dual-port memory flash default write protection controls optional fct245 transceiver 8/16/32-bit boot-prom support block diagram this functional block diagram represents the memory and i/o control unit of the rc32334. figure 10.1 block diagram of rc32334 memory controller 1. to 8mb each for the rc32332. memory_block_with_ip ip_bus ip slave interface control_reg sram state machine memory_block datain[31:0] dataout[31:0] slave_datain[31:0] slave_dataout[31:0] data_in[] data_out[] wa i t- s tat e rc32300 cpu core bus biu_mem_sel[] biu rc32300 cpu core bus interface dtr_n, ack_n cip_n, wr_n, counter dpm state machine iom state machine ioi state machine mem_cs[], mem_oe_n, mem_rd_n, mem_wr_n[3:0] mem_wait_n last_n ack_n, mux/demux arbiter cip_n dt_r_n increment_addr_n memory controller functional overview 79rc32334/332 user reference manual 10 - 2 june 4, 2002 notes functional overview the rc32334 memory controller controls six memory or i/o peripheral regions. each region has an associated chip select line (mem_cs_n[5:0]), but shar es the rest of the control and address signals. to meet the system?s needs, each memory and i/o region can be independently configured. configuration options available for each bank are: ? address range (cs 0 and 1 only) ? memory type ? port width ? wait-states and access speed, during read and write operations each of these configuration options is enabled th rough the corresponding set of registers for each bank, which, at reset, will default to the user?s previously software defi ned base configuration. memory controller operation the memory controller is activated when the cpu, dma controller, or the pci bridge issues a read or write transaction that is within the range of any of the six memory and i/o regions. integrated processor generated transactions when the controller issues a read or a write operati on to an external memory or i/o peripheral, the memory controller looks at the address compares it with the address range of the six regions. if the address matches, the memory controller supplies the address bus , the various control signals, as well as the chip select for that region. the appropriate configuration of the various regist ers enables the memory controller to assert the appropriate control signal and end the transaction at the specified time. the memory controller allows the controller to perform single or burst (up to 4 words) transfers from/to the memory and i/o peripherals for the read and write transfers. burst read transactions from the c ontroller use a subblock ordering me thod, as shown in figure 10.2. a subblock ordered transaction allows the system to def ine the order in which the data elements are retrieved. figure 10.2 subblock ordered burst read sequences dma controller or pci bridge generated transactions when the controller issues a read or a write operati on to an external memory or i/o peripheral, the memory controller looks at the address and compares it with the address range of the six regions. if the address matches, the memory controller supplies the address bus with the various control signals as well as the chip select for that region. in this case, the data transfer occurs between the rc32334 and the external memory or i/o peripherals. the rc32334 generates all control signals, per configuration of the vari ous registers, and will also end the transaction at the specified time. during r ead transactions, the rc32334 samples the mem_data[31:0] bus to latch the data into the dma or pci fifo. during write transactions, the rc32334 drives the data on the mem_data[31:0] bus from the dma or pci fifo. fr om either the dma controller or pci bridge, the memory controller will support both r ead and write single and burst transactions 1 . 1. burst transactions from dma are linearly addressed. start address[3:0] burst sequence 0 (0,4,8,c) 4 (4,0,c,8) 8 (8,c,0,4) c (c,8,4,0) memory controller using 8- or 16-bit boot proms 79rc32334/332 user reference manual 10 - 3 june 4, 2002 notes chip selects the memory controller contains 6 separate memo ry spaces, each having it s own mem_cs_n output pin. the first two highly configurable mem_ cs spaces occupy from 64k to 4gb of address space of which 64mb is externally addressable (due to the 26 1 address lines). the second through the fourth fixed memory chip select spaces occupy 32 mb of address space, all of which is externally addressable (due to the 26 address lines). 2 if the dma or pci bridge is not used to acce ss a particular memory bank, an optional external fct373 transparent latch can be used to extend t he number of address bits for cpu accesses. the address spaces that mem_cs_n[0] and me m_cs_n1[] decode are programmable. the memory controller uses the programmed information in the ba se address registers, al ong with the size (64k to 8mb) of the given area as programmed in the page ma sk registers, to setup the mem_cs spaces for banks 0 and 1. this information is used to compare with the addres s asserted by the controller-biu, dma controller, or pci bridge, to determine if that particular mem_cs _n area is being accessed for the current read or write operation. each area supports single reads, burst reads, single writes, and burst writes. the port size of the data path (8, 16, 32-bit, or interleaved) of each ar ea is also programmable th rough the appropriate control register. transceiver control interface the memory controller provides transceiver output enables and write enabl es that are suitable for direct bus connection, or fct245 tr ansceivers. the selection of the type of memory is software programmable. fct245s can be used for other banks, if the boot prom is also behind the fc t245s. the following are recommendations for system use: ? transceivers and buffering in small to large systems in small systems , no glue logic is required. if the number of memory devices is eight or less, then address buffering is not required. if the number of memory and io banks is eight or less, then data transceivers are also not required. in medium systems using more than eight memory chips, the address bus from rc32334 should be buffered usi ng fct244s. in general, the data bus does not need transceivers as often as the address bus needs buffering. typically, for 8-bit chip devices, in each bank, there are four chips per address signal , but only one chip per data signal, yielding a 4- to-1 ratio. typically, only the largest systems have more than eight banks of devices, at which point data transceivers are recommended. ? using slow-to-turn-off eprom s in small to large systems in small systems using slow-to-turn-off-data eprom or io, the eprom or io data bus, for each bank, can be transceivered using fct 245s connected to mem_cs_n[5:0] and mem_245_dt_r_n(dir). alternatively, the rc32334 bus turnaround (bta) feature can be used to delay transactions after reads. in medium systems using slow-to-turn-off-data eprom or io, the eprom and io data bus can be transceivered, us ing a single bank of fct245s connected to mem_245_oe_n(oe) and mem_245_dt_r_n(dir). in large systems using multiple banks of eprom or io, the eprom or io data bus for each bank can be transceivered using fct245s connected to mem_cs_n[] and mem_245_dt_r_n(dir). using 8- or 16-bit boot proms when using 8- or 16-bit boot proms, 3 the proms must use mem_addr[3:2] and mem_we_n[3:0] to provide the lsb system memory address bits. in the 16-bit case, the dynamic byte enables are provided via the rc32334?s mem_we_n[3] and mem_we_n[0] signals. in the 8-bit case, the byte enable is provided by the rc32334?s mem_we_n[0] signal. 1. 23 address lines for the rc32332. 2. the rc32334 has 26 address lines addressing a maximum 2 26 (64) mb. the rc32332 has 23 address lines addressing a maximum 2 23 (8) mb. 3. note that 8-bit and 16-bit proms cannot use the rc32334 dma to transfer data. memory controller wait-state generator (wsg) 79rc32334/332 user reference manual 10 - 4 june 4, 2002 notes note that the rc32334 coprocessor port width cont rol register should be initialized by the boot prom software for the non-boot regions of memo ry such as 32-bit wide dram regions. wait-state generator (wsg) the wsg controls the speed of memory accesses to and from the internal bus interface unit (biu) controller, which includes the start time of a memory transaction until the first data are sent or received and the time between consecutive data on burst transac tions. the signal called mem_wait_n can be used to override the wsg?s programmed se ttings. when mem_wait_n is asserted, however, the actual action performed by the wsg depends upon when it is assert ed, relative to the transaction. the mem_wait_n signal is also useful for accessing memories such as dual-port-type memory and other off-card memory where the acknowledge (ack) signal mu st be connected to the mem_wait_n. address decoding memory spaces are selectable up to 64mb 1 per channel. the first two memory-i/o channels have soft- ware selectability as to where and how much memory space the channel uses 2 . the remaining channels have fixed-size memory spaces. within rc32334, t he internal design is such that the address decoding and its registers is actually done with the rc32334- to-ip bridge hardware. fo r readability reasons, the memory decode functionality is described in this chapter. user notes: 1. mem/io 0 space is used for reset boot roms typically starting at 0x1fc0_0000, and thus is limited to a linear 4m from the boot reset addr ess. if the rom is wrapped around after 4m, then the lower portion of the address range can also be accessed. 2. mem/io spaces larger than 64mb require an exte rnal address latch, and in that case, can only be accessed via the controller (and not dma or pci). 3. mem/io spaces within the sa me controller physical region must have the same port width and bta settings; for example, mem/io 2&3 and mem/io 4&5. 4. mem/io 1 space in this example uses an address able region that may not be accessible in future rc32334 derivatives. if such a derivative is on t he user?s road map, mem/io 1 should be assigned to another area of memory, i.e., from 0x1f00_0000 . port width pin signals mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] dma (32-bit) mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] 32-bit mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] 16-bit byte high write enable mem_addr[1] not used (driven low) byte low write enable 8-bit not used (driven high) mem_addr[1] mem_addr[0] byte write enable table 10.1 8- and 16-bit lsb a ddresses and write-en able connections 1. 8mb for the rc32332. 2. note that mem/io spaces within the same region must have the same port width and bta settings, for example mem/io 2&3, and mem/io 4&5. also, future channels may split the 0x1600_0000 to 0x 17ff_ffff memory space into several more sections. users can easily externally decode a chip select to expand the number of selectable devices, and through the use of an external decoder?such as a f138/f139 logic device?using the msb system memory address bits, extra chip selects can be provided to like size/speed devices. memory controller memory type and port-width size support 79rc32334/332 user reference manual 10 - 5 june 4, 2002 notes memory type and port-width size support encoding the memory-type field with the values list ed in table 10.3 determines the bus interface timing to be supported by the memory controller. the port size field values listed in table 10.4 determine the width of the memory or i/o port. one of the four memory types described below must be selected, as shown in table 10.3: ? flash/sram this is the default memory type. the r ead data is primarily controlled by the mem_oe_n signal which enables the read data ba ck onto the mem_data[] bus on a continuous basis. write data is primarily controlled by the chip select, mem_cs_n[x], which is used as the write strobe. ? ioi (intel-type i/o) this i/o type uses separate read and write strobes to signal valid data. custom- arily, this i/o type uses single word accesses. ? iom (motorola-type i/o) this i/o type uses a common data strobe, mem_cs_n[] and uses mem_oe_n or mem_we_n[] as write/read_n or read/wri te_n status lines. customarily, this i/o type uses single word accesses. ? dpm (dual-port memory) the read data is primarily contro lled by the mem_oe_n signal which enables the read data back onto the mem_data[] bus on a continuous basis. write data is primarily controlled by the write enables, mem_we_n[3:0], wh ich are used as the writ e strobes. the external wait-state pin, mem_wait_n when asserted, resets the internal wait-state generator back to its ini- tial value, such that when mem_wait_n is de-asserted , the internal wait-state count start over giving a full length transaction from that point in time. note: the write protect field and the port width si ze field of the memory control register for each bank must be setup before any writes to that bank occur. the write protect field defaults to protected, thus it must be unset to first issue a write. during write protection, the chip select remains de-asserted. rc32334 physical address range max. size region rc32300 cpu core region description 0000_0000 0fff_ffff 256mb a ,b,c,d dram 0,1,2,3 (16mb typical) 1000_0000 11ff_ffff 32mb e mem/io 2 (8mb typical) 1200_0000 13ff_ffff 32mb e mem/io 3 (8mb typical) 1400_0000 15ff_ffff 32mb f mem/io 4 (8mb typical) 1600_0000 17ff_ffff 32mb f mem/io 5 (8mb typical) 1800_0000 1bff_ffff 64mb g rc32334 internal registers 1c00_0000 1fff_ffff 64mb h mem/io 0 (4mb typical) 2000_0000 23ff_ffff 64mb i mem/io 1 (8mb typical) 4000_0000 5fff_ffff 512mb j pci memory space 1 (256mb typical) 6000_0000 7fff_ffff 512mb k pci memory space 2 (256mb typical) 8000_0000 ff1f_ffff o reser ved, undecoded. if accesses are made to this region, the rc32334 will return a bus error. ff20_0000 ff2f_0000 1mb o reserved for rc32334 on-chip ejtag interface. the rc32334 does not decode this address and a bus error will be returned if accessed. table 10.2 rc32334 typical memory map memory controller port-width size 79rc32334/332 user reference manual 10 - 6 june 4, 2002 notes when choosing a dual-port memory, the semaphore or interrupt version can be useful for data buffer streams. if the busy version is used, the external mem_wait_n signal (see table 10.11 for signal definitions) can be used for busy-signal support by using the dual-port memory type. in the dual-port memory type, if the busy pin is asserted, then the memory c ontroller?s wait-state counter resets to 0. during the first clock, the busy pin is always ignored; thus, for seamle ss integration, a dual-port memory part?where busy_n becomes valid bet ween 1 and 2 clocks?must be selected. if a slower part were to be selected, application specific wait-state programming and external delay logic would be necessary, to mask out the indeterminate busy flag for the first few clocks. dual-port memory type differs from flash/sram memory type in that: ? mem_wait_n is handled differently ? writes use mem_we_n[3:0] controlled writes instead of mem_cs_n[x] controlled writes dual-port memory type reads drive the address, chip select, and output at the same time. burst read transfers alter the address on subsequent data. thus, if the external dual-port memory is fast enough, true zero wait-state burst reads will be able to occur. d ual-port memory type writes also drive the address, data and chip select, but delay the assertion of mem_ we_n[]. after the programmed number of wait-states, mem_we_n[] is de-asserted and the address, data, and chip select are held for 1 clock. as such, burst writes require a minimum of 3 clocks for each data burst. port-width size non-interleaving, non-expandable 32-/16- /8-bit support for bank 0 or bank 1 can be 16- or 8-bit, but it might not be physically contiguous with bank 0, unless it is at least 64kx8. note that in the former case, the tlb and the rc32334 integrated processor can be used to make physical memory virtually contiguous for linearly addressed so ftware applications. in the sram mode, 16-bit ports require that t he write enable pins mem_we_n[3] and mem_we_n[0] be connected to the most and least significant bytes, respec tively. also, in the 16-bit mode, sram mode multi- byte writes will delay the subsequent assertion of mem_ cs_n[] by one clock from the normal 32-bit or 8-bit cases, to allow the mem_we_n[3:0] signals to setup during burst writes. as in the case of dual-port memory, 8-bit ports may require that the write enable pin of the memory device be connected to the rc32334 pin, mem_we_n[0]. w hen in this mode, the memory controller asserts mem_we_n[0] on writes. in 8-bit mode, mem_ we_n[2:1] serve as address bits 1 and 0. value action 11 dual port note: if the dual-port mode is selected, all other memory types will ignore the mem_wait_n pin. this prevents inadvertent lockups from matc hing addresses during non-dual-port transactions. 10 m-type i/o = motorola type i/o 01 i-type i/o = intel type i/o 00 flash/sram (default) table 10.3 memory type field values and actions value action 11 reserved 10 32-bit port width size writes (default) 01 16-bit port width size writes 00 8-bit port width size writes table 10.4 port width size field values and actions memory controller programmable wait-state generator 79rc32334/332 user reference manual 10 - 7 june 4, 2002 notes depending on the port-width size selected, the by te enable handling on writes will differ: 16-bit port width memories split a single word write into two mini -burst 16-bit data segments. in this case, the 16-bit port width mode will ensure that mem_we_n[3] and mem_we_n[0] are de-asserted on the first data segment to provide data hold time. 8-bit port width memories always assert mem_we_n[0] on each data word. i/o width support because the rc32334 does not directly support byte enables on reads (it coul d be done externally), 32- bit i/o word-aligned devices are strongly recomm ended. 8- and 16-bit devices should be word-aligned, such that the msb bits [31:8] and [31:16] are not used independent from endianness. burst or mini-burst accesses are not recommended, although they will comp lete with an implementation specific method that does not necessarily meet any particular device?s bur st protocol or command recovery period (bta period). programmable wait-state generator a software programmable register (see table 10.11 on page 10-11) allows selection of the number of wait-states from between 0 and 31 for reads versus wr ites. data within bursts have identical settings to reads versus writes. according to the nature of eac h memory type?s protocol, a minimum number of wait- states for asynchronous transfer types is required, as shown in table 10.5. external wait-state behavior on sram, ioi (i/o intel type), and iom (i/o motorola type) accesses , the internal wait-state gener- ator ignores the mem_wait_n signal until its last inter nal wait-state. at that time, users can add an arbitrary number of additional external wait-states. the last internal wait-state corres ponds to the clock before cpu_ack_n would have asserted, thus mem_wait_n must be asserted any time before the final clock cycle of the transaction occurs. if the channel is using 0 wait-states internally, the first data cannot be stopped unless mem_wait_n is left asserted before the memory transaction begins. on dual-port accesses , if mem_wait_n is always ignored during the first clock of a dpm transaction, it allows the dpm time to generate a valid busy_n signal . on subsequent clocks, mem_wait_n is internally synchronized for metastability by delaying it one clock, and the internal wait-state counter is then reset to 0 to restart the dpm transaction. if any channel uses the dpm mode, then mem_wait_n is automatically ignored during sram, ioi, and iom accesses. note that only 1 dpm may use mem_wait_n, unless external provisions are made to ensure that a dpm address match does not occur on other banks. typically, the rc32334 bta register is also set up before switching to any bank besides the boot prom. the rc32334 btas are set to their maximum of 3 clocks and most memories can be set to a minimum of 1 clock (a trecovery clock is al ways inserted, in addition to any bta clocks). memory type transfer type minimum wait-state requirements sram read 0 sram write (32/8-bits) 2 sram write (16-bits) 2 + (1 clk automatically inserted between data) ioi read 1 + (2 clks automatically inserted between data) ioi write 2 + (1 clk automatically inserted between data) iom read 1 + (2 clks automatically inserted between data) iom write 2 + (1 clk automatically inserted between data) dpm read 0 dpm write 2 table 10.5 minimum wait-state settings memory controller bus error recovery 79rc32334/332 user reference manual 10 - 8 june 4, 2002 notes bus error recovery the memory controller gracefully aborts on a bus error and bus time-ou t. both bus errors and bus time- outs latch the present physical address into the buserror address register. this implies that the bus error controller can only assert cpu_buserr_n up unt il the first cpu_ack _n would be returned. on a bus error, the memory controller ignores the mem_wait_n signal and returns cpu_ack_n to the cpu core, at the normal times indicated by the ws g until the transaction is complete. at the first cpu_ack_n, cpu_buserr_n is then asserted. a bus time-o ut may occur at any time during the bus transac- tion, even after the first ack_n has been returned. if t he time-out occurs, the bus time-out interrupt is asserted, then the mem_wait_n is ignored and the transaction continues. signal descriptions table 10.6 describes the signals used in rc32334?s memo ry controller transactions. the list of memory controller registers is provided in t able 10.7, with register fields and thei r descriptions listed in table 10.11. name type description memory/i/o controller mem_addr[25:2] 1 i/o not appli- cable memory address bus these signals provide the memory or dram address, during a memory or dram bus transaction. during each word data, the address increments either in linear or sub-block ordering, depending on the transaction type. the table below indicates how the memory write enable signals are used to address discrete memory port width types. mem_addr[22] alternate function: reset_boot_mode[1]. mem_addr[21] alternate function: reset_boot_mode[0]. mem_addr[20] alternate function: reset_pci_host_mode. mem_addr[19] alternate function: modebit [9]. mem_addr[18] alternate function: modebit [8]. mem_addr[17] alternate function: modebit [7]. mem_addr[15] alternate function: sdram_addr[15]. mem_addr[14] alternate function: sdram_addr[14]. mem_addr[13] alternate function: sdram_addr[13]. mem_addr[11] alternate function: sdram_addr[11]. mem_addr[10] alternate function: sdram_addr[10]. mem_addr[9] alternate function: sdram_addr[9]. mem_addr[8] alternate function: sdram_addr[8]. mem_addr[7] alternate function: sdram_addr[7]. mem_addr[6] alternate function: sdram_addr[6]. mem_addr[5] alternate function: sdram_addr[5]. mem_addr[4] alternate function: sdram_addr[4]. mem_addr[3] alternate function: sdram_addr[3]. mem_addr[2] alternate function: sdram_addr[2]. table 10.6 memory controller pin descriptions (part 1 of 2) port width pin signals mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] dma (32-bit) mem_we_n[3] mem _we_n[2] mem_we_n[1] mem_we_n[0] 32-bit mem_we_n[3] mem_we_n[ 2] mem_we_n[1] mem_we_n[0] 16-bit byte high write enable mem_addr[1] not used (driven low) byte low write enable 8-bit not used (driven high) mem_addr[1] mem_addr[0] byte write enable mem_addr subsets mem_addr[22:20] i/o reset_boot_mode[1:0] reset_pci_host_mode mem_addr[19:17] i/o reset mode bits mem_addr[15:2] i/o sdram_addr[15:2] memory controller register definitions 79rc32334/332 user reference manual 10 - 9 june 4, 2002 notes register definitions table 10.7 provides the physical har dware address locations of the memo ry controller registers, which include memory base and mask registers for banks 1:0 and the control registers for banks 5:0. fields of the bank and mask registers are s hown in figure 10.3 and figure 10.4. details on these fields are provided in table 10.9 and table 10.10. the memory control register infor- mation is provided in figure 10.5 and table 10.11. mem_cs_n[5:0] o not appli- cable memory chip select negated recommend an external pull-up. signals that a memory bank is actively selected. mem_oe_n o not appli- cable memory output enable negated recommend an external pull-up. signals that a memory bank can output its data lines onto the cpu_ad bus. mem_we_n[3:0] o not appli- cable memory write enable negated bus signals which bytes are to be written during a memory transaction. bits act as byte enable and mem_addr[1:0] signals for 8-bit or 16-bit wide addressing. mem_wait_n i memory wait negated requires an external pull-up. sram/ioi/iom modes: allows external wait-states to be injected during last cycle before data is sampled. dpm (dual-port) mode: allows dual-port busy signal to restart memory transaction. alternate function: sdram_wait_n. mem_245_oe_n o not appli- cable memory fct245 output enable negated controls output enable to optional fct245 transceiver bank by asserting during both reads and writes to a memory or i/o bank. mem_245_dt_r_n o cpu_dt_r_ n memory fct245 direction xmit/rcv negated recommend an external pull-up. alternate function: cpu_dt_r_n. 1. mem_addr[22:2] for the rc32332. physical address register descriptions 1800_0080 memory base address register for bank 0 1800_0084 memory base mask register for bank 0 1800_0200 memory control register for bank 0 1800_0088 memory base address register for bank 1 1800_008c memory base mask register for bank 1 1800_0204 memory control register for bank 1 1800_0208 memory control register for bank 2 1800_020c memory control register for bank 3 1800_0210 memory control register for bank 4 1800_0214 memory control register for bank 5 table 10.7 list of memory control registers name type description table 10.6 memory controller pin descriptions (part 2 of 2) memory controller register definitions 79rc32334/332 user reference manual 10 - 10 june 4, 2002 notes memory msb base address register for banks 1:0 the base address registers are used to determine the st arting location of a particular chip select. there are six pairs of msb and lsb regist ers, a pair for each memory chip select (memcs). each pair of memory base address registers is concatenated onto an internal 32-bit register and refers to the most significant 16 address bits and the l east significant 16 addres s bits. unused bits are always read as ?0?. typically, if two banks of prom/sram are used, the larger bank is placed in the bank 0 address space and the smaller bank is placed in the bank 1 address space. this arrangement a llows a contiguous address space for the two combined banks. the default value for bank 0 base address regi ster [1800_0080] is 0x1fco_0000 when the rc32334 is programmed in the standard boot m ode. the default is 0xffco_0000 w hen programmed with the reset vector pci_boot mode or the non_boot mode. the default value for bank1 base address register [1800- 0088] is 0x 2000_0000. figure 10.3 memory base address register for banks 1:0 memory msb bank mask registers for banks 1:0 the bank mask registers are used to determine the addr ess bits in the base address that are to be used for comparing whether a chip select is to be activa ted. unused bits are always read as ?0?. the internal grouping of the six chip selects are as listed in table 10.9. figure 10.4 memory bank mask register for banks 1:0 internal group base address mem_cs_n[0] default is 1fco_0000 except if in pci- boot or non-boot mode where the default is ffco_0000 mem_cs_n[1] default is 2000_0000 mem_cs_n[2] hard-coded to 1000_0000 mem_cs_n[3] hard-coded to 1200_0000 mem_cs_n[4] hard-coded to 1400_0000 mem_cs_n[5] hard-coded to 1600_0000 table 10.8 internal chip select base addresses 0000 msb base address 31 16 15 0 0000 msb bank mask 31 16 15 0 memory controller register definitions 79rc32334/332 user reference manual 10 - 11 june 4, 2002 notes memory control register for banks 5:0 systems with multiple memory/io banks can have all banks behind a fct245 transceiver bank or they can have all banks on the cpu local bus. systems may be ?mixed? such that the boot memory bank 0 is behind the fct245 bank and other memory/io banks can reside either behind the fct245 transceiver bank or on the local cpu bus. note: for each bank, the write protect field (bit 12) and the port width size field (bits 11:10) of the memory control register must be setup befor e any writes to that bank occur. the write protect field defaults to protected and must be uns et prior to the first write issued. during write protection, the chip select remains de-asserted. figure 10.5 memory control register channel 5:0 internal group chip-select mask bit activation mem_cs_n[0] default is ffff_0000 mem_cs_n[1] mem_cs_n[2] effective value is hard-coded as fe00_0000 mem_cs_n[3] mem_cs_n[4] mem_cs_n[5] table 10.9 internal chip select grouping value action 1 bit is used in address comparison 0 bit is masked out table 10.10 memory mask field definitions and values bit name description 15:14 memory type table 10.11 memory controller register field descriptions, channels 5:0 (part 1 of 2) port width size writes write protect 245 mode read write wait-states wait-states enable memory type 15 14 13 12 11 10 9 5 4 0 value description 11 dual port note: if the dual-port mode is selected, all other memory types will ignore the mem_wait_n pin. this prevents inadvertent lockups from matching addresses during non-dual-port transactions. 10 m-type i/o (motorola type) 01 i-type i/o (intel type) 00 flash/sram (default) memory controller timing diagrams 79rc32334/332 user reference manual 10 - 12 june 4, 2002 notes timing diagrams the timing of various memory and peripheral read and write operations is shown in the diagrams that follow. these diagrams include timi ng representations for both single and burst transfers. an operational overview description is pr ovided before each diagram. figure 10.6 shows an sram-type single word memory read with 1 internally generated wait-state. note that both the chip select, mem_cs_n[0], and the out put enable, mem_oe_n, signals primarily determine the read access time for the data from the sram. note that additional internally generated wait-states will repeat state 4. (type=00, 245=1, wp=0, pw=10, wws=2, rws=1). 13 mem_245_oe_n enable field the mem_245_oe_n enable field controls whether the mem_245_oe_n transceiver enable can assert or not. if it is disabled, then the memory bank for this channel can reside on the local cpu bus rather than behind a transceiver bank. 12 write protect field 11:10 port width size writes the function of this field is discussed in the section titled ?port-width size? on page 10-6. 9:5 write wait-states this software programmable register allows selection of the number of wait-states for writes from between 0 and 31. each memory type?s protocol requires a minimum number of wait- states. as shown, the default value is 31. 4:0 read wait-state this software programmable register allows selection of the number of wait-states for reads from between 0 and 31. each memory type?s protocol requires a minimum number of wait- states. as shown, the default value is 31. bit name description table 10.11 memory controller register field descriptions, channels 5:0 (part 2 of 2) value description 1 mem_245_oe_n enabled for this channel bank (default) 0 mem_245_oe_n disabled for this channel bank such that it can reside on the cpu local bus value description 1 mem_cs_n not asserted on writes ( default ) 0 mem_cs_n asserts during writes (typical setting) value size 11 reserved 10 32-bit port width size writes (default) 01 16-bit port width size writes 00 8-bit port width size writes value wait-states 0 - 31 refer to table 10.4 for transfer type requirements. the default value is 31 . value wait-states 0 - 31 refer to table 10.4 for transfer type requirements. the default value is 31 . memory controller timing diagrams 79rc32334/332 user reference manual 10 - 13 june 4, 2002 notes figure 10.6 single word sram read transaction 1 2 3 4 5 6 3c00000 1fc00004 0 1111 1111 1111 tdo7, tdo7, tdo8, tdo8, tdo7a, tdo7a, tdo7, tdo7, tdo6, tdo6, tdo5, tdo5, thld2 tsu2 thld8 tsu6 cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n mem_wait_n tdoh3 tdoh3 tdoh3 tdoh3 tdoh3 tdoh3 tdoh3 tdoh3 tdoh3 tdoh3 tdoh3 tdoh3 memory controller timing diagrams 79rc32334/332 user reference manual 10 - 14 june 4, 2002 notes figure 10.7 shows an sram-type single word memory read with 1 internally generated wait-state and then 1 externally generated wait-state as indicated by mem_wait_n asserting. note that if the memory controller were programmed such that 2 or more in ternally generated wait-states occurred, mem_wait_n is ignored until the final wait-state occurs the clo ck before where debug_cpu_ack_n would assert. (type=00, 245=1, wp=0, pw=10, wws=2, rws=1). figure 10.7 single word sram read transaction with wait-state 1 2 3 4 5 6 7 3c00000 1fc00004 0 1111 1111 1111 tp tp tp tp tp tp tp tp tp tp tp tp tsu6 thld8 thld8 tsu6 thld8 tsu6 cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n mem_wait_n memory controller timing diagrams 79rc32334/332 user reference manual 10 - 15 june 4, 2002 notes figure 10.8 shows an sram-type single word memory write with 2 internally generated wait-states. note that the write enables, mem_we_n[3:0], are used as status lines, while the chip select, mem_cs_n[0], is used as the primary write strobe. also note that additional internally gener ated wait-states will repeat state 4, so that mem_cs_n[0] is continuously assert ed during internal wait-states. (type=00, 245=1, wp=0, pw=10, wws=2, rws=1). figure 10.8 single word sram write transaction 1 2 3 4 5 6 3c00000 1fc00004 abcd0000 1111 0000 1111 tp tp tp tp tp tp tp tp tp tp tdo4, tdo4, tp tp thld tsu cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n mem_wait_n tdoh1 tdoh1 memory controller timing diagrams 79rc32334/332 user reference manual 10 - 16 june 4, 2002 notes figure 10.9 shows an sram-type single word memory write with 3 internally generated wait-states and then 1 externally generated wait-state as indicated by mem_wait_n asserting. this case provides 1 more wait-state beyond the required minimum of 2 wait-sta tes. note that if the memory controller were programmed such that 3 or more internally generated wait-states occurred, mem_wait_n is ignored until the final wait-state occurs wher e debug_cpu_ack_n would assert. (type=00, 245=1, wp=0, pw=10, wws=3, rws=2). figure 10.9 single word sram write transaction with wait-state 1 2 3 4 5 6 7 8 3c00000 1fc00004 abcd0000 1111 0000 1111 tp tp tp tp tp tp tp tp tp tp tp tp tp tp tsu thld thld tsu cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n mem_wait_n memory controller timing diagrams 79rc32334/332 user reference manual 10 - 17 june 4, 2002 notes figure 10.10 shows an sram-type four word memory burst read with 1 internally generated wait-state on each data. note that both the chip select, me m_cs_n[0], and the output enable, mem_oe_n, primarily determine the read access time for the data from the sram. (type=00, 245=1, wp=0, pw=10, wws=2, rws=1). figure 10.10 quad word burst read sram transaction 1 2 3 4 5 6 7 8 9 10 11 12 3c00000 3c00004 3c00008 3c0000c 1fc00004 0 4 8 c 1111 1111 1111 tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp thld tsu thld tsu thld tsu thld tsu thld tsu thld tsu thld tsu thld tsu cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n mem_wait_n memory controller timing diagrams 79rc32334/332 user reference manual 10 - 18 june 4, 2002 notes figure 10.11 shows an sram-type four word memory burst write with two internally generated wait- states. note that the writes enables, mem_we_n[3:0], are used as status lines, while the chip select, mem_cs_n[0], is used as the primary write strobe. note that if the access is to a 16-bit port-width, then an extra cycle (not shown) is aut omatically inserted between each datum, such that the write enables, mem_we_n[] can change dynamically for each halfword with both 1 clock setup and hold relative to the chip select asserting and de-asserting. (ty pe=00, 245=1, wp=0, pw=10, wws=2, rws=1). figure 10.11 sram 4 word burst write figure 10.12 shows an sram-type tri-by te mini-burst 16-bit port width write with 2 internally generated wait-states. note that the second assertion of mem_ cs[] is delayed one clock to allow mem_we_n[] time to setup. (type=00, 245=1, wp=0, pw=10, wws=2. rws=1). figure 10.12 tri-byte 16-bit sram write transaction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 3c00000 3c00004 3c00008 3c0000c 1fc00004 abcd0000 abcd0004 abcd0008 abcd000c 1111 0000 1111 tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp thld tsu thld tsu thld tsu thld tsu cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n mem_wait_n 1 2 3 4 5 6 7 8 9 10 3c00000 3c00002 1fc00004 1234 0056 1111 00 11 10 tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp thld tsu thld tsu cpu_masterclk mem_addr[25:1]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3,0] mem_245_dt_r_n mem_245_oe_n mem_wait_n memory controller timing diagrams 79rc32334/332 user reference manual 10 - 19 june 4, 2002 notes figure 10.13 shows an ioi-type single word memory read with 1 internally generated wait-state. note that the read output enable, mem_oe_n provides the read data strobe. note that additional internally generated wait-states will repeat state 4, so that mem_oe_n is continu- ously asserted during internal wait states. (type=01, 245=1, wp=0, pw=10, wws=2, rws=1). figure 10.13 ioi 1 word single read 1 2 3 4 5 6 3c00000 1fc00004 abcd0000 1111 1111 1111 tp tp tp tp tp tp tp tp tp tp tp tp thld tsu thld tsu cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n mem_wait_n memory controller timing diagrams 79rc32334/332 user reference manual 10 - 20 june 4, 2002 notes figure 10.14 shows an ioi-type single word memory r ead with 2 internally generated wait-states. this case provides 1 more wait-state beyond the requir ed minimum of 1 wait-state. (type=01, 245=1, wp=0, pw=10, wws=3. rws=2). figure 10.14 ioi 1 word single read with wait-state 1 2 3 4 5 6 7 3c00000 1fc00004 abcd0000 1111 1111 1111 tp tp tp tp tp tp tp tp tp tp tp tp thld tsu thld tsu cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n mem_wait_n memory controller timing diagrams 79rc32334/332 user reference manual 10 - 21 june 4, 2002 notes figure 10.15 shows an ioi-type single word memory wr ite with 2 internally generated wait-states. note that the write enable bus, mem_we_n[3:0], provides the write data strobe. note that additional internally generated wait-states will repeat state 4, so that mem_oe_n is continu- ously asserted during internal wait states.( type=01, 245=1, wp=0, pw=10, wws=2, rws=1). figure 10.15 ioi 1 word single write 1 2 3 4 5 6 3c00000 1fc00004 abcd0000 1111 0000 1111 tp tp tp tp tp tp tp tp tp tp tp tp tp tp thld tsu cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n mem_wait_n memory controller timing diagrams 79rc32334/332 user reference manual 10 - 22 june 4, 2002 notes figure 10.16 shows an ioi-type single word memory wr ite with 3 internally generated wait-states. this case provides 1 more wait-state beyond the requir ed minimum of 2 wait-states. (type=01, 245=1, wp=0, pw=10, wws=3. rws=2). figure 10.16 ioi 1 word single write with wait-state figure 10.17 shows an ioi-type four word memory bur st read with 1 internally generated wait-state for each datum. note that the read output enable, mem_oe_n, provides the read data strobe. the burst iom- type access is not conventionally used by i/o per ipherals. (type=01, 245=1, wp=0, pw=10, wws=2, rws=1). figure 10.17 ioi 4 word burst read 1 2 3 4 5 6 7 3c00000 1fc00004 abcd0000 1111 0000 1111 tp tp tp tp tp tp tp tp tp tp tp tp tp tp thld tsu cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n mem_wait_n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 3c00000 3c00004 3c00008 3c0000c 0 4 8 c 1111 1111 1111 1111 1111 1111 1111 1111 1111 tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp thld tsu thld tsu thld tsu thld tsu thld tsu thld tsu thld tsu thld tsu cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n mem_wait_n memory controller timing diagrams 79rc32334/332 user reference manual 10 - 23 june 4, 2002 notes figure 10.18 shows an ioi-type four word memory burst write with 2 internally generated wait-states for each data. note that the write enable bus, mem_we_n[ 3:0], provides the write da ta strobe. the burst iom- type access is not conventionally used by i/o per ipherals. (type=01, 245=1, wp=0, pw=10, wws=2, rws=1). figure 10.18 ioi 4 word burst write figure 10.19 shows an iom-type single word memory read with 1 internally generated wait-state. note that the chip select, mem_cs_n[0], provides the data strobe while the output enable?or the write enables? indicate the read/write status. also note that additional internally generated wait-states will repeat state 4, so that mem_cs_n[0] is continuously asserted during internal wait-states. (type=10, 245=1, wp=0, pw=10, wws=2, rws=1). figure 10.19 iom 1 word single read 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 3c00000 3c00004 3c00008 3c0000c 1fc00004 abcd0000 abcd0004 abcd0008 abcd000c 1111 0000 1111 0000 1111 0000 1111 0000 1111 tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp thld tsu thld tsu thld tsu thld tsu cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n mem_wait_n 1 2 3 4 5 6 3c00000 1fc00004 abcd0000 1111 1111 1111 tp tp tp tp tp tp tp tp tp tp tp tp tsu thld thld tsu cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n mem_wait_n memory controller timing diagrams 79rc32334/332 user reference manual 10 - 24 june 4, 2002 notes figure 10.20 shows an iom-type single word memory r ead with 2 internally generated wait-states. this case provides 1 more wait-state beyond the requir ed minimum of 1 wait-state. (type=10, 245=1, wp=0, pw=10, wws=3. rws=2). figure 10.20 iom 1 word single read with wait-state 1 2 3 4 5 6 7 3c00000 1fc00004 abcd0000 1111 1111 1111 tp tp tp tp tp tp tp tp tp tp tp tp tsu thld thld tsu cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n mem_wait_n memory controller timing diagrams 79rc32334/332 user reference manual 10 - 25 june 4, 2002 notes figure 10.21 shows an iom-type single word memory wr ite with 2 internally generated wait-states. note that the chip select, mem_cs_n[0], provides the dat a strobe while the output enable, or the write enables, indicate the read/write status. also note that additional internally generated wait-states will repeat state 4, so that mem_cs_n[0] is continuously asserted during internal wait-states. (type=10, 245=1, wp=0, pw=10, wws=2, rws=1). figure 10.21 iom 1 word single write 1 2 3 4 5 6 3c00000 1fc00004 abcd0000 1111 0000 1111 tp tp tp tp tp tp tp tp tp tp tp tp tp tp thld tsu cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n mem_wait_n memory controller timing diagrams 79rc32334/332 user reference manual 10 - 26 june 4, 2002 notes figure 10.22 shows an iom-type single word memory wr ite with 3 internally generated wait-states. this case provides 1 more wait-state beyond the required minimum of 2 wait-states. (type=10, 245=1, wp=0, pw=10, wws=3. rws=2). figure 10.22 iom 1 word single write with wait-state figure 10.23 shows an iom-type four word memory r ead with 1 internally generated wait-state for each data. note that the chip select, mem_cs_n[0], provi des the data strobe while the output enable, or the write enables, indicate the read/write status. the burst iom- type access is not conventionally used by i/o periph- erals. (type=10, 245=1, wp=0, pw=10, wws=2, rws=1). figure 10.23 iom 4 word burst read 1 2 3 4 5 6 7 3c00000 1fc00004 abcd0000 1111 0000 1111 tp tp tp tp tp tp tp tp tp tp tp tp tp tp thld tsu cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n mem_wait_n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 3c00000 3c00004 3c00008 3c0000c 0 4 8 c 1111 1111 1111 1111 1111 1111 1111 1111 1111 tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp thld tsu thld tsu thld tsu thld tsu thld tsu thld tsu thld tsu thld tsu cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n memory controller timing diagrams 79rc32334/332 user reference manual 10 - 27 june 4, 2002 notes figure 10.24 shows an iom-type four word memory writ e with 2 internally generated wait-states for each datum. note that the chip select, mem_cs_n[0], prov ides the data strobe while the output enable, or the write enables, indicate the read/writ e status. the burst iom-type access is not conventionally used by i/o peripherals. (type=10, 245=1, wp =0, pw=10, wws=2, rws=1). figure 10.24 iom 4 word burst write figure 10.25 shows a dpm-type single word memory read with 1 internally generated wait-state. note that both the chip select, mem_cs_n[0] and the output enable, mem_oe_n, prim arily determine the read access time for the data from the sram. note that additional internally generated wait-state s will repeat state 4. (type=11, 245=1, wp=0, pw=10, wws=2, rws=1). figure 10.25 dual-port 1 word single read 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 3c00000 3c00004 3c00008 3c0000c 1fc00004 abcd0000 abcd0004 abcd0008 abcd000c 1111 0000 1111 tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp thld tsu thld tsu thld tsu thld tsu cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n mem_wait_n 1 2 3 4 5 6 7 3c00000 1fc00004 abcd0000 1111 1111 1111 tp tp tp tp tp tp tp tp tp tp tp tp thld tsu thld tsu cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n mem_wait_n memory controller timing diagrams 79rc32334/332 user reference manual 10 - 28 june 4, 2002 notes figure 10.26 shows a dpm-type singl e word memory read with 1 in ternally generated wait-state, and then 1 externally generated wait-state is indicated by mem_wait_n asserting. note that the internal wait- state counter starts over each time mem_wait_n is asserted, such that when mem_wait_n de-asserts the internal wait-state counter goes through a complete count before the transaction ends. (type=11, 245=1, wp=0, pw=10, wws=2, rws=1). figure 10.26 dual-port 1 word single read with wait-state 1 2 3 4 5 6 7 8 9 3c00000 1fc00004 abcd0000 1111 1111 1111 tp tp tp tp tp tp tp tp tp tp tp tp thld tsu tsu thld tsu thld thld tsu cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n mem_wait_n memory controller timing diagrams 79rc32334/332 user reference manual 10 - 29 june 4, 2002 notes figure 10.27 shows a dpm-type single word memory write with 2 internally generated wait-states. note that the writes enables, mem_we_n[3:0], are used as t he primary write strobes. note that additional inter- nally generated wait-states will repeat state 4. (type=11, 245=1, wp=0, pw=10, wws=2, rws=1). figure 10.27 dual-port 1 word single write 1 2 3 4 5 6 3c00000 1fc00004 abcd0000 1111 0000 1111 tp tp tp tp tp tp tp tp tp tp tp tp tp tp thld tsu cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n mem_wait_n memory controller timing diagrams 79rc32334/332 user reference manual 10 - 30 june 4, 2002 notes figure 10.28 shows an sram-type single word memory write with 3 internally generated wait-states and then 1 externally generated wait-state as indicated by mem_wait_n asserting. this case provides 1 more wait-state beyond the required minimum of 2 wait-sta tes. note that if the memory controller were programmed such that 3 or more internally generated wait-states occurred, mem_wait_n is ignored until the final wait-state occurs wher e debug_cpu_ack_n would assert. (type=00, 245=1, wp=0, pw=10, wws=3, rws=2). figure 10.28 single word sram write transaction with wait-state figure 10.29 shows a dpm-type four word memory bur st read with 1 internally generated wait-state for each datum. note that both the chip select, me m_cs_n[0] and the output enable, mem_oe_n primarily determine the read access time for the data from the sram. (type=11, 245=1, wp=0, pw=10, wws=2, rws=1). _ figure 10.29 dual-port 4 word burst read 1 2 3 4 5 6 7 3c00000 1fc00004 abcd0000 1111 0000 1111 tp tp tp tp tp tp tp tp tp tp tp tp tp tsu thld thld tsu cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n mem_wait_n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 3c00000 3c00004 3c00008 3c0000c 1fc00004 0 4 8 c 1111 1111 1111 tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tsu thld thld tsu tsu thld thld tsu tsu thld thld tsu tsu thld thld tsu cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n mem_wait_n memory controller timing diagrams 79rc32334/332 user reference manual 10 - 31 june 4, 2002 notes figure 10.30 shows a dpm-type four word memory bur st write with 2 internally generated wait-states. note that the writes enables, mem_we_n[3:0], are us ed as the primary write strobes. (type=11, 245=1, wp=0, pw=10, wws=2, rws=1). figure 10.30 dual-port 4 word burst write 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 3c00000 3c00004 3c00008 3c0000c 1fc00004 abcd0000 abcd0004 abcd0008 abcd000c 1111 0000 1111 0000 1111 0000 1111 0000 1111 tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp tp thld tsu thld tsu thld tsu thld tsu cpu_masterclk mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_245_oe_n mem_wait_n memory controller timing diagrams 79rc32334/332 user reference manual 10 - 32 june 4, 2002 notes notes 79rc32334/332 user reference manual 11 - 1 june 4, 2002 chapter 11 synchronous dram controller introduction the sdram controller supports 4 channels of 32- bit physical banks. because each sdram chip/ channel internally provides 2 to 4 bank arrays of memory, the 4 physical channels have a total of 8 to 16 virtual/conventional page banks. in systems using dimms, the 4 chip selects correspond to 2 dimm cards. only same size banks are supported. a total of 512 mb of sdram memory can be used. each of the dram channels has software selectability as to how much memory space a channel uses. features ? sdram controller (32-bit memory only) ? 4 banks, non-interleaved, 512 mb total (interleaving is not supported) ? automatic refresh generation in the background ? software programmable options support 1 (33mhz), 2 (66mhz), or 3 clock cas latency for 75mhz parts ? software programmable pre-c harge time and refresh time ? supports sdram dimms or sodimms sdram enhancements in y silicon revision the sdram memory controller is one of the modul es that has been enhanced in the y revision of the silicon. table 11.1 outlines some of the signific ant differences between the z and y revisions. for more information on the differences between the silicon revisions, refer to application note an-350, rc32334/ rc32332 differences between z and y revisions, and to the rc32334/rc32332 device errata, both posted on idt's web site at www.idt.com. function z revision y revision comments sdram address line 16 not supported added allows the y revision to address 256 and 512mb sdram devices. note: use of 256mb sdrams was imple- mented for z revision using mem_addr[25:24], an approach that restricted their use to rc32334-based imple- mentations. supported sdram memory configurations 16mb-256mbit 16m-512mbit. addi- tional configurations include64mb: 2mbx32128mb: 32mbx4 allows the part to support larger bursts from external pci bus masters transferring infor- mation to/from sdram. note: legacy bank address to mem_addr line mappings have changed between silicon revisions. table 11.1 sdram differences between z and y revisions (part 1 of 2) synchronous dram controller features 79rc32334/332 user reference manual 11 - 2 june 4, 2002 notes to ensure backwards compatibility with z revision, the new functional ity in y revision is enabled using bits in a new register that was not included in the z revi sion. specifically, the contro l register present in the z revision has been renamed to primary control regist er and a new register, secondary control register, has been added. both registers are shown in table 11.2 below. twr timing uses trp to define mini- mum recovery period after a write. additional option to set recovery period to two clock periods. dqm behavior assertion of dqm signal used to setup external transceivers for buffered sdram systems. dqm asserted 2 clocks early for read accesses. chip select signal would stay asserted for two clocks beyond the access. option to assert dqm only with read or write command. simplifies view and interpreta- tion by logic analyzers of memory cycles. sdram refresh behav- ior burst mode did not sup- port dynamic bytes enables. burst needed all four byte enables to be active for all words in the burst. byte enables are sampled dynami- cally for every datum. simplifies system design and programming of memory con- troller. base address register offset address effective address 1800_0000 sdram primary control register 300 base + offset sdram secondary control register 304 table 11.2 modified and new sdram control registers function z revision y revision comments table 11.1 sdram differe nces between z and y revisions (part 2 of 2) synchronous dram controller block diagram 79rc32334/332 user reference manual 11 - 3 june 4, 2002 notes block diagram figure 11.1 sdram block diagram functional overview the sdram controller provides a glueless interface to industry standard sdrams as well as four chip selects (sdram_cs_n[3:0]), each supporting either two or four sd ram banks. two banks are supported when 16 m-bit sdrams are used; four banks when 64 m-bit sdrams are used. each sdram bank must have a 32-bit data path. as shown in table 11.3, t he sdram controller supports a wide variety of sdrams, allowing the 32-bit data path to be construc ted using x4, x8, x16, or x32 sdrams. sdram size sdram organization sdram chip select total memory 16 m-bit 2mb x 4 x 2 banks 16 mb 1mb x 8 x 2 banks 8 mb 512 kb x 16 x 2 banks 4 mb 64 m-bit 4 mb x 4 x 4 banks 64 mb 2 mb x 8 x 4 banks 32 mb 1 mb x 16 x 4 banks 16 mb 0.5 mb x 32 x 4 banks 8 mb 128 m-bit 8 mb x 4 x 4 banks 128 mb (limit 2 chip selects) 1 4 mb x 8 x 4 banks 64 mb 2 mb x 16 x 4 banks 32 mb 1 mb x 32 x 4 banks 16 mb table 11.3 supported sdrams (part 1 of 2) idt ip bus rc32300 cpu core bus sdram control biu address generator mux latch clk ale ip to cpu & cpu to ip rc32300 address ip address cpu sel [3:0] ip sel [3:0] row/col, inc, load addr page hit page size, bank size ale clk mux latch mem addr [15:2] data register page comparator 16 compare registers cntl register ip slave # 1 ip slave # 2 ip cntl reg sel ip sel [3:0] cpu sel [3:0] ip sel [3:0] from biu cpu sel [3:0] ip sel [3:0] 245 oe & dir sdram cs [3:0] ras,cas,cke,wr dqm[3;0] refresh from timer refresh from timer page size synchronous dram contro ller functional overview 79rc32334/332 user reference manual 11 - 4 june 4, 2002 notes the master input clock to rc32334 is cpu_masterclk, which is used as the system clock for sdrams. all sdram transactions on the memory and peripheral bus are synchronous to this clock. during sdram transactions, the address bus is mult iplexed as shown in table 11.4. the exact address multiplexing is dependent upon the configuration of the page size field in the sdram control register. the sdram controller contains a single control register, since s drams connected to all four chip selects must share a common configuration. the sdram controller does not support the burst addressing mode of sdrams. instead, sdrams must be configur ed to use the pipeline command mode, allowing the sdram controller to simulate bur st operations by issuing a new addr ess on each clock cycle. this allows the sdram controller to perform linear burst operati ons, as required by the dma controller, as well as supporting subblock address ordering read oper ations as required by cache refills. the sdram controller provides the control signals neces sary to control two sets of external buffers, such as 74fct245s, on the rc32334 system data bus (mem_data[31:0]). the buffer output enable (sdram_245_oe_n) pins are the enables for such buff ers, while the external buffer direction (sdram_245_dt_r_n) pin controls the direction. note: the memory and peripheral address bus sdra m_addr [13:2], corresponds to the sdram chip pins a11:a0. sdram[16] is added by multiplexing its functiona lity onto mem_addr[16]. the drive strength for mem_addr[16] must be increased to sdram high dr ive strength. sdram[16] outputs a27, a26, a25, and a24 are based on the sdram ras mux control fi eld setting in the sdram control register. the rc32334 includes a dedicated sdram addres s signal, denoted sdram_addr_12 (a10), which allows transparent refreshes to assert the prec harge_all command during sdram accesses, as well as the appropriate row address during the row addre ss command. this signal should be connected to the a10 pin on the sdram devices. 256 m-bit (rc32334 only) 16 mb x 4 x 4 banks 256 mb 2 (limit 1 chip select) 8 mb x 8 x 4 banks 128 mb 2 (limit 2 chip selects) 4 mb x 16 x 4 banks 64 mb 2 mb x 32 x 4 banks 32 mb 512 m-bit (rc32334 only) 16 mb x 8 x 4 banks 256 mb 2 (limit 1 chip select) 8 mb x 16 x 4 banks 128 mb 2 (limit 2 chip selects) 1. the allocated physical memory map for sdram is 256 mb maximum when using the user mode. the kernel mode can address additional me mory above 0xc000_0000, but it is generally not recommended since the user mode cannot access this physical address space. thus, in practice, several of the 128 m-bi t, 256 m-bit, and 512 m-bit syst ems are limited to using only 1 or 2 of the available 4 chips selects. sdram organization 1 cycle memory and peripheral bu s address (sdram_addr[16:2]) 2 1615141312111098765432 2 mb x 4 x 2 banks 16 mb (10-bit page) pin# ba 3 a10a9a8a7a6a5a4a3a2a1a0 row a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 column a23 ap 4 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 1 mb x 8 x 2 banks 16 mb (9-bit page) pin# ba 3 a10a9a8a7a6a5a4a3a2a1a0 row a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 column a22 ap 4 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 table 11.4 sdram address multiplexing (part 1 of 3) sdram size sdram organization sdram chip select total memory table 11.3 supported sdrams (part 2 of 2) synchronous dram contro ller functional overview 79rc32334/332 user reference manual 11 - 5 june 4, 2002 notes 512 kb x 16 x 2 banks 16 mb (8-bit page) pin# ba 3 a10a9a8a7a6a5a4a3a2a1a0 row a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 column a21 ap 4 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 4 mb x 4 x 4 banks 64 mb (10-bit page) pin# ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 row a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 column a25 a24 a23 ap 4 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 2 mb x 8 x 4 banks 64 mb (9-bit page) pin# ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 row a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 column a24 a23 a22 ap 4 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 1 mb x 16 x 4 banks 64 mb (8-bit page) pin# ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 row a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 column a23 a22 a21 ap 4 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 512 kb x 32 x 4 banks 64 mb (8-bit page) pin# ba1 ba0 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 row a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 column a22 a21 ap 4 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 8 mb x 4 x 4 banks 128 mb (11-bit page) pin# ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 row a26 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 column a26 a25 a12 ap 4 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 4 mb x 8 x 4 banks 128 mb (10-bit page) pin# ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 row a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 column a25 a24 a23 ap 4 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 2 mb x 16 x 4 banks 128 mb (9-bit page) pin# ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 row a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 column a24 a23 a22 ap 4 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 1 mb x 32 x 4 banks 128 mb (8-bit page) pin# ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 row a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 column a23 a22 a21 ap 4 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 16 mb x 4 x 4 banks 256 mb (11-bit page) pin# ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 row a27 a26 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 column a27 a26 a13 a12 ap 4 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 8 mb x 8 x 4 banks 256 mb (10-bit page) pin# ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 row a26 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 column a26 a25 a13 a12 ap 4 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 4 mb x16 x 4 banks 256 mb (9-bit page) pin# ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 row a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 column a25 a24 a13 a12 ap 4 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 sdram organization 1 cycle memory and peripheral bu s address (sdram_addr[16:2]) 2 1615141312111098765432 table 11.4 sdram address multiplexing (part 2 of 3) synchronous dram contro ller functional overview 79rc32334/332 user reference manual 11 - 6 june 4, 2002 notes the sdram_ras_n, sdram_cas_n, sdram_we_n, and sdram_addr[12] signals, summarized in table 11.5, encode the command issued to an sdram. 2 mb x 32 x 4 banks 256 mb (8-bit page) pin# ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 row a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 column a24 a23 a13 a12 ap 4 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 16 mb x 8 x 4 banks 512 mb (11-bit page) pin# ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 row a27 a26 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 column a27 a26 a13 a12 ap 4 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 8 mb x 16 x 4 banks 512 mb (10-bit page) pin# ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 row a26 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 column a26 a25 a13 a12 ap 4 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 1. a25 - a2 denote bits from the rc32334 internal physical address bus. 2. sdram_addr[14:2] pins correspond to the a12:a0 pins on sdram devices. 3. for 16 m-bit bank size, sdra m_addr[14] duplicates sdram_ addr[13] for dimm expandability, such that the sdram ba pin(s) can be connected to sdram_addr[14] instead of sdram_addr[13]. 4. ap - auto precharge (automatically precharged at end of transaction). command description sdram_ras_n sdram_cas_n sdram_we_n sdram_addr[12] nop1 no operation h h h x 1 1. x = don?t care. active select active bank and row lhhrow read select bank and column, perform read (auto pre- charge disabled) hlh l read select bank and column, perform read (auto pre- charge enabled) hlh h write select bank and column, perform write (auto pre- charge disabled) hl l l write select bank and column, perform write (auto pre- charge enabled) hl l l refresh enter self refresh mode l l h x 1 precharge deactivate row in bank (selected by ba) lhl l precharge deactivate row in all banks lhl h table 11.5 sdram command encoding sdram organization 1 cycle memory and peripheral bu s address (sdram_addr[16:2]) 2 1615141312111098765432 table 11.4 sdram address multiplexing (part 3 of 3) synchronous dram contro ller functional overview 79rc32334/332 user reference manual 11 - 7 june 4, 2002 notes base address decoding the sdram base (sdram[3|2|1|0]base) and sdra m mask (sdram[3|2|1|0]mask) registers 1 control the address decoding for each sdram chip selec t. the sdram mask register bit settings control the bits used for address decoding. when a bit in t he sdram mask register equals one, the corresponding address bit is active in address comparisons. if a bit in the sdram mask register equals zero, then the corresponding addres s bit does not participate in address comparisons. all active address bits not masked by the sdram mask register are compared to the value in the sdram base register. if they all match, then the corresponding sdram chip select is asserted. the software selectable regions are as listed in table 11.6. note: because bank1, bank2, and bank3 default to the same base register value, all three registers must be programmed by the boot software, when initializi ng the dram interface to valid base and mask register values before initial access. page row comparators bank row page address comparators are used by th e sdram controller to speed up consecutive multiple bus transactions to the same row of an al ready active bank, i.e., where the upper row address bits are constant but the lower column address bits are changing. each chip select supports up to four bank page row address comparators: two are used with 16 m-bit sdrams and all four are used with 64 m-bit sdrams. although each bank row page address comparator is 12 bits in size (a31:a20), not all bits are used in all sdram configurations. the bank page row address comparators support 1024, 2048 & 4096 byte pages, and because even the smallest application has at least 2 pages to select from, the page comparators will typically be left on as defined by cas a10 (sdram_addr[12]). to decode which page comparator is being used, use ras a11 (sdram_addr[ 13]) (16m-bit) or ras a12/a13 (sdram_addr[14][15]) (64m-bit). when the cpu performs a read or write operation to sdram space, the bank page row address comparator associated with the sdram bank selected is checked. if the bank was left active and the value in the comparator matches the sdram row address, then the access can be made without first closing the currently active page and then opening a different page. if the active page in the bank page row address comparator does not match the sdram row address, before the access can occur, the active page must first be closed (precharged) and the correct page made active. finally, if there is no active page in the bank , the required page must first be made active and then the access can occur. burst support rc32334 does not use the burst addressing mode of sdram chips. instead, the rc32334 uses the ?pipeline command? mode, which imitates a burst by issuing a new address on each clock. the rc32334 is able to burst in subblock address order on bursts fr om the rc32300 cpu core as well as burst in linear address order on bursts up to 1kb. from dma. fi gure 11.2 shows the subblock retrieval method. 1. the bank1 range priority overrides the bank0 range. thus, if the physical address of a memory transaction is such that bank1 is selected, it will override the bank0 row select. similarly, bank3 overrides bank2, which over- rides bank1. default physical address range default base setting default mask setting sdram register description from to 0000_0000 000f_ffff 00 00_0000 fff0_0000 base/ma sk address bank0 0100_0000 010f_ffff 00 10_0000 fff0_0000 base/ma sk address bank1 0100_0000 010f_ffff 00 10_0000 fff0_0000 base/ma sk address bank2 0100_0000 010f_ffff 00 10_0000 fff0_0000 base/ma sk address bank3 table 11.6 base address and base mask address map synchronous dram controlle r sdram initialization 79rc32334/332 user reference manual 11 - 8 june 4, 2002 notes figure 11.2 subblock ordered retrieval method ras/cas address mux using an ras/cas multiplexer?wher e extra address bits can be used for various chip types (1mx16, 2mx8, 4mx4)?provides 32-bit s upport. because common sdram dimms come in a 64-bit width, some users may want to populate rc32334 boards with di screte package(s) in order to provide 32-bit wide memory. alternatively, users can tie a 64- bit dimm module?s data outputs and by te masks together to form two banks of 32-bit sdram. systems consisting of more than eight chips should buffer the address lines. 64m- bit parts, which use 4 internal banks, are supported by using an a dditional address pin as the additional signal. two additional page comparators are added. if the sdram controller?s control register bank si ze is selected to be 16m bank size, then during the row address phase sdram_addr[13] (ba) will be duplicat ed on sdram_addr [14] for dimm upward compati- bility. refresh timer the sdram timer is enabled/disabled through software so that self-refresh can be invoked. an internal interrupt can be optionally generated when the timer ov erflows. in systems with no sdram, the sdram refresh timer can be used as a general purpose timer. this option is enabled by setting the sdram_enable_n bit (31) in the sdram control register to zero, which disables the queueing of sdram refresh transactions when the timer expires. the to stic ky bit in the rtc register is an input to the interrupt controller. a refresh will close all open pages. error recovery the sdram controller is required to abort gracefully on a bus error and bus time-out. both bus errors and bus time-outs latch the present physical address into the buserror address register. this implies that the bus error controller can only assert buserror_n up until the first ack_n would be returned. both ack_n and busreq_n are de-asserted when buser ror_n is asserted, such that the user can connect retry_n instead of buserror_n if desired. on a bus error, the memory controller must ski p to the transaction end state of the primary state machine and return all outputs to their transaction end va lues. a bus time-out may occur at any time during the bus transaction, even after the first ack_n has been returned. if the time-out occurs, then ack_n is immediately returned and if a bur st, the transaction continues. sdram initialization before using, sdrams must be powered up and in itialized in a predefined manner. each sdram contains a mode register which def ines the specific mode of operati on for the sdram. the mode register selects: the burst length, the burst type, cas la tency, operating mode, and write burst mode. the mode register is programmed using an s dram load mode register command. to support compatibility within a wide range of devices , the sdram controller does not directly support the sdram load mode register command. inst ead, this command must be synthesized using an sdram custom transaction, initiated as follows: ? select one or all four of the chip selects (sdram _cs_n[3:0]) in the cs field of the sdram control register ? program the sdram_addr[12] status by setting the sdram_addr[12] bit in t he sdram control regis- start address[3:0] burst sequence 0 (0,4,8,c) 4 (4,0,c,8) 8 (8,c,0,4) c (c,8,4,0) synchronous dram controller register definitions 79rc32334/332 user reference manual 11 - 9 june 4, 2002 notes ter, which then determines the state of the sd _addr[12] pin during an sdram custom transac- tion 1 ? program the write enable status by setting the we bit in the sdram control register, which then determines the state of the dwen pi n during an sdram custom transaction ? program the ras and cas status by setting the r as and cas bits in the sdram control register, which specifies the state of the rasn and c asn signals during an sdra m custom transaction. on the next decoded sdram memory cycle, a trans action will be issued to the sdram with the command programmed in the sdram control register. for the load mode register command, the lower address field bits (a13:a0) determine the value pr ogrammed into the sdram mode register. the chip select signals selected in the chip select field are asserted for one clock cycle and are reset after the command has been executed. the state of the sdram_ras_n, sdram_cas_n, and sdram_we_n signals reflects the state programmed into the sdram control register, until a new command va lue is written into the sdram control register. the state of the sdram_cke signal is reflected directly from the programmed state. the address bus is driven with the column address. if the processor operation was a write 2 , the data bus is driven with the data to be written. using this mechanism, most sdram commands, including load mode register, may be synthesized by the rc32334. after the sdram custom transaction completes, the value of the chip select field in the sdram control register is automatically reset back to zero. register definitions the base address and base mask registers allow selection of the address range to be decoded for each channel. the address map for base address, bas e mask, and primary and secondary control registers is provided in table 11.7. through the sdram prim ary and secondary control registers, various sdram features and options are enabled, as shown in figure 11.3 and table 11.8 for primary and figure 11.4 and and table 11.9 for secondary. 1. set this bit only for a precharge command. 2. the rc32300 cpu core performs a read or write oper ation to sdram space. this causes the rc32334 to assert the sdram chip selects programmed in the cs field of the control register, drive the address bus with the address of the sdram column address, and drive t he sdram custom command programmed in the sdram register. in addition, if the cpu core performed a write operation to sdram space, then the data bus is driven with the data written by the cpu. base address register offset address effective address 1800_0000 dram base address register 0 c0 base + offset dram base mask register 0 c4 dram base address register 1 c8 dram base mask register 1 cc dram base address register 2 d0 dram base mask register 2 d4 dram base address register 3 d8 dram base mask register 3 dc sdram primary control register 300 sdram secondary control register 304 table 11.7 sdram register address map synchronous dram controlle r sdram control registers 79rc32334/332 user reference manual 11 - 10 june 4, 2002 notes sdram control registers sdram primary control register figure 11.3 sdram primary control register fields bit field description 31 sdram controller enable note that if the dram base address range is decoded and the sdram controller is not enabled, and an sdram access is attempted, a bus error will occur. 30:29 sdram ras mux control shifts the ras address to memaddr bit assignments. table 11.8 sdram primary control regist er field descriptions (part 1 of 4) sdram enable page size (mux control) bank size (16/64m-bit) cas trcd auto pre-charge/ page mode latency enable trp trc twr + bit action 8 sdram_addr[12] (sticky write, that is, data retained until rewritten) 7 cke status (sticky write, that is, data retained until rewritten) 6 ras_n status (sticky write, that is, data retained until rewritten) 5 cas_n status (sticky write, that is, data retained until rewritten) 4 we_n status (sticky write, that is, data retained until rewritten) 3 cs_n[3] status (write data retained until next data address decode) 2 cs_n[2] status (write data retained until next data address decode) 1 cs_n[1] status (write data retained until next data address decode) 0 cs_n[0] status (write data retained until next data address decode) 0 sodimm enable output_clk output enable 30 29 28 27 26 25 24 23 22 21 2019 16 15 14 13 9 0 31 reserved to zero 8 value description 1 sdram controller enabled 0 sdram controller disabled (default) value action 11 no shift (11-bit cas) 10 shift 1 (10-bit cas) 4mx4 sdram chips 01 shift 2 (9-bit cas) 2mx8 sdram chips (default) 00 shift 3 (8-bit cas) 1mx16 sdram chips synchronous dram controlle r sdram control registers 79rc32334/332 user reference manual 11 - 11 june 4, 2002 notes 28 sdram bank size field a along with sdram bank field size b, selects which address bits are used for the ba pin(s). 27:26 cas latency (cl) implements a number of clocks needed for the cas phase. the default number of clocks is two. a cas latency of one is not supported by all sdram manufacturers. 25:24 active to r/w command clocks (rcd) value description 23 reserved set to 0 22 bank auto pre-charge / bank remains active this value controls sdram_addr_12 (a10) during the cas phase and is used to control if the sdram controller assumes after each single or burst access that the current bank and bank page row comparator are to be de-activated (similar to non-page mode dram); or that the current bank and bank page row comparator are to remain active in anticipation of a possible follow-on access within the same bank row (similar to page mode dram). bit field description table 11.8 sdram primary control regist er field descriptions (part 2 of 4) value description 1 16 m-bit (2 banks) (default) 0 64 m-bit (4 banks) (typical) note: use for x4, x8, x16 but not x32 wide 64 m-bit parts. 128 m-bit (4 banks) note: use for x4, x8, x16, x32 wide 128 m-bit parts. value action 11 3 clocks 10 2 clocks (default) 01 1 clock 00 reserved value action 11 reserved 10 3 clocks (default) 01 2 clocks 00 1 clock value description 1 bank auto pre-charge (bank row de-acti- vated after each access) 0 bank remains active (bank row left-acti- vated after each access) synchronous dram controlle r sdram control registers 79rc32334/332 user reference manual 11 - 12 june 4, 2002 notes 21:20 pre-charge clocks / pre- charge to active command clocks (trp) and write recovery time clocks (twr) (trp+twr) number of clocks used for sdram pre-charge + write recovery time 19:16 refresh transac- tion clocks (rc) refresh to active clocks 1,2,3,4 15 sodimm enable enables rc32334 controller to operate with sodimm-144 devices. if sdram control regis- ter bit 15 is set to 1, then logically or each pair of sdram chip selects on two new pins, and use the present chip selects for the odd chip select byte masks. sdram_s_n[1] corresponds to chip select 3 and 2. sdram_s_n[0] corresponds to chip select 1 and 0. sdram_cs_n[3:0] correspond to the byte enable dqm signals for chip select 3 and 1. sdram_bemask_n[3:0] correspond to the byte enable dqm signals for chip select 2 and 0. 14 output clk allows the output_clk signal to be driven as an output from the rc32334. when disabled, output_clk signal is tri-stated. default value is 1. 13:9 reserved reserved to zero. 8:4 sdram_addr[12], cke,ras_n, cas_n,we_n status the values in these register bits assert or de-assert the corresponding pins as synced with the cs_n status bits. bit field description table 11.8 sdram primary control regist er field descriptions (part 3 of 4) value description 11 4 clocks (default) 10 3 clocks 01 2 clocks (typical) 00 reserved value description 15-12 reserved 11-3 number of clocks used during a refresh operation (default is 8) 2-0 reserved value description 1 sodimm mode enabled 0 sodimm mode disabled value description 1 enable output_clk signal as output 0 output_clk signal output disabled value description 1 high (default) 0low synchronous dram controlle r sdram control registers 79rc32334/332 user reference manual 11 - 13 june 4, 2002 notes sdram secondary control register figure 11.4 sdram secondary control register fields 3:0 cs_n[3:0] write low waits until the next bank address decode and, while in command write, asserts the pin low for 1 clock and de-asserts the pin high after the command write occurs. bit field description 31:14 reserved 13:12 sdram bank size field b along with sdram bank size field a, selects which address bits are used for the ba pin(s). 11 sdram ras mux control b along with sdram ras mux control field, shifts the ras address to memaddr bit assign- ments. table 11.9 sdram secondary control regi ster field descriptions (part 1 of 2) bit field description table 11.8 sdram primary control regist er field descriptions (part 4 of 4) value description 1 high (default) 0low reserved sdram refresh reserved 31 14 13 12 11 10 9 1 0 priority sdram refresh optimal timing sdram twr sdram dqm sdram ras sdram bank size 2 8 value description 11 reserved 10 256 m-bit or 512 m-bit (4 banks) 01 64 m-bit with x32 wide parts (4 banks) 00 use sdram bank size field a (default value description 1 if sdram ras mux control field = 00, then shift 4 (12-bit cas). if sdram ras mux control field 00, then the shift is undefined (reserved). 0 use the sdram ras mux control field (default). synchronous dram controlle r sdram control registers 79rc32334/332 user reference manual 11 - 14 june 4, 2002 notes 10 sdram dqm 9 sdram twr if the twr field is set, the sdram controller will use the twr field rather than the trp field to time write recovery periods. the trp field can then be programmed to the optimal trp period without regard to adding in the twp period. note: twr is a timing parameter that requires a minimum recovery period after a write. the rc32334 adds an option to optimize pc-100/133 writes using the secondary control reg- ister bit 9. 8:2 reserved 1sdram refresh with optimal timing 0sdram refresh priority . bit field description table 11.9 sdram secondary control regi ster field descriptions (part 2 of 2) value description 1 assert sdram_bemask_n (dqm) only with read or write command. 0 assert sdram_bemask_n (dqm) earlier and deassert later for external transceiver setup and hold (default). value description 1 use 2 clocks for twr independent of trp set- ting (pc100+ setting). 0 use part of trp time to include twr (default/ legacy sdram setting). value description 1 new refresh with optimal timing behavior. access after refresh issues an active com- mand with no preceding precharge (typi- cal). 0 legacy behavior. page mode (ras-left- asserted) access after refresh issues a pre- charge (default). value description 1 new refresh priority. refresh occurs before any new read or write command (typical). 0 legacy behavior. refresh occurs during idle cycles after read or write commands (default). synchronous dram controller timing diagrams 79rc32334/332 user reference manual 11 - 15 june 4, 2002 notes timing diagrams figure 11.5 shows an sdram non-page burst read, as it occurs after the sdram controller has been idle, such as after reset, refresh, or if the page mode is turned off. because no precharge occurs, the row address is captured immediately and a trcd active command to r/w command delay?in this case 2 clocks?then occurs. finally, the co lumn addresses are then captured. note that there is cas latency from the column addr ess until the first data appears, which in this case is 2 clocks. also, in this case, auto precharge has b een programmed?as indicated by the ap symbol?by the col3 sdram_addr. finally, the beginning of the next transaction is shown. a minimum pre-charge time occurs, however, at least 4 clocks coincidently, pr ior to the next transaction because of the rc32300 cpu core bta protocol. (en=1, mux=01, size=0, cl=2, rcd=2, ap=1, rp=4, rc=8, status=ff). figure 11.5 sdram non-page burst read figure 11.6 shows an sdram non-page burst write as it occurs after the sdram controller has been idle, such as after reset, refresh, or if the page mode is turned off. because no precharge occurs, the row address is captured immediately and a trcd active command to r/w command delay?in this case 2 clocks?then occurs. finally, the co lumn addresses are then captured. note that the write data occurs at the same time as its column address and write command. in this case, auto precharge has been programmed, as indicated by the ap symbol, by the col3 sdram_addr. finally, the beginning of the next transaction is shown. a minimum pre-charge time is enforced, in this case 3 clocks, before the next transaction from the sdram controll er can begin. (en=1, mux=01, size=0, cl=2, rcd=2, ap=1, rp=3, rc=8, status=ff). tdo8, tdoh4 tdo8, tdoh4 tdo8, tdoh4 tdo11, tdoh4 tdo11, tdoh4 tdo11, tdoh4 tdo9, tdoh4 tdo9, tdoh4 tdo9, tdoh4 tdo9, tdoh4 tdo9, tdoh4 tdo9, tdoh4 tdo9, tdoh4 tdo9, tdoh4 tdo9, tdoh4 tdo9, tdoh4 tdo9, tdoh4 tdo9, tdoh4 tdo9, tdoh4 tdo9, tdoh4 tdo9, tdoh4 tdo9, tdoh4 tdo9, tdoh4 tdo9, tdoh4 tdo9, tdoh4 tdo9, tdoh4 tdo9, tdoh4 tdo10, tdoh4 tdo10, tdoh4 tdo10, tdoh4 tdo10, tdoh4 tdo10, tdoh4 tdo10, tdoh4 tsu2 tsu2 tsu2 tsu2 tsu2 tsu2 thld2 tsu2 cl cl trcd trcd addr data0 data1 data2 data3 row col0 col1 col2 col3 inhibit active read read read read inhibit addr active ap ap = auto precharge, which is enabled by a12 high. cl = cas latency = 2 nop nop inhibit clk sdram_addr[15:2] mem_data[31:0] sdram_cs_n[x] command[ras,cas,we] sdram_bemask_n[3:0] sdram_cke sdram_245_oe_n sdram_245_dt_r_n synchronous dram controller timing diagrams 79rc32334/332 user reference manual 11 - 16 june 4, 2002 notes figure 11.6 sdram non-page burst write figure 11.7 shows an sdram non-page single word read as it occurs after the sdram controller has been idle, such as after reset, refresh, or if page mode is turned off. because no precharge occurs, the row address is captured immediately, a trcd active command to r/w command delay?in this case 2 clocks? then occurs. finally, the column address is captured. note that there is cas latency from the column address until the data appears, which is 2 clocks in this case. also in this case, auto precharge has been pr ogrammed?as indicated by the ap symbol?by the col sdram_addr. finally, the beginning of the next transac tion is shown. a minimum pre-charge time occurs coincidentally at least 4 clocks before the next tr ansaction begins, because of the rc32300 cpu core bta protocol. (en=1, mux=01, size=0, cl=2, rcd=2, ap=1, rp=4, rc=8, status=ff). figure 11.7 sdram non-page word read figure 11.8 shows an sdram non-page single word write, as it occurs after the sdram controller has been idle, such as after reset, refresh, or if t he page mode is off. because no precharge occurs, the row address is captured immediately and a trcd active command to r/w command delay?in this case 2 clocks? then occurs. finally, the column address is captured. note that the write data occurs at the same time as its column address and write command, as does the sdram_bemask_n[3:0] and dqm bus, indicating which by tes are valid. in this case, auto precharge has been programmed, as indicated by t he ap symbol, by the col sdram_addr. finally, the beginning of the next trp tdo4, tdoh1 trp tdo4, tdoh1 tdo4, tdoh1 tdo4, tdoh1 trcd trcd tdo4, tdoh1 addr data0 data1 data2 data3 row col0 col1 col2 col3 inhibit active write write write write inhibit inhibit addr active ap ap = auto precharge, which is enabled by a12 high. clk sdram_addr[15:2] mem_data[31:0] sdram_cs_n[x] command[ras,cas,we] sdram_bemask_n[3:0] sdram_cke sdram_245_oe_n sdram_245_dt_r_n cl cl trcd trcd addr data0 row col with ap inhibit active read inhibit addr active ap = auto precharge, which is enabled by a12 high. cl = cas latency = 2 nop nop inhibit clk sdram_addr[15:2] mem_data[31:0] sdram_cs_n[x] command[ras,cas,we] sdram_bemask_n[3:0] sdram_cke sdram_245_oe_n sdram_245_dt_r_n synchronous dram controller timing diagrams 79rc32334/332 user reference manual 11 - 17 june 4, 2002 notes transaction is shown. a minimum pre-c harge time is enforced, in this ca se 3 clocks, before the next transac- tion from the sdram controller can begin. the rp field, in this case 3 clocks, must include both the trp precharge time and the twr write recovery time of the sdram ac requirements. ( en=1, mux=01, size=0, cl=2, rcd=2, ap=1, rp=3, rc=8, status=ff ). figure 11.8 sdram non-page word write figure 11.9 shows an sdram page-hit burst read, as it occurs after the sdram controller has been left with an active page open. in this figure, the current memory page matches the previous page. thus, no precharge occurs. the row address is not needed nor is a trcd active command to r/w command delay, so the column addresses are captured. note that there is cas latency2 clocks in this ca se, from the column address until the first data appears. also in this case, page left actively asserted has been programmed, as indicated by the lack of an ap symbol, by the col3 sdram_addr. finally, the beginning of the next transaction is shown. at least 4 clocks coincidently occur before the next transaction because of the rc32300 cpu core bta protocol, at which time a sdram page-hit may reoccur. ( en=1, mux=01, size=0, cl=2, rcd=2, ap=0, rp=2, rc=8, status=ff ). figure 11.9 sdram page-hit burst read figure 11.10 shows a sdram page-hit burst write, as it occurs after the sdram controller has left with an active page open. in this figure, the current memory page matches the previous page, so no precharge occurs. neither the row address or trcd active command to r/w command delay are needed, so the column addresses are captured. trp trcd addr data row col with ap inhibit active write inhibit inhibit addr active ap = auto precharge, which is enabled by a12 high. clk sdram_addr[15:2] mem_data[31:0] sdram_cs_n[x] command[ras,cas,we] sdram_bemask_n[3:0] sdram_cke sdram_245_oe_n sdram_245_dt_r_n cl addr data0 data1 data2 data3 col0 col1 col2 col3 inhibit read read read read addr read ap = auto precharge, which is enabled by a12 high. cl = cas latency = 2 nop nop inhibit clk sdram_addr[15:2] mem_data[31:0] sdram_cs_n[x] command[ras,cas,we] sdram_bemask_n[3:0] sdram_cke sdram_245_oe_n sdram_245_dt_r_n synchronous dram controller timing diagrams 79rc32334/332 user reference manual 11 - 18 june 4, 2002 notes note that the write data occurs at the same time as its column address and write command. in this case, page left actively asserted has been programmed, as indi cated by the lack of an ap symbol, by the col3 sdram_addr. finally, the beginning of the next transaction is shown. at least 2 clocks coincidently occur before the next transaction because of the rc32300 cp u core bta protocol, at which time a sdram page-hit may reoccur. (en=1, mux=01, size=0, cl=2, rcd=2, ap=0, rp=2, rc=8, status=ff). figure 11.10 sdram page-hit burst write figure 11.11 shows a sdram page-hit single word read as it occurs after the sdram controller has been left with an active page open. in this figure, t he current memory page matches the previous page, so no precharge occurs. the row address is not needed nor a trcd active command to r/w command delay, so the column address is captured. note that there is cas latency, 2 clocks in this case, from the column address until the first data appears. also in this case, page left actively asserted has been programmed, as indicated by the lack of an ap symbol, by the col sdram_addr. finally, the beginning of the next transaction is shown. at least 4 clocks coincidently occur before the next transaction, becaus e of the rc32300 cpu core bta protocol, at which time an sdram page-hit may reoccur. (en=1, mu x=01, size=0, cl=2, rcd=2, ap=0, rp=2, rc=8, status=ff). figure 11.11 sdram page-hit word read addr data0 data1 data2 data3 col0 col1 col2 col3 inhibit write write write write inhibit addr write clk sdram_addr[15:2] mem_data[31:0] sdram_cs_n[x] command[ras,cas,we] sdram_bemask_n[3:0] sdram_cke sdram_245_oe_n sdram_245_dt_r_n cl addr data col inhibit read addr ap = auto precharge, which is enabled by a12 high. cl = cas latency = 2 nop nop inhibit clk sdram_addr[15:2] mem_data[31:0] sdram_cs_n[x] command[ras,cas,we] sdram_bemask_n[3:0] sdram_cke sdram_245_oe_n sdram_245_dt_r_n synchronous dram controller timing diagrams 79rc32334/332 user reference manual 11 - 19 june 4, 2002 notes figure 11.12 shows an sdram page-hit single word writ e, as it occurs after the sdram controller has left with an active page open. in this figure, the cu rrent memory page matches the previous page, so no precharge occurs. the row address is not needed nor is a trcd active command to r/w command delay, so the column address is captured. note that the write data occurs at the same time as its column address and write command. in this case, page left actively asserted has been programmed, as indicated by the lack of an ap symbol, by the col sdram_addr. finally, the beginning of the next transac tion is shown. at least 2 clocks coincidently occur before the next transaction because of the rc32300 cp u core bta protocol, at which time an sdram page-hit may reoccur. ( en=1, mux=01, size=0, cl=2, rcd=2, ap=0, rp=2, rc=8, status=ff ). figure 11.12 sdram page-hit word write figure 11.13 shows a sdram page-miss burst read, as it occurs after the sdram controller has been left with an active page open. in this figure, the cu rrent memory page does not match the previous page, so a precharge occurs that is of the pre-charge progra mmed length, in this case 3 clocks. then the row address is captured and a trcd active command to r/w command delay occurs. the column addresses are then captured. note that there is cas latency, 2 clocks in this case, from the column address until the first data appears. also in this case, page left actively asserted has been programmed, as indicated by the lack of an ap symbol, by the col3 sdram_addr. finally, the beginni ng of the next transaction is shown. at least 4 clocks coincidently occur before the next transacti on because of the rc32300 cpu core bta protocol, at which time a sdram page-miss or hit may (re-)occur. ( en=1, mux=01, size=0, cl=2, rcd=2, ap=0, rp=3, rc=8, status=ff ). figure 11.13 sdram page-miss burst read addr data0 col0 inhibit write inhibit addr clk sdram_addr[15:2] mem_data[31:0] sdram_cs_n[x] command[ras,cas,we] sdram_bemask_n[3:0] sdram_cke sdram_245_oe_n sdram_245_dt_r_n cl trcd trp addr data0 row col inhibit active read inhibit cl = cas latency = 2 read read inhibit prechg addr data2 data3 data1 col col col read nop inhibit clk sdram_addr[15:2] mem_data[31:0] sdram_cs_n[x] command[ras,cas,we] sdram_bemask_n[3:0] sdram_cke sdram_245_oe_n sdram_245_dt_r_n synchronous dram controller timing diagrams 79rc32334/332 user reference manual 11 - 20 june 4, 2002 notes figure 11.14 shows an sdram page-miss single word read, as it occurs after the sdram controller has been left with an active page open. in this figure, the current memory page does not match the previous page, so a precharge occurs that is of the pre-charge programmed length , in this case 3 clocks. then the row address is captured and a trcd active command to r/w command delay occurs. the column address is then captured. note that there is cas latency, 2 clocks in this case, from the column address until the first data appears. in this case, page left actively asserted has been programmed, as indicated by the lack of an ap symbol, by the col sdram_addr. finally, the beginning of the next transaction is s hown. at least 4 clocks coincidently occur before the next transaction because of the rc32300 cpu core bta protocol, at which time a sdram page-miss or hit may (re-)occur. (en= 1, mux=01, size=0, cl=2, rcd=2, ap=0, rp=3, rc=8, status=ff). figure 11.14 sdram page-miss word read figure 11.15 shows an 11 clock page mode sdram refresh with the pre-charge clocks field programmed to the value of 3 clocks and the refres h transaction clocks field programmed to the value of 8 clocks. a minimum of 8 clocks occurs before the next ac tive command can occur, which in this figure is a page mode write. note that a non-page mode sdram refresh is simila r, except that the pre-charge all command and the pre-charge clocks field delay do not oc cur. also note that the refresh o ccurs transparently with respect to concurrent memory controller gener ated transactions. the refresh will wait until the current sdram trans- action is complete (if present) and has higher priori ty over the next/new sdra m transaction (if present). (en=1, mux=01, size=0, cl=2, rcd=2, ap=0, rp=3, rc=8, status=ff). figure 11.15 sdram refresh cl trcd trp addr data0 row col inhibit active read inhibit addr read cl = cas latency = 2 nop nop inhibit inhibit prechg clk sdram_addr[15:2] mem_data[31:0] sdram_cs_n[x] command[ras,cas,we] sdram_bemask_n[3:0] sdram_cke sdram_245_oe_n sdram_245_dt_r_n 0 row f 0 f 0 f e f trc=8 trp=3 trp=3 inhibit pa cbr inhibit inhibit active clk sdram_addr[12] sdram_cs_n[3:0] command[ras,cas,we] sdram_bemask_n[3:0] sdram_cke sdram_245_oe_n sdram_245_dt_r_n synchronous dram controller sodimm 79rc32334/332 user reference manual 11 - 21 june 4, 2002 notes connecting the rc32334 to the sdrams below is the recommended address interface between the rc32334 and the sdram banks. a[10] allows ?precharge all banks? during each sdram pr echarge command as well as the appropriate row address during the row address command. sodimm sodimm configuration rc32334 memory configurations can always use discrete parts. in addition, rc32334 is designed to use memory modules. the rc32334 default memory modul e configuration is the 100/168-pin dimm with 4 chip selects. in addition, the rc32334 supports the 144-pin small outline dimm (sodimm-144) with 2 chip selects. the use of sodimm requires two additional pins, sdram_s_n[1: 0]. the sodimm mode requires that the rc32334 sdram control register?s sodimm enable bit be initialized to the sodimm setting. note that when the sodimm mode is enabled, all dimms in the system must use the sodimm signal configuration. in the sodimm mode, the sdram module chip sele cts are provided on the two sdram_s_n[1:0] signals. sdram_s_n[0] is used to select banks 0 and 1 on the first sodimm as programmed by the rc32334 address ranges for banks 0 and 1. sdram_s_n[1] is used to select banks 2 and 3 on an optional second sodimm as programmed by the rc 32334 address ranges for banks 2 and 3. the sodimm mode also changes the behavior of the sdram_bemask_n[3:0] dqm byte mask enables to only assert on even bank selects, 0 and 2. the sodimm mode also changes the behavior of the sdram_cs_n[3:0] chip selects to become dqm byte mask enables that only assert on odd bank selects, 1 and 3. sdram sodimm even bank non-page word read figure 11.16 sdram sodimm e ven bank non-page word read rc32334 sdram banks sdram_addr[15:13] a[13:11] sdram_addr_12 a[10] sdram_addr[11:2] a[9:0] cl cl trcd trcd rowcol with ap inhibit active read inhibit active ap = auto precharge, which is enabled by a12 high. cl = cas latency = 2 nop nop inhibit clk sdram_addr[15:2] sdram_s_n[x] command[ras,cas,we] sdram_bemask_n[3:0] sdram_cs_n[3:0] sdram_cke sdram_245_oe_n sdram_245_dt_r_n synchronous dram controller sodimm 79rc32334/332 user reference manual 11 - 22 june 4, 2002 notes figure 11.16 shows an sdram sodimm even bank non- page word read as it occurs after the sdram controller has been idle, such as after reset, refr esh, or if page mode is turned off. because no precharge occurs, the row address is captured immediately, a tr cd active command to the r/w command delay (in this example a 2 clock delay) then occurs. finally, the column address is captured. the module select, sdram_s_n[0] will assert if bank 0 is accessed or sdram_ s_n[1] will assert if bank 2 is accessed. the even dqm bus signals, sdram_bemask_n[3:0], are asserted instead of the odd dqm bus signals, sdram_cs_n[3:0]. note that the burst, write, and page mode accesses for even banks are similar to this case. sdram sodimm odd bank non-page word read figure 11.17 sdram sodimm o dd bank non-page word read figure 11.17 shows an sdram sodimm odd bank non- page word read as it occurs after the sdram controller has been idle, such as after reset, refr esh, or if page mode is turned off. because no precharge occurs, the row address is captured immediately, a tr cd active command to the r/w command delay (in this example a 2 clock delay) then occurs. finally, the column address is captured. the module select, sdram_s_n[0] will assert if bank 1 is accessed or sd ram_s_n[1] will assert if bank 3 is accessed. the odd dqm bus signals, sdram_cs_n[3:0], are asse rted instead of the even dqm bus signals, sdram_bemask_n[3:0]. note that the burst, write, and page mode accesses for odd banks are similar to this case. cl cl trcd trcd rowcol with ap inhibit active read inhibit active ap = auto precharge, which is enabled by a12 high. cl = cas latency = 2 nop nop inhibit clk sdram_addr[15:2] sdram_s_n[x] command[ras,cas,we] sdram_bemask_n[3:0] sdram_cs_n[3:0] sdram_cke sdram_245_oe_n sdram_245_dt_r_n synchronous dram controller sodimm 79rc32334/332 user reference manual 11 - 23 june 4, 2002 notes sdram sodimm refresh figure 11.18 sdra m sodimm refresh figure 11.18 shows an 11 clock page mode sdram sodi mm refresh with the pr e-charge clocks field programmed to the value of 3 clocks and the refres h transaction clocks field programmed to the value of 8 clocks. a minimum of 8 clocks occur before the nex t active command can occur, which in this example is a page mode write. note that a non-page mode sdram refr esh is similar, except that the pre-charge all command and the pre-charge clocks field delay do not occur. also note that the refresh occurs transparently with respect to concurrent memory controller generated transactions. the refresh will wait until the curr ent sdram transaction is complete (if present) and has higher priority over the next/new sd ram transaction (if present). the m odule selects, sdram_s_n[1:0], are both asserted. (en=1, mux=01, size=0, cl=2, rc d=2, ap=0. rp=3, rc=8, status=ff.) (sodimm=1.) output_clk usage the rc32334 provides an output_clk output. this cloc k follows the cpu_masterclk with an approximate 5ns phase delay which aligns the tr ansmit direction control, address, and data signals to a transmit clock. conventional non-registered pc66, pc100, and pc133 sdrams cannot take advantage of the output_clk output feature. instead, it is recommended that most systems use the cpu_maste rclk as the sdram clock. because the output_clk output is enabled at reset time, unless used elsewhere in the system as a transmit aligned clock, output_clk can be turned off to sa ve power using the rc32334 sdram control register output_clk output enable bit. please see the rc32334 design considerations doc ument at www.idt.com for the latest sdram recommendations, especially concerning the use of transceivers, speed grades, and data width. 0 row 3 0 3 0 3 2 3 trtc=8 trtc=8 trp=3 trp=3 inhibit pa cbr inhibit inhibit active cbr = auto refresh; pa = precharge all, which is enabled by a12 low. clk sdram_addr[12] sdram_s_n[1:0] command[ras,cas,we] sdram_bemask_n[3:0] sdram_cs_n[3:0] sdram_cke sdram_245_oe_n sdram_245_dt_r_n synchronous dram controller sodimm 79rc32334/332 user reference manual 11 - 24 june 4, 2002 notes notes 79rc32334/332 user reference manual 12 - 1 june 4, 2002 chapter 12 pci interface controller introduction the pci interface controller complies with pci local bus specification, revision 2.2 1 . both master and target modes are supported. the interface implements 3.3v pci-compliant pads (5v tolerant). the pci bus operates up to 66 mhz and supports burst transfers. the pci interface controller serves as a pci bridge between the pci bus and the rc32334 internal bus. the bl ock diagram of the pci interface controller is shown in figure 12.1. the pci bus interface contains two separate data pat hs, one for access initiated by the cpu or dma and one for access initiated by an external pci agent. each path has its own fifo, and each path operates independently from the other. the pci controller uses a dedicated dma engine, separate from the four general purpose dma controller channels described in chapter 13, to initiate pci bus target transfers to and from local memory. features the pci interface module includes the following functions: ? master and target controllers ? host or satellite (adapter card) mode ? capability to access confi guration registers from cpu ? target lock support ? pci bus arbitration selection in host mode ? internal arbiter provides: - fixed priority or round robin - arbitrate 3 2 external pci masters ? capability to disable internal arbiter to implement arbiter function externally ? mailbox registers ? software programmable endianness byte swapper ? address translation between cpu addr ess space and pci address space ? independent dma engine for pci target transfers from pci bus to cpu memory ? support for plug and play pci interface enhancements in y silicon revision the pci interface is one of the modules that has been significantly enhanced in the y revision of the silicon. ttable 12.1 outlines some of the signific ant differences between the z and y revisions. for more information on the differences between the silicon revisions, refer to application note an-350, rc32334/ rc32332 differences between z and y revisions, and to the rc32334/rc32332 device errata, both posted on idt's web site at www.idt.com. 1. for operational details and/or timing diagrams not included in this chapter, refer to the pci 2.2 specification. 2. arbitrate 2 external pci masters for the rc32332. pci interface controller features 79rc32334/332 user reference manual 12 - 2 june 4, 2002 notes function z revision y revision comments pci specification sup- ported 2.1 2.2 fifo size for target read and target writes 8 words deep in each direction. 16 words deep in each direction. allows the part to support larger bursts from external pci bus masters transferring infor- mation to/from sdram. fifo size for master read and master writes 8 words deep in each direction. read fifo is 8 words deep, write fifo now 16 words deep. maximum burst size for target writes one word eight words significant performance improvement for bursts of data from external pci bus mas- ters. number of bar regis- ters 2 4 allows users to program cer- tain bars for sdram and others to system control regis- ters, preventing multiple changes to the bar register. improves time taken to switch between tasks. programmability of bar address bits upper four bits of bar are programmable. upper 24 bits are programmable. provides more efficient use of memory space for applications where rc32332/4 is config- ured for satellite mode opera- tion (example - pci-add in cards). priority of pci target reads versus writes behavior writes favored over reads. multiple writes can be buffered, but reads cannot. write fifo must be flushed before target read is allowed to complete. retry of target writes during read opera- tions made optional. option to perform eight word fetch for one word request. opportunity to balance read and write operations. "eager prefetch" not available part will continue to perform target read operations until its fifo is full. significant performance improvement for applications moving large blocks of data across pci. trdy counter behavior holds pci bus for 16 cycles before retrying a transaction. bus can be held longer than 16 cycles. violates the pci specification, but provides opportunity to optimize platform and mini- mize wasted pci cycles. table 12.1 pci differences between z and y revisions pci interface controller functional overview 79rc32334/332 user reference manual 12 - 3 june 4, 2002 notes to ensure backwards compatibility with z revision, the new functional ity in y revision is enabled using bits in new registers that were not included in the z revision. these new register s are shown in table 12.2 below. functional overview during reset, three reset initialization pins (mem _addr[22:20]) must be set up properly to select the desired pci and boot modes for the rc32334. table 12.3 shows all of the possi ble mode configurations with the settings of mem_addr[22-20] pins, which are latched after reset. the pci interface controller can be in either host mode or satellite mode . when the pci boot mode option is selected at reset, the pci host can write to the pci master enable bit. this is because the pci target not ready bit (pci ar bitration register, bit 2) is cleared when the pci boot mode option is selected. figure 12.1 pci interface controller block diagram address register 0x1800_20a0 new feature register 0x1800_20a4 pci target control register table 12.2 additional pci control registers mem_addr[22:21] mem_addr[20] description 0 0 0 host mode, boot from me mory controller, serial eeprom not supported 0 0 1 satellite mode, boot from memory controller, serial eeprom not supported 0 1 0 not allowed 0 1 1 satellite mode, boot from pci serial eeprom 1 0 x reserved 1 1 x tri-state memory bus and eeprom bus during coldreset_n assertion. table 12.3 initialization pins mem_addr[22:20] settings memory control dram control dma bus interface unit cpu pci target control internal bus master control internal bus control slave pci master control rc32334 system bus internal bus (idt peripheral bus) pci configuration registers eeprom (optional in boot from pci pci interface controller pci bus pci target receive fifo pci target transmit fifo pci master receive fifo pci master transmit fifo pci interface controller internal registers i/o mode) memory pci interface controller functional overview 79rc32334/332 user reference manual 12 - 4 june 4, 2002 notes memory mapping figures 12.2 and 12.3 show the cpu to pci memory mapping and the pci to cpu memory mapping, respectively. figure 12.2 cpu to pci memory mapping cpu virtual address (4 ranges) cpu virtual address mapped to physical local bus address mapped via tlb range 1 (up to 512mb) b8c0_0000 - b8ff_ffff (w/ non-pci-boot reset option) or bfc0_0000 - bfff_ffff (w / pci-boot reset option) b880_0000 - b88f_ffff mapped via tlb range 2 (up to 512mb) 4000_0000 - 5fff_ffff (v ia tlb, 512mb) 6000_0000 - 7fff_ffff (v ia tlb, 512mb) 1880_0000 - 188f_ ffff (via fixed mapping, 1mb) 18c0_0000 - 18ff_ffff (via fixed mapping, 4mb) cpu/dma local bus physical addresses assigned to fixed pci memory or i/o spaces (4 ranges) pci memory space 1 pci memory space 2 (top 4-bits substituted) pci memory space 3 pci i/o space via tlb or fixed mapping; or address originates as dma local bus address (4 ranges) cpu/dma local bus physical address mapped via ? pci memory space [3:1] base register ? or ? pci i/o space base register ? into pci address (4 ranges) pci memory space 1 (top 4-bits substituted) pci memory space 4 (top 4-bits substituted) pci i/o space (top 12-bits substituted) pci memory space 2 or 1fc0_0000 - 1fff_ffff (v ia fixed mapping, 4mb) example: b880_1234 example: 1880_1234 example: 1880_1234 example: 0000_1234 (i/o) pci interface controller functional overview 79rc32334/332 user reference manual 12 - 5 june 4, 2002 notes figure 12.3 pci to cpu memory mapping rc32334 pci bus target operation the pci interface of the rc32334/rc32332 integrated pr ocessors is optimized to support transfers for external pci bus masters that initiate the transmiss ion/reception of data to/from local sdram (termed as target mode in this chapter). when the device is c onfigured for target operatio n, the module supports up to seven queued target write commands and one queued ta rget read command. when these queues are exceeded, the pci host transaction will be retri ed until the command can be accepted. when the rc32334 pci is configured as a target, external pc i masters can perform up to 8 word bursts. the pci target interface allows an external pci master to be able to read and write any local memory address. this allows an external pci master to acce ss local sdram, memory-i/o (8, 16 or 32-bit memory) or any internal register. the pci target interface aut omatically performs byte sc attering (writes) and gath- ering (reads) for devices on the memo ry and peripheral bus, and partial wr ites and reads for sdrams. pci bus accesses to 8-/16-/32-bit exte rnal i/o are supported, provided t hat the i/o addresses are aligned on a word boundary and that the data is located in the correc t 1/2/4 byte lanes. note there is no byte unpacking. therefore, for 8- or 16-bit accesses t he reminder of the word will not be used. the pci bus master can read/write to memory through a cpu memory space 1 br. the cpu memory space 1 br translates a pci address to a local physi cal cpu address by modifying the top upper 24 bits are programmable. this means that t he minimum memory size is 256 bytes. similarly, when accessing i/o peripherals, the cpu i/o space br translates a pci address to a local physical cpu address by modifying the top 24 address bits of the pci address. for i/o accesses, note that only the top 8 address bits of the pci address bus ar e used, as the i/o space accessed from the pci bus is limited to 64 words (256 bytes). the endianness swap se tting can be modified for each of the above brs by setting a bit in each br. the rc32334 pci does not support the cache line wrap mode defined in the pci specification. thus, the rc32334 pci master never generates a cache line wrap mode. a cache line wrap mode cannot be generated from pci agents, since the rc32334 does not recognize this mode. if this mode is generated from the pci bus, the rc32334 device will treat the access as linear incrementing. the pci bus interface supports tar get locking. once a lock has been es tablished, all pci target transac- tions to the rc32334/rc32332 device ar e retried until the lock has been released. lock operations are useful for creating atomic sequences as seen by external masters on the pc i bus. lock accesses cannot be issued when the rc32334 is a pci master. note that on pci target accesses to memo ry and io, 0x0xxx_xxxx and 0x0000_00xx spaces are decoded. this enables conventional debug and no n-pc system usage of this address space. pci address decoded by 32334/32332 target pci ? memory base address register ? ( bar1 , pci address translated to local bus physical address by the bar 1 (up to 4gb) bar 4 (up to 4gb) bar 3 (up to 4gb) bar 2 (up to 4gb) cpu memory space 1 (up to the top 24-bits substituted) ? pci to cpu i/o space base register? (4 ranges) example: 7f00_c840 (i/o) example: 1f00_c840 bar2 , bar4 ) or target pci ? i/o base address register ? ( bar3 ) (4 ranges). ? pci to cpu memory space [4,3,1] ? or cpu i/o space (up to the top 24-bits substituted) cpu memory space 2 (up to the top 24-bits substituted) cpu memory space 4 (up to the top 24-bits substituted) the bar?s are setup via the pci configuration register space rather than the local bus memory space. pci interface controller functional overview 79rc32334/332 user reference manual 12 - 6 june 4, 2002 notes pci target burst transactions which attempt to bur st data beyond the address space allocated to a bar will terminate with a target disconnect without data. the pci address spaces m apped by two bar registers may be contiguous. pci target burst transactions wh ich attempt to burst data across adjacent address spaces mapped by bar registers will terminat e with a target disconnect without data. pci target control in the pci to cpu memory and i/o space base register s contain additional fields beyond the bar register which control the behavior of the pci bus interface when acting as a pci target. these include: ? a retry timer controls the number of pci clock cycle s the pci interface will wait (to receive the first data of an access) before it issues a retry command. this is used during target read operations (i.e., memory read, memory read multiple, memo ry read line, and i/o read) to specify the number of pci clock cycles the pci bus interface is allow ed to wait (for the first data quantity of a transac- tion) before the transaction must be retried. duri ng target write operations (i.e., memory write, memory write and invalidate, and i/o write), this fiel d specifies the number of pci clock cycles the pci bus interface is allowed to wait (for space to appear in the pci target input fifo) before a transaction must be retried. the initial value for the retry timer is specified in the retry timer (rtimer) field of the pci cpu memory and i/o space base register. note that pci 2.2 sets the maximum to 16 pci clock cycles. however, th e rc32334/rc32332 device allows this limit to be extended up to 255 clock cycles. although this violat es the pci specification, it does provide an opportunity to optimize pci bandwidth for systems with known pc i-based peripherals. ? a disconnect timer controls the number of pci cl ock cycles the pci inte rface will wait between data transfers. if the pci bus interface is unable to accept data before the timer expires, the pci bus will be released. pci 2.2 specification allo ws a maximum of 8 pci clock cycles, but the rc32334/rc32332 allow a value of up to 255 clock cycles. the pci bus interface supports target delayed r eads. the pci bus interface supports only one pending delayed read. if a read is attempted while a delay ed read is pending, the transaction is retried and a delayed read is not initiated for the transaction. the external pci master that initiates a delayed read is expected to retry the transaction until the read completes. the pci bus interface contains a discard timer. if the master does not repeat a delayed read request within 2 15 clock cycles, the disc ard timer will expire and discard the pending read. if the discard timer ex pires and a pending read is discarded, then the pending read discarded (prd) bit is set in t he pci controller interrupt pending regi ster. note that the discard timer can be disabled by setting the disable discar d timer (ddt) bit in the pcitc register. the pci transaction ordering constraints may be viewed as favoring target write operations, since only a single delayed read is allowed when t here are posted writes, while multip le posted writes are allowed when there is a delayed read. there is also an ?eager prefetch? mode. when enabled, the target read pci block will continue to fetch data until its fifo is filled. since the new fifo is 16 words, this means that a single word fetch can result in 16 words, divided into two bursts, being fetched across the local bus. this will result in substantial throughput improvements in cases of long block reads. ho wever, this mode should be used with caution. if the system is not moving blocks of data, but rather doing isolated reads from specific locations, enabling these features will degrade system performance rather than improve it. note that the last 16 words of physical memory should not be accessed by a prefetchable pci target read. if they are accessed, a system error via the pc i_serr_n signal may be signa lled since the target read prefetch may try to access non-existent memory beyond the physical memory bank, thereby generating a local bus non-decoded address error. rc32334 pci bus master operation rc32334 pci bus master operation is defined as cpu co re or general purpose dma initiated read/write transfers between the rc32334 and the pci bus. the addr ess map is shown in table 12.4 when the cpu core or dma controller wants to access the pci bus . the cpu or dma can read/wr ite to targets on the pci bus through 3 pci memory spaces. in pci master m ode, the device can perform quad-word bursts for both read and write accesses. when accessing pci memory space, the corresponding pci memory space base register (br) translates a local physical cpu addres s into a pci address by modifying the top 4 address bits of the local cpu address. pci interface controller functional overview 79rc32334/332 user reference manual 12 - 7 june 4, 2002 notes similarly, when accessing pci i/o space, the pci i/o space base register translates a local physical cpu address into a pci address by modifying the top 4 address bits of the local cpu address. the brs can point to the same or over lapping address spaces, if desired. the endianness sw ap setting can be modi- fied for each of the brs by setting a bit in each br. when the rc32334 pci is configured as a master, it can perform quad-word burst for both read and write accesses. rc32334 pci bus target operation rc32334 pci bus target operation is def ined as an external device that initiates a pci bus read or write transfers between the pci bus and external memory or between the pci bus and an i/o peripheral. note that only 32-bit wide external memory is supported. the pci bus master can read/write to memory through a cpu memory space 1 br. the cpu memory space 1 br translates a pci addr ess to a local physical cpu address by modifying the top upper 24 bits are programmable. this means that the minimum memory size is 256 bytes. the pci controller uses a dedicated dma engi ne, separate from the four general purpose dma controller channels described in chapter 13, to initiate pci bus target transfers to and from local memory. similarly, when accessing i/o peripherals, the cpu i/o space br translates a pci address to a local physical cpu address by modifying the top 24 address bits of the pci address. note that only the top 8 address bits of the pci address bus are used for i/o accesses, as the i/o space accessed from the pci bus is limited to 64 words (256 bytes). the endianness swap setting can be modified for each of the above brs by setting a bit in each br. the rc32334 pci bus target supports pci bus accesses to 8-/16-/32-bit external i/o, assuming the i/o addresses are aligned on a word boundary and that the data is located in the correct 1/2/4 byte lanes. note there is no byte unpacking. therefore 8- or 16-bi t access the reminder of the word will not be used. when the rc32334 pci is configured as a target, exte rnal pci masters can only perform up to 8 word bursts. if the write address is such that it will cross a 1024-byte boundary (minimum sdram page size), the current write will end when the 0x3fc offset is reached and a new ipbus write is ready to begin. the rc32334 pci does not support the cache line wrap mode defined in the pci specification. thus, the rc32334 pci master never generates a cache line wrap mode. a cache line wrap mode cannot be generated from pci agents, since the rc32334 does not recognize this mode. if this mode is generated from the pci bus, the rc32334 device will treat the access as linear incrementing. the rc32334 pci controller supports lock accesses w hen rc32334 is a pci target. however, the lock accesses cannot be issued when the rc32334 is a pci master. note that on pci target accesses to memo ry and io, 0x0xxx_xxxx and 0x0000_00xx spaces are decoded. this enables conventional debug and no n-pc system usage of this address space. pci satellite mode the pci bus interface can also be configured for satellite mode operation. the satellite mode can be initiated in two ways: from to allocation 1800_2000 1800_2fff pci internal registers (4kb) 1880_0000 188f_ffff pci i/o space (1m) 18c0_0000 18ff_ffff pci memory space 3 (4mb) (for non- pci boot reset option) 1fc0_0000 1fff_ffff pci memory space 3 (4 mb) (for boot from pci bus option) 4000_0000 5fff_ffff pci memo ry space 1 (512mb) 6000_0000 7fff_ffff pci memo ry space 2 (512mb) table 12.4 pci address map pci interface controller functional overview 79rc32334/332 user reference manual 12 - 8 june 4, 2002 notes ? the satellite can boot from the memory controller. in this case, the bootstrapping code for the satel- lite resides in the local memory space from which the satellite board boots up ? the satellite can boot from the pci serial eeprom. in this case, the satellite loads its configuration registers from a serial eeprom and t hen attempts to boot over the pci bus. in either case, the host pci bridge in the system is required to program the pci configuration registers prior to the satellite generating or re ceiving any pci cycles on the pci bus. to ensure the correct satellite mode of operati on, the system controller needs to configure mem_addr[22:20] bits on reset. when mem_addr[22:20] is configured to [001], the satellite is set to boot from the memory controller. when mem_addr[22:20] is c onfigured to [011], the satellite is set to boot from the pci serial eeprom. booting from the memory controller booting from the memory controller, the satellite mode receives and generates pci cycles on the pci bus. the initialization steps are as follows: 1. configure the local boot rom on the satellite system to: ? link local pci registers and cpu (pci to cpu and cpu to pci) ? set up the pci configuration register master latency timer, cacheline size, retry timeout, trdy timeout, etc. ? reset the pci target not ready bi t in the pci arbitration register. 2. configure the satellite pci configur ation registers using the host pci bridge: ? memory base address register (configuration header offset: 0x10) ? i/o base address register (c onfiguration header offset: 0x18) ? enable the bus master, memory, and i/o access in the pci configuration command register. booting from the pci serial eeprom the satellite mode, booting from the pci serial eeprom , loads the pci configurat ion registers from the serial eeprom. the initializa tion steps are as follows: 1. program the serial eeprom with the desired configuration register values. 2. configure the satellite pci configur ation registers usi ng the host pci bridge. ? memory base address register (configuration header offset: 0x10) ? i/o base address register (c onfiguration header offset: 0x18) ? enable the bus master, memory, and i/o access in the pci configuration command register. once the satellite pci interface is enabled by the hos t pci bridge by writing to the command configura- tion register, the satellite generates an instruction fe tch cycle with the local bus physical address 0x1fc0 0000. this address is translated to the pci bus address 0x0fc0 0000 before being placed on the pci bus by the satellite?s local pci memory space 3 ba se register, its contents being all 0?s on reset. the satellite can only boot from a 32-bit port-width ex ternal device sitting across the pci bus. the target device selected for the pci address 0x0fc0 0000 must have a 32-bit boot memory in this address space (typically a 32-bit eprom space or an sdram space where the bootstrap code for the satellite is placed prior to enabling the satellite). the target not ready bi t in the pci arbitration register is reset by default. also, the buserror is disabled at power up in this mode. the buserror must be enabled by the startup code as soon as the satellite is initialized in order to catch any non-decodable address cycles on the pci bus. in the pci-boot mode, the system controller internal biu buserror register has the cpu buserror, ip buserror, and watch dog timeout bits disabled, which allows the rc32334 to wait indefinitely for the pci host to initialize the system. serial eeprom interface when booting from pci, the serial eeprom is used to load the pci configuration header in the satellite mode. the boot serial eeprom must be compatible with and at least as large as the nm93cs46 (1024-bit or greater), which uses the microwire tm of national semiconductor se rial protocol. the rc32334 will sequentially read each of the regist er addresses listed in table 12.5, starting from eeprom address 0x00, skipping unused addresses, and continuing until eepr om address 0x3e. each eeprom address corre- pci interface controller functional overview 79rc32334/332 user reference manual 12 - 9 june 4, 2002 notes sponds to a 16-bit datum (not the 8-bit datum that pci address uses ), such that each eeprom address holds a 16-bit pci field. thus, all odd eep rom addresses are unused by the rc32334 pci eeprom interface and can be used for other storage purposes. th e 16-bit pci fields correspond to the definitions of the corresponding pci configuration registers. pci commands supported the rc32334 pci master supports pci memory re ad line and memory write invalidate commands. memory read line performs a quad-wo rd burst read and memory writ e invalidate performs a quad-word write. to enable the memory write invalidate command, the cache line size in the cacheline size configura- tion register must be nonzero (see figure 12.21), the memory write and invalidate enable bit in the command configuration register (see figure 12.17) must be enabled, and a burst write must be generated from the cpu or, more typically, from the dma. as a pci target, the rc32334 supports memory read line, memory read multiple, and memory write invalidate. table 12.6 summarizes the pci command codes suppor ted (and not supported) by the controller as master and as target. field name eeprom address device id 0x00 vendor id 0x02 status 0x04 class code (msb?s) 0x08 class code (lsb), revision id 0x0a header type 0x0c subsystem id 0x2c subsystem vendor id 0x2e min_lat, min gnt 0x3c interrupt pin 0x3e table 12.5 pci serial eeprom address fields cben[3:0] command as a master as a target 0000 interrupt acknowledge no ignored 0001 special cycle no ignored 0010 i/o read yes yes 0011 i/o write yes yes 010x reserved 0110 memory read yes yes, prefetch 4 words 0111 memory write yes yes 100x reserved 1010 configuration read yes yes 1011 configuration write yes yes 1100 memory read multiple no yes, prefetch 8 words table 12.6 pci commands (part 1 of 2) pci interface controller functional overview 79rc32334/332 user reference manual 12 - 10 june 4, 2002 notes pci configuration register access the way rc32334 interfaces and accesses the configurat ion registers is defined in the pci specification 2.1, section 3.7.4.1, configuration mechanism #1. this mechanism requires the following two rc32334 internal registers be defined to access pci configuration space: ? pci configuration address register at 1800_2cf8 ? pci configuration data register at 1800_2cfc. a pci configuration register should be accessed in the following manner: a. write the desired address of a configuration regi ster to the pci configuration address register b. read from (or write to) the pci configurati on data register to receive (or to send) data. the data in the pci configuration data register w ill be automatically received from (or sent to) the desired configuration regist er. the device number field of the pci c onfiguration address register is used to select the idsel line of the pci satellite to be configured. see table 12.7 below. device number 0x00 refers to the pci host (rc 32334) in which case the transaction is handled inter- nally and the pci bus remains idle. device numbers 0x15 to 0x01 will assert a single pci_ad[31:11] line high during the configuration access shown in table 12.7. the pci system board is assumed to resistively couple the appropriate pci_ad[31:11] line to each satellite?s pci_idsel line. before the rc32334 can be ready to perform any pci operations, its pci configuration registers must be set up correctly. the rc32334 pci master and target are defaulted to not ready (disabled) after reset. if the rc32334 pci is in host mode, then the cpu needs to configure the rc32334 pci configuration registers, including read-only confi guration registers. the rc32334 pci ta rget is not ready until the pci target not ready bit (bit 2 of the pci arbitration r egister) is set to 0. when the rc32334 pci target is not ready, all the pci assesses to rc32334 from the pci bus will be retried by the pci controller. thus, after the writing of configuration regist ers is complete and rc32334 is ready, bit 2 of the arbitration register needs to be set to 0 to enable the rc32334 pci target operations. 1101 dual address cycle no ignored 1110 memory read line yes, quad word burst read yes, aliased to memory read 1111 memory write and invalidate yes, quad word burst write yes, aliased to memory write device number address line device number address line device number address line 0x00 internal access 0x08 pci_ad[18] 0x10 pci_ad[26] 0x01 pci_ad[11] 0x09 pci_ad[19] 0x11 pci_ad[27] 0x02 pci_ad[12] 0x0a pci_ad[20] 0x12 pci_ad[28] 0x03 pci_ad[13] 0x0b pci_ad[21] 0x13 pci_ad[29] 0x04 pci_ad[14] 0x0c pci_ad[22] 0x14 pci_ad[30] 0x05 pci_ad[15] 0x0d pci_ad[23] 0x15 pci_ad[31] 0x06 pci_ad[16] 0x0e pci_ad[24] ? ? 0x07 pci_ad[17] 0x0f pci_ad[25] ? ? table 12.7 pci device to idsel mapping cben[3:0] command as a master as a target table 12.6 pci commands (part 2 of 2) pci interface controller signal definitions 79rc32334/332 user reference manual 12 - 11 june 4, 2002 notes when writing the configuration registers, the rc3 2334 in host mode will perform 5 extra cycles of address stepping, such that the pci address is vali d for 5 clocks before pci_frame_n is asserted. this allows the target to resistively coupl e an address signal to its pci_idsel pin. if the rc32334 pci is in satellite mode, read-only configuration registers can be loaded by the cpu core. if the cpu core finishes loading the read-only confi guration registers in the satellite mode, then bit 2 of the pci arbitration register needs to be set to 0, so that the rc32334 pci target can respond to accesses from the pci bus. if the boot mode initialization c hooses to use the eeprom to load read-only configura- tion registers, then the system us ing the rc32334 will be booted from the pci bus after reset, instead of from the normal local bus address space. to enable rc32334 pci master operation, the enable bus master bit in the configuration command register must be set to 1 either by the cpu core if the rc32334 pci is in host mode or by an external pci host if in satellite mode. pci polling error handling when the rc32334 device issues a config_read cycle to an unpopulated pci slot, the device should read back 0xffffffff. the rc32334 can al so be configured to ignore pci bus errors. this is controlled through bit 7 in the bus interface unit (biu) buserr control register. even when buserror is disabled, a bus error interrupt is still generated wh ich can be polled by pci bios software. pci interrupts if the pci bus writes a 1 to one of the low order 4 bits in the pci_to_cpu mailbox pending register, then a corresponding interrupt is generated to the cpu core via the internal cpu_int_n[3] signal and the cpu core must service and clear this interrupt. (for testi ng purposes only, the cpu may also set the interrupt.) if the cpu writes a 1 to one of the low order 4 bits in the cpu_to_pci pending mailbox register, then a corre- sponding interrupt is generated to the pci bus via the pci_inta__n pin, and this interrupt needs to be cleared from the pci bus. note that the pci_to_cpu mailbox interrupt can be generated in either host or satellite mode, while cpu_to_pci mailbox interrupts can be generated only in the satellite mode. the cpu core or dma can initiate a pci access and k now whether it is failed or not by enabling both the pci master read error interrupt and the pci master writ e error interrupt defined in the pci controller inter- rupt pending register. note that both interrupts must be enabled to ensure that a rc32334 pci master access error can be observed. if only one of the interr upts is enabled, then a master access error may not be detected. to enable any pci address or data parity error detection by the pci interface controller, both the parity error response bit and serr# enable bit must be enabled in the command configuration register. two kinds of parity errors can be reported to t he cpu by using two specific interrupt s. these two errors are pci target write data parity error, and pi master data parity er ror, as indicated in the pci controller interrupt pending register. signal definitions note that the pci_serr_n i/o signal to the rc 32334 is connected as an output, but the signal is not connected internally inside the device as an input. us ers wishing to utilize th is signal should connect this signal externally to either the cpu_nm i_n signal or a high priority interrupt line on the pci host. additionally, a pci_eeprom_cs signal has been added as a pio pin. this enables exter nal eeproms, configured in the pci memory address space, to be written to and repr ogrammed. to support the feature, an extra pio register has also been added. note that the i/o directi on of pci_gnt_n[1] is controlled by the pio direction register, not by the pci arbiter mode. see c hapter 15, programmable i/o (pio) controller. when the rc32334 is in pci satellite mode, the pc i_gnt_n[2:0] and pci_req_n[2:0] pins on the rc32334 each have a different name and use 1 . table 12.8 shows the name and the direction of each pin for the different settings of rc32334. a complete description of all pci signals is prov ided in chapter 1, rc32334 device overview. 1. depending on the pci mode for which the default is configured. pci interface controller register definitions 79rc32334/332 user reference manual 12 - 12 june 4, 2002 notes register definitions rc32334 in host mode rc32334 in satellite mode reset use internal arbiter use external arbiter pci_gnt_n[2], output tri-stated if host pci_gnt_n[2], out- put not used, tri-stated pci_inta_n, open-collec- tor output pci_gnt_n[1], bidirectional 1 1. pci_gnt_n[1] output enable control is determined by the pio pin direction register bit field, wh ich defaults to the output dire c- tion at reset. output pci_gnt_n[1], out- put not used, output pci_eeprom_cs, output pci_gnt_n[0], bidirectional tri-stated pci_gnt_n[0], out- put pci_req_n=output pci_gnt_n, input pci_req_n[2], input tri-stated pci_req_n[2], input not used, tri-stated pci_idsel, input pci_req_n[1], input 2 2. there is no pci_req_n[1] in the rc32332. tri-stated pci_req_n[1], input 2 not used, tri-stated not used, tri-stated pci_req_n[0], bidirectional tri-stated pci_req_n[0], input pci_gnt_n, input pci_req_n, output table 12.8 rc32334 muxed pci pin names and directions base address register function offset address effective address 1800_0500 pci controller interrupt pending register 11 b0 base + offset 1800_0500 pci controller interrupt mask register 11 b4 1800_0500 pci controller interrupt clear register 11 b8 1800_0500 cpu to pci mailbox interrupt pending register 12 c0 1800_0500 cpu to pci mailbox interrupt mask register 12 c4 1800_0500 cpu to pci mailbox interrupt clear register 12 c8 1800_0500 pci to cpu mailbox interrupt pending register 13 d0 1800_0500 pci to cpu mailbox interrupt mask register 13 d4 1800_0500 pci to cpu mailbox interrupt clear register 13 d8 1800_2000 pci new feature register 0a0 1800_2000 pci target control register 0a4 1800_2000 pci memory and i/o space 1 base register 0b0 1800_2000 pci memory and i/o space 2 base register 0b8 1800_2000 pci memory and i/o space 3 base register 0c0 1800_2000 pci memory and i/o space 4 base register 0c8 1800_2000 pci arbitration register 0e0 1800_2000 pci cpu space1 base register 0e8 1800_2000 pci cpu space 2 base register 0f4 1800_2000 pci cpu space 3 base register 100 table 12.9 pci interface control register address map (part 1 of 2) pci interface controller register definitions 79rc32334/332 user reference manual 12 - 13 june 4, 2002 notes note: a detailed description of interrupt related r egisters is provided in chapter 14, expansion interrupt controller. pci controller interrupt pending register 11 figure 12.4 pci controller interrupt pending register 11 fields cpu to pci mailbox interrupt pending register 12 setting a bit in the cpu to pci mailbox interrupt pending register by the cpu will generate a corre- sponding interrupt to the pci bus. figure 12.5 cpu to pci mailbox interrupt pending register 12 fields 1800_2000 pci cpu space 4 base register 10c 1800_2000 pci configuration address register cf8 1800_2000 pci configuration data register cfc bit field description 31:5 reserved 4 pci pending read dis- carded (prd) allow interrupt from a pci target read to be discarded as the discard timer expired. 3 pci target write data parity error interrupt interrupt due to a data parity error of a target write to the rc32334 pci 2 pci master data parity error interrupt interrupt due to a data parity error of a rc32334 pci master read or write 1 pci master read error interrupt interrupt indicating a failed pci master access, which may be possibly caused by a pci master read 0 pci master write error interrupt interrupt indicating a failed pci master access, which may be possibly caused by a pci master write table 12.10 pci controller interrupt pending register 11 field descriptions base address register function offset address effective address table 12.9 pci interface control register address map (part 2 of 2) pci target write data parity error interrupt pci master data parity error interrupt pci master read error interrupt pci master write error interrupt reserved 31 5 4 3 2 1 0 pci pending read discarded see expansion interrupt controller chapter int3 int2 int1 int0 16 15 14 13 12 11 31 0 see expansion interrupt controller chapter pci interface controller register definitions 79rc32334/332 user reference manual 12 - 14 june 4, 2002 notes table 12.11 cpu to pci mailbox interr upt pending register 12 field descriptions pci to cpu mailbox interrupt pending register 13 external pci bus masters may access the pci to cpu mailbox interrupt pending register via a rc32334 target memory or i/o access. this assumes that ei ther the pci cpu memory space base register or the pci cpu i/o space base register is set up to allow access to the rc32334 system controller physical address range base of 0x18000000. setting a bit in the pci to cpu mailbox interrupt pending register by the pci bus will generate a corre- sponding interrupt to the cpu bus. figure 12.6 pci to cpu mailbox in terrupt pending register 13 fields pci memory space [1,2,3] base register whenever pci memory is accessed from the cpu or dma, the high order 4 bits of the cpu physical address are replaced by bits 31:28 of th is register to generate the pci address. bit field name description 31:16 see chapter 14, expansion interrupt controller. 15 interrupt 3 0 = no interrupt (default) 1 = interrupt pending 14 interrupt 2 0 = no interrupt (default) 1 = interrupt pending 13 interrupt 1 0 = no interrupt (default) 1 = interrupt pending 12 interrupt 0 0 = no interrupt (default) 1 = interrupt pending 11:0 see chapter 14, expansion interrupt controller. bit field name description 31:4 reserved 3 interrupt 3 0 = no interrupt (default) 1 = interrupt pending 2 interrupt 2 0 = no interrupt (default) 1 = interrupt pending 1 interrupt 1 0 = no interrupt (default) 1 = interrupt pending 0 interrupt 0 0 = no interrupt (default) 1 = interrupt pending table 12.12 pci to cpu mailbox interr upt pending register 13 field descriptions 31 reserved 4 3 2 1 0 int3 int2 int1 int0 pci interface controller register definitions 79rc32334/332 user reference manual 12 - 15 june 4, 2002 notes figure 12.7 pci memory space [1,2,3] base register pci i/o base register whenever i/o space is accessed from the cpu or dma, the high order 12 bits of the cpu physical address are replaced by bits 31:20 of th is register to generate the pci address. note that if compatibility with existing software wr itten for the rc32134 system controller is desired, this register should be programmed with 0x _ 88 _ _ _ _ h. figure 12.8 pci i/o base register bit field name description 31:28 pci memory i/o base default to 0 these 4 bits replace the top 4 bits of the cpu physical address 27:1 reserved 0 0 endianness swap value description 1 = byte swap 0 = no byte swap (default) table 12.13 pci memory space [1,2,3] base register field descriptions bit field name description 31:8 cpu memory or i/o base default value is 0. up to the top 24 bits translate/rep lace the top 24 bits of the pci address with a local bus address. the size field determines the number of bits to translate/replace. 7 reserved reserved to ?0?. table 12.14 pci i/o base register field descriptions (part 1 of 2) pci memory base endianness swap reserved 31 28 27 1 0 pci i/o base endianness swap reserved 31 8 7 2 1 0 size 6 reserved pci interface controller register definitions 79rc32334/332 user reference manual 12 - 16 june 4, 2002 notes new feature register this register is not present in the z revi sion of the rc32334/rc32332 devic es. to ensure backwards compatibility, new functionality was provided by adding new registers. upon syste m boot-up, this register defaults to provide compatibility with z revision silicon as follows: ? bit 1 is zero, enabling configuration read cycles to generate an interrupt should a pci error occur ? bit 0 is zero, enabling bits 23:20 of the pci base register to progr am higher order bits. when a config_read cycle is generated, a pci error will produce read data as 0xffffffff. with the pci config read suppress bus error bit field set in the pci new feature register, the pci interface controller suppresses the generation of an ipbus erro r for config read errors and returns the read data as 0xffffffff. thus, neither a bus erro r exception to the cpu nor an ipbus error interrupt will occur. even with this bit set, non-config reads to conventional pci memory space still signal a cpu bus error. 6:2 size address space size. this field indicates the size of the address space for the corresponding pci base address register and the num- ber of the cpu memory or i/o base bits to translate/replace. all bits greater than or equal to size in the memory or i/o base address register (bar) may be modified. bits less than size and greater than or equal to bit 4 always return a value of zero when read and cannot be modified. setting the size field to a value less than 8 disables the pci base address register from decoding and causes the appropriate bar bits to always return a value of zero when read and cannot be modified. one may also view this field as indicating the number of the most significant bit to be used in the decode, the minimum number being the 8th upper most significant bit. all bits greater than or equal to size in the cpu memory or i/o base field are used to translate/replace the top bits of the pci address with a local bus address. 1 reserved reserved to ?0?. 0 endianess swap this bit controls byte swapping for pci transactions that map to the local bus through the bar register. bit field name description table 12.14 pci i/o base register field descriptions (part 2 of 2) value description >= 8 set size to 2 size 28 set size to 2 28 7 to 1 set size to 0, i.e., disabled 1 set size to 0, i.e., disabled (default for bar2 and bar4) 0 set size to 2 28 (default for bar1 and bar3) value description 1 byte swap 0 no byte swap (default) pci interface controller register definitions 79rc32334/332 user reference manual 12 - 17 june 4, 2002 notes figure 12.9 pci new feature register . pci target control register a new register for the y revision of silicon, pci target control register, is added at physical address 0x1800_20a4. figure 12.10 pci target control register bits field name description 31:2 reserved 1 config read sup- press bus error . 0 shift cpu to i/o base field . table 12.15 pci new feature register field descriptions shift cpu to i/o base config read suppress reserved 31 2 1 0 bus error value description 1 suppress internal ipbus error generation on pci config read errors. 0 ipbus bus error generated on pci config read errors (default). value description 1 use the pci to cpu i/o base register base address field and size field to program bits 31:8 (which corre- sponds to bits 31:8). 0 use bits 23:20 of the pci to cpu i/o base register field to program bits 31:28 (requires the pci to cpu i/o base register size field to be set to 2 28 ). 31 0 refer to table 12.14 pci interface controller register definitions 79rc32334/332 user reference manual 12 - 18 june 4, 2002 notes bits field name description 31 reserved reserved to ?0?. 30 eager prefetch for bar4 eager prefetch mode. on a memory read line or a memory read multiple command decoded by memory base address register 4 (bar4), after the initial prefetch, if the target read continues without a disconnect and the target read fifo has at least 8 data words empty, then prefetch the next block of data. 29 reserved reserved to ?0?. 28 eager prefetch for bar2 1 eager prefetch mode. on a memory read line or a memory read multiple command decoded by memory base address register 2 (bar2), after the initial prefetch, if the target read continues without a disconnect and the target read fifo has at least 8 data words empty, then prefetch the next block of data. 27 eager prefetch for bar1 1 eager prefetch mode. on a memory read line or a memory read multiple command by memory base address register 1 (bar1), after the initial prefetch, if the target read continues without a disconnect and the target read fifo has at least 8 data words empty, then prefetch the next block of data. 26 mwmwi memory write and memory write and invalidate behavior. in some system dependent applications, reducing the target write burst size on the local bus may help balance target read vs. write throughput. table 12.16 pci target control register field descriptions (part 1 of 4) value description 1 use eager prefetch mode. 0 do not use eager prefetch mode (default). value description 1 use eager prefetch mode. 0 do not use eager prefetch mode (default). value description 1 use eager prefetch mode. 0 do not use eager prefetch mode (default). value description 1 burst up to 8 words on the local bus. 0 burst up to 4 words on the local bus (default). pci interface controller register definitions 79rc32334/332 user reference manual 12 - 19 june 4, 2002 notes 25:24 threshold threshold for target write fifo. the threshold setting provides hysteresis on the incoming pci stream, ensuring that pci burst writes are accepted in 4 or 8 data word increments. note that the fifo threshold takes into account one command/address word fifo location such that the actual internal fifo pointer representation is the data word threshold + 1 com- mand/address word. 23 mrml4 memory read and memory line behavior for memory base address reg- ister 4 (bar4). 22 reserved reserved to ?0?. 21 mrml2 memory read and memory line behavior for memory base address reg- ister 2 (bar2). bits field name description table 12.16 pci target control register field descriptions (part 2 of 4) value description 3 reserved. 2 threshold = 8 data words. wait until at least 8 data words are free in fifo before accepting any new write commands. 1 threshold == 4 data words. wait until at least 4 data words are free in fifo before accepting any new write commands (default). 0 no threshold (threshold == 1 data word). wait until at least 1 data word is free in fifo before accepting any new write commands. value description 1 prefetch 8 words on memory read and memory line target accesses similar to memory read multiple. 0 if the bar for the decoded target memory read or memory read line indicates the prefetchable attribute is enabled, prefetch 4 words (default). value description 1 prefetch 8 words on memory read and memory line target accesses similar to memory read multiple. 0 if the bar for the decoded target memory read or memory read line indicates the prefetchable attribute is enabled, prefetch 4 words (default). pci interface controller register definitions 79rc32334/332 user reference manual 12 - 20 june 4, 2002 notes 20 mrml1 memory read and memory line behavior for memory base address reg- ister 1 (bar1). 19 edt enable discard timer. when a master does not repeat a delayed read request within 2 15 pci clock cycles the pci interface discards the delayed completion. when this bit is not set, delayed completions are never dis- carded. note that an interrupt may optionally be set when the timer expires. 18 rdr retry when delayed read. when this bit is set, all transactions are retried as long as there is an uncompleted delayed read being executed on the local bus. once the pci target read command is accepted, the pci target write fifo is flushed. meanwhile, additional pci target writes are accepted but not issued until after the pci target read is issued. once the pci target write fifo is flushed and the pci target read is issued, all new pci transactions are retried. warning : setting this bit may violate the pci 2.2 specification -- see imple- mentation note in the pci 2.2 specification section 3.3.3.3.4. bits field name description table 12.16 pci target control register field descriptions (part 3 of 4) value description 1 prefetch 8 words on memory read and memory line target accesses similar to memory read multiple. 0 if the bar for the decoded target memory read or memory read line indicates the prefetchable attribute is enabled, prefetch 4 words (default). value description 1 discard timer enabled (default). 0 discard timer disabled. value description 1 retry writes when delayed read. 0 post writes (default). pci interface controller register definitions 79rc32334/332 user reference manual 12 - 21 june 4, 2002 notes pci arbitration register when the rc32334 pci is in the host mode, either an internal arbiter or an external arbiter can be selected. the internal arbiter can arbitrate up to four 1 pci masters, including the rc32334 device itself. when the internal arbiter is used, either a round robi n or a fixed priority arbi tration scheme can be chosen. if the rc32334 pci is in the satellite mode, then the external arbiter is always used. at boot time, in the standard reset boot mode, the pci target not ready bit is set. this allows the pci configuration registers to be written from the cpu and from the pci side. a fter initialization, this bit should be cleared so that normal pci operation, which requires the configuration registers to be in read-only mode, can begin. note: most conventional masters are able to take advantage of idle grant mode enabled. 17:16 reserved reserved to ?0?. 15:8 dtimer disconnect timer. this field specifies the number of pci clock cycles the pci interface will wait between data phases in an access before issuing a disconnect. a side effect of a disconnect is that any prefetched data in the target read fifo will be flushed. the pci 2.2 specification sets the maxi- mum limit of this timer at 8 pci clock cycles, but in some systems it may be necessary to extend this limit for more optimal performance. the minimum disconnect timer value is four. values less than four are aliased to four. 7:0 rtimer retry timer. this field specifies the number of pci clock cycles the pci interface will wait (to receive the first data of an access) before a retry com- mand is issued. the pci 2.2 specification sets the maximum limit of this timer at 16 pci clock cycles, but in some systems it may be necessary to extend this limit for more optimal performance. 1. to fully utilize the eager prefetch mode, the target disconnect time r (dtimer) should be set hi gh enough to avoid prac- tically all disconnects, and the master should issue memory read multiple commands using large blocks (for instance 64 words or more). 1. two pci masters for the rc32332. bits field name description table 12.16 pci target control register field descriptions (part 4 of 4) value description any pci target interface will wait for subsequent data of an access before issuing a retry. 0x08 pci target interface will wait 8 clocks for subsequent data of an access before issuing a retry (default). value description 0xff- 0x08 pci target interface will wait the specified number of pci clocks for the first data of an access before issu- ing a retry. 0x10 pci target interface will wait 16 clocks for the first data of an access before issuing a retry. (default). 0x08 minimum value allowed. 0x07- 0x00 reserved pci interface controller register definitions 79rc32334/332 user reference manual 12 - 22 june 4, 2002 notes figure 12.11 pci arbitration register fields pci to cpu memory/io space [1,2,3,4] base registers whenever local cpu memory is accessed via the pci bus, the upper 4 bits of a pci address are substi- tuted to create a cpu physical address. figure 12.12 pci to cpu memory/io space [1,2,3,4] base register bit field name description 31:5 reserved 4 arbiter idle grant mode arbiter idle grant mode. if enabled, the arbiter idle grant mode may use pci spec. rules to withdraw a grant during idle cycles and then grant a higher priority master. if disabled, the arbiter will not withdraw a grant unless the original requesting mas- ter withdraws its request, the master asserts pci_frame_n, or until a pci arbiter timeout occurs where 16 pci clocks occur after a grant and pci_frame_n has not been asserted by the master. 3 arbiter park mode enable arbiter park mode enabled. when the pci bus interface is configured to operate in pci host mode using an internal arbiter, this bit selects the bus parking mode to park the bus on the last master that was granted access to the bus. if the arbiter park mode is disabled, then the pci arbiter will return to idle when no masters are requesting the bus. 2 pci target not ready 0 = pci target ready (default if pci-boot mode is selected) 1 = pci target not ready (default if standard boot mode is selected) 1 arbitration type 0 = use internal arbiter 1 = use external arbiter (default) 0 arbitration mode 0 = round robin. rotating sequence is rc32334 pci, pci_req_n[0], pci_req_n[1] 1 , pci_req_n[2], and so on. 1 = fixed priority (default). priority order is rc32334 pci, pci_req_n[0], pci_req_n[1] 1 , pci_req_n[2], with the highest priority assigned to the rc32334 pci. 1. there is no pci_req_n[1] in the rc32332. table 12.17 pci arbitration register field descriptions arbitration mode arbitration type pci target not ready reserved 31 5 4 3 2 1 0 arbiter idle grant mode arbiter park mode enable value description 1 pci arbiter idle grant mode enabled. 0 pci arbiter idle grant mode disabled (default). value description 1 pci arbiter park mode enabled. 0 pci arbiter park mode disabled (default). cpu memory or i/o base endianness reserved 31 8 7 6 2 1 0 swap size reserved pci interface controller register definitions 79rc32334/332 user reference manual 12 - 23 june 4, 2002 notes bit field name description 31:8 cpu memory or i/o base default value is 0. up to the top 24 bits translate/replace the top 24 bits of the pci address with a local bus address. the size field determines the number of bits to translate/replace. 7 reserved reserved to 0 6:2 size address space size. this field indicates the size of the address space for the corresponding pci base address register and the number of the cpu memory or i/o base bits to translate/replace. all bits greater than or equal to size in the memory or i/o base address register (bar) may be modified. bits less than size and greater than or equal to bit 4 always return a value of zero when read and cannot be modified. setting the size field to a value less than 8 disables the pci base address register from decoding and causes the appropriate bar bits to always return a value of zero when read and cannot be modified. one may also view this field as indicating the number of the most sig- nificant bit to be used in the decode, the minimum number being the 8th upper most significant bit. all bits greater than or equal to size in the cpu memory or i/o base field are used to translate/replace the top bits of the pci address with a local bus address. summary of pci bar size decoding valid values bar1: 28 (0), 27, 26 bar2: 27, 26, 25, or disabled (1) bar3: 8 (0) bar4: 27, 26, 25, or disabled (1) 1 reserved reserved to 0 0 endianness swap this bit controls byte swapping for pci transactions that map to the local bus through the bar register. table 12.18 pci to cpu memory/io space [1,2,3,4] base register field descriptions value description 28 bar1: set size to 2 28 27 bar1, bar2, bar4: set size to 2 27 26 bar1, bar2, bar4: set size to 2 26 25 bar2, bar4: set size to 2 25 1 bar2, bar4: set size 0, i.e., disabled (default for bar2 and bar4) 0 bar1: set size to 2 28 bar3: set size to 2 8 (default for bar1 and bar3) other all other values are reserved. value description 1 byte swap 0 no byte swap (default) pci interface controller rc32334 pci configuration registers 79rc32334/332 user reference manual 12 - 24 june 4, 2002 notes pci configuration address register figure 12.13 pci configurat ion address register fields pci configuration data register figure 12.14 pci configurat ion data register field rc32334 pci configuration registers the pci configuration space is described in this section. table 12.21 shows the bits used, the read/ write status, and the base address of each register. shaded registers are read-only registers after being loaded and areas with x?s are ?don?t-care s?. each of the registers is described in the sections following this table. these shaded read-only registers can be written (wher e applicable and allowed) by the cpu by first enabling the pci target not ready bit in the pci arbi tration register and then foll owing this two-step proce- dure: 1. write the pci configuration register address as a pointer into the register number field of the pci configuration address register. 2. write the data to the pci configuration data register. the non-shaded status and read/write r egisters in table 12.21 may only be read or written by the cpu when the pci interface controller is configured to be in host mode. when the pci interface controller is configured to be in satellite mode, the non-shaded stat us and read/write registers may only be read by the bit field name description 31 enable bit 0 = disabled 1 1 = enabled 1. if the enable bit is illegally disabl ed (because there is no analogous pc-at i/o address space in the mips architec- ture) then the pci target state machine is fully reset. 30:24 reserved 23:16 bus number pci bus number 15:11 device number pci device number. 2 asserts pci_ad[31:11] for device numbers 0x15 through 0x01. 2. device number 0 refers to the rc32334?s host device (which is itself). 10:8 function number pci function number 7:2 register number pci configuration register address 1:0 hardwired to 00 table 12.19 pci configuration addr ess register field descriptions bit field name description 31:0 data data value of configuration read/write access table 12.20 pci configuration data register field description 31 30 24 23 16 15 11 10 8 7 2 1 0 enable bit reserved bus number device number function number register number 0 0 31 0 data pci interface controller rc32334 pci configuration registers 79rc32334/332 user reference manual 12 - 25 june 4, 2002 notes cpu by first enabling the pci target not ready bit in the pci arbitration register and then following the two step pointer/data procedure listed in the paragr aph above. in satellite mode, the non-shaded status and read/write registers may never be cleared or written by the cpu. during a configuration register access or other ac cess that results in an error?for example, an unde- coded access to an empty pci slot?the pci controller will return the data value 0xffffffff to the cpu. a buserror will also result unless masked by the internal biu buserror control bits for cpu and ip accesses. typically, during empty slot polling, the inte rnal biu buserror control register?s bit 7 (buserror exception disable) can be disabled. this will prevent a cpu exception from being generated, and the buserror interrupt can be handled/ignored by the expansion interrupt controller. vendor id register this read/write register specifies the vendor of this device. this register must be set to 111dh. figure 12.15 vendor id register 0x111d is the idt vendor id. bits used address 31 16 15 0 device id vendor id 00h status command 04h class code revision id 08h bist header type master latency timer cacheline size 0ch memory/io base address 1 10h memory/io base address 2 14h memory/i/o base address 3 18h memory/io base address 4 1ch xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 20h xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 24h xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 28h subsystem id subsystem vendor id 2ch xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 30h reserved 34h reserved 38h max_lat min_gnt interrupt pin interrupt line 3ch reserved retry timeout value trdy timeout value 40h reserved 44h-ffh table 12.21 rc32334 pci configuration registers bit description reset 15:0 vendor id 111dh table 12.22 vendor id address field description 15 0 vendor id pci interface controller rc32334 pci configuration registers 79rc32334/332 user reference manual 12 - 26 june 4, 2002 notes device id register this read/write register specifie s the id to identify this device. on the rc32332 it is recommended that the pci device id be written as 0205h, either through the configuration register interface or, if in the pci boot mode, through the pci boot eeprom. using t he recommended value will di stinguish the controller from the rc32334. the default for the rc323 32 is 204h, the same value as the rc32334. figure 12.16 device id register pci command register the pci command register is a r ead/write register that provides protocol control to generate and respond to pci cycles. note that system errors typically occur due to address or data parity errors. however, if a target access occurs that is undec oded by the local memory bus, a system error will also occur, which is generally only recoverable by t he master aborting its retries and resetting the rc32334. figure 12.17 pci command register bit description reset 31:15 device id 0x0204h 1 1. 0x0205h for the rc32332. table 12.23 device id address field description bit description reset 15:10 reserved 0h 9 fast back-to-back master enable 0h 8 system error enable 0 7 reserved 6 parity error enable 0 5 reserved 4 memory write and invalidate enable (mwinv). allows master write and invali- date operations if the cacheline size configuration register is nonzero and a burst write is issued from the dma or cpu. 0 3 reserved 2 bus master enable when pci boot mode option is selected at reset, pci master enable bit can be written to by the pci host because the pci target not ready bit (pci arbitration register bit 2) is cleared when the pci boot mode option is selected at reset. 0 1 memory access enable 0 0 i/o access enable 0 table 12.24 command register 31 16 device id i/o bus reserved mwinv memory access access master reserved enable parity error enable reserved reserved fast master enable back-to-back 15 10 9 8 7 6 5 4 3 2 1 0 system error enable pci interface controller rc32334 pci configuration registers 79rc32334/332 user reference manual 12 - 27 june 4, 2002 notes pci status register the pci status register reports the status of operations on the pci bus. it also indicates the pci _ devsel # timing that has been selected. if the arbitration register pci target not ready bit is set, then the 66mhz-capable flag (as well as ot her read-only flags ) may be written. note: except for bit 5, this is a register with a mixture of clearable status bits and read-only bits. updates of bit 5 should be done through a read (other read-only bits), mask (status bits), modify, and write series of operations. figure 12.18 pci status register device revision identification register this read-only register contains the cu rrent revision identifier for this device. figure 12.19 configuration device revision identification register bit description reset type 15 detect parity error 0 status 14 signaled system error 0 status 13 received master abort status. set when pci master terminates a host-to-pci transaction with a master abort. 0 status 12 received target abort status. set when the core initiates a pci transaction and it is terminated by the target. 0 status 11 signaled target abort status 0 status 10:9 device select timing. indicates timing of pci_devsel# when the core responds to a pci transaction as a target. 01 ro 8 data parity detected 0 status 7 fast back-to-back capable status flag. 1 ro 6 reserved 0 ro 5 66 mhz-capable status flag. application software can set this bit to indicate the pci interface can be operated at 66mhz. 1 write/read 4:0 reserved 0h ro table 12.25 configuration pci status register bit description reset 7:0 revision identification number 01h table 12.26 configuration device revision identification register field description signaled system error rx target abort signaled abort status target reserved 66 mhz-capable status flag reserved status timing device select data parity detected master 15 14 13 12 11 10 9 8 7 6 5 4 0 detect error rx abort status fast bk2bk capable status flag error revision identification number 7 0 pci interface controller rc32334 pci configuration registers 79rc32334/332 user reference manual 12 - 28 june 4, 2002 notes class code register the class code register c ontains a code value identifying the generic function of this device. the codes listed in table 12.28 duplicate pci 2.2 specification. figure 12.20 class code register cacheline size the cacheline size register specifies the system cache line size in units of 32-bit words. it allows master write and invalidate operations if the pci command regi ster mwinv bit is set and a burst write is issued from the dma or cpu. figure 12.21 cacheline size register bit description reset 31:8 class code value 000000h table 12.27 class code register field description base class device type 00h device built before standardized definition of class codes 01h mass storage controller 02h network controller 03h display controller 04h multimedia device 05h memory controller 06h bridge device 07h simple communication controllers 08h base system peripherals 09h input devices 0ah docking stations 0bh processors 0ch serial bus controllers 0dh - feh reserved ffh device does not fit in any designated class table 12.28 class code definitions 31 8 class code value 7 0 cacheline size pci interface controller rc32334 pci configuration registers 79rc32334/332 user reference manual 12 - 29 june 4, 2002 notes the pci system requirements specify that the cachel ine size must default to 0 at reset time. the rc32334 requires that the maximum ca cheline size be no greater than 4. master latency timer register the master latency time register is an 8-bit read/write register that c ontrols the amount of time that the core, as a bus master, can perform burst transfers if another master requests the bus. the two least signifi- cant bits are hardwired to zero, allowing inte rval changes in increments of four clocks. figure 12.22 master latency timer register fields header type header type is defined in section 6.2.1 of the pci 2.1 specification. figure 12.23 header type register field bist this capability is not supported. figure 12.24 bist register field bit description reset 7:0 cacheline size 00h table 12.29 configuration cacheline size field description bit description reset 15:10 master latency timer count value this register sets the minimum number of pci clock cycles that the core will be guaranteed access to the pci bus. after the count has expired the core will surrender the pci bus as soon as other pci master devices are granted the bus by the arbiter. 00h 9:8 reserved: hardwired to 0. 0h table 12.30 master latency timer register field descriptions bit description reset 23:16 header type. 00h table 12.31 header type register field description reserved master latency timer count value 15 10 9 8 23 16 header type 23 16 bist pci interface controller rc32334 pci configuration registers 79rc32334/332 user reference manual 12 - 30 june 4, 2002 notes pci memory/io base address [1,2,3,4] registers this register contains the bas e address (bar1-4) through which t he pci memory space is accessed. bars1, 2, and 4 are memory base addresses by default; bar3 is an i/o base address by default. figure 12.25 pci memory/io base address [1,2,3,4] register bit description reset 23:16 built in self test, hardwired to 0 00h table 12.32 bist register field description bits description reset 31:8 memory or i/o base address 000000h 7:4 reserved 0h 3 prefetchable (hardwired to prefetchable). 1 2:1 port bus width. hardwired to indicate 32 bit width. 00b 0 i/o space vs. memory space (hardwired to memory space). 0 table 12.33 memory/io base address re gister 1 (bar1) field description p width i/ 0 memory base or i/o base 31 8 7 4 3 2 1 reserved 0 value description 1 prefetchable (hardwired default) 0 not prefetchable (reserved) value description 1 i/o space (reserved) 0 memory space (hardwired default) pci interface controller rc32334 pci configuration registers 79rc32334/332 user reference manual 12 - 31 june 4, 2002 notes . bits description reset 31:8 memory or i/o base address 000000h 7:4 reserved 0h 3 prefetchable. note that if not prefetchable is selected, then all types of pci reads, including memory read, memory read multiple, and memory read line, will fetch 1 word at a time on the local bus to fulfill the exact number of words required for the read. 0 2:1 port bus width. hardwired to indicate 32 bit width. 00b 0 i/o space vs. memory space (hardwired to memory space) 0 table 12.34 memory/i/o base address registers 2 and 4 (bar2,4) field description bits description reset 31:8 memory or i/o base address 000000h 7:4 reserved 0h 3 prefetchable (hardwired to not prefetchable) 0 2:1 port bus width. hardwired to indicate 32 bit width. 00b 0 i/o space vs. memory space (hardwired to i/o space) 1 table 12.35 memory/i/o base address register (bar3) field description value description 1 prefetchable 0 not prefetchable (default) value description 1 i/o space (reserved) 0 memory space (hardwired default) value description 1 prefetchable (reserved) 0 not prefetchable (hardwired default) value description 1 i/o space (hardwired default) 0 memory space (reserved) pci interface controller rc32334 pci configuration registers 79rc32334/332 user reference manual 12 - 32 june 4, 2002 notes subsystem vendor id this read/write register identifies the vendor of the sub system where the pci device resides. figure 12.26 subsyste m vendor id register subsystem id this read/write register identifies the subsystem where the pci device resides. figure 12.27 subsystem id register interrupt line register the interrupt line register contains the interrupt line to which the cont roller core is currently connected. figure 12.28 interrupt line register interrupt pin register this register contains the inte rrupt pin that the device uses. figure 12.29 interrupt pin register bit description reset 15:0 subsystem vendor id 0000h table 12.36 subsystem vendor id field description bit description reset 31:16 subsystem id 0000h table 12.37 subsystem id field description bit description reset 7:0 identifies the interrupt line register to which the core is connected 00h table 12.38 interrupt line register field description subsystem vendor id 15 0 subsystem id 31 16 interrupt line register 7 0 interrupt pin register 15 8 pci interface controller rc32334 pci configuration registers 79rc32334/332 user reference manual 12 - 33 june 4, 2002 notes min_gnt register this register specifies how long a burst period the device needs. figure 12.30 min_gnt register max_lat register this register specifies how often the device needs to gain access to the pci bus. figure 12.31 max_lat register trdy timeout value this register sets the length of time in pci clocks t hat the controller core, as master, will wait for trdy. note: if this register is set to 0, the number of clocks that the master waits for trdy timeout is infinite. figure 12.32 trdy timeout value register bit description reset 15:8 identifies which interrupt pin the device uses 00h table 12.39 interrupt pin register field description bit description reset 23:16 identifies length of burst period, assuming a 33 mhz clock. units are 0.25 s. 00h table 12.40 min_gnt register field description bit description reset 31:24 sets value of max_lat. see pci 2.1 specification section 6.2.4 for details. units are 0.25 s. 00h table 12.41 max_lat register field description bit description reset 7:0 sets number of pci clocks that core as master will wait for trdy. the setting must be greater than or equal to 16. settings of 15-0 are reserved. 80h table 12.42 trdy timeout value field description min_gnt register 23 16 max_lat register 31 24 trdy timeout value 7 0 pci interface controller rc32334 pci configuration registers 79rc32334/332 user reference manual 12 - 34 june 4, 2002 notes retry timeout value this register sets the maximum number of times the c ontroller, as master, will retry. if the retry timeout value is reached, a pci master read or write error inte rrupt will occur in pci controller interrupt pending register 11, bit 1 or bit 0. the combined value (in nsec) of the retry timeout multiplied by trdy timeout must be smaller than the ipbus timeout value (in nsec). this ensures that pci fifo?s are properly re-aligned on timeout errors. for additional information, refer to the buserror address register section in chapter 8 and the base address register 5 (tabl e 16.7) in chapter 16. figure 12.33 retry timeout register for pci systems capable of stopping the clock, the cpu bus timeout, ipbus timeout, and the watchdog timeout timers must be disabled, so that t he pci clock can be restarted after an arbitrary delay. alternatively, if the system design al lows, the cpu could be signalled to not issue pci master transactions or a pci reset could be issued when the pci clock is stopped. such a si gnal or reset would allow the cpu to continue operation while the pci clock is stopped. on pci master write errors, the dma engine is dec oupled from the pci interface via a master write fifo. for example, if the pci master write error oc curs due to a trdy/retry timeout, the pci write fifo is then flushed so that pending writes can be abor ted. however, the dma engine may have stored or continue to store additional writes afte r the initial error. thus, in general, the pci master write error inter- rupt service routine should note the pci error and, if appropriate, restart the dma engine from the point of the error. bit description reset 15:8 sets number of retries that the core as master will perform. 1 1. for example, assume 133mhz cpu, 33mhz pci, and 1/2 system clock. if trdy timeout = 40 nsec and retry timeout = 40 nsec, then pci timeout = 124 sec. and i pbus timeouts should be great er than (124 sec * 133mhz / 2) which should be greater than 2079h. note that the cpu and ipbus timers use the ipbus system clock which is typically 1/2 the frequency of the cpu pipeline clock. 80h table 12.43 retry timeout value field description retry timeout value 15 8 notes 79rc32334/332 user reference manual 13 - 1 june 4, 2002 chapter 13 dma controllers introduction four general purpose dma channels move data bet ween source and destination resources such as system memory, pci or external i/o devices (8-,16-,or 32-bit i/o devices are treated as memory-mapped word-aligned devices). using a flexible, memory-based de scriptor structure, any of the four channels effi- ciently support ?scatter/gather? capability. the rc32334 dma supports byte, half-word (16-bit), word, and quad-word burst transfers that can cross over quad- word boundaries and are then automatically split into single-word transfers until a quad-word boundary is reached. the dma controller also automatically prevents burst transfers from crossing sdram page boundaries and suppor ts little- or big-endian data conversions. to initiate 1 a dma transfer, the cpu configures the status, source address, destination address and next descriptor address registers with the memory address, pci bus address, r ead-write transfer direction, boundary crossing points, end-of-transfe r interrupt enable, and transfer enable information. once config- ured, the controller arbitrates for the memory and pci bus and performs data transfers to or from memory without host cpu intervention. throughout this chapter, the followi ng terms are used as defined below: transfer ? refers to the cumulative data that is moved via the entire descriptor chain. transaction ? pertains to data that is transferred per descriptor block. list of features ? four general purpose dma channels ? flexible descriptor based operation ? memory-to-memory and memory-to-peripheral transfers ? supports quad-word burst transfer ? supports last partial word transfer ? supports endianness swapping ? programmable dma bus transaction bur st size (1, 2, 4 or 16 bytes) dma enhancements in y silicon revision the dma controller is one of the modules that has been enhanced in the y revision of the silicon. table 13.1 outlines some of the significant differences bet ween the z and y revisions. for more information on the differences between the silicon revisions, refer to application note an-350, rc32334/rc32332 differences between z and y revisions, and to the rc32334/rc32332 device errata, both posted on idt's web site at www.idt.com. 1.although any of rc32334?s four dma channels can be used for pci master initiator reads or writes, channels 2 and 3 are recommended, because of the presence of the optional dma_ready_n pins for channels 0 and 1. note that the rc32332 only includes the dma_ready_n signal for channel 0. dma controllers list of features 79rc32334/332 user reference manual 13 - 2 june 4, 2002 notes two new fields, shown in table 13.2, hav e been added to the configuration register. function z revision y revision comments readability of dma status registers not readable readable during active channel oper- ation provided this function is enabled. memory to pci transfer behavior bus requested immedi- ately when a memory controller has data to be transferred to the pci module internal bus only requested once pci master fifo has enough space to accept transfer. reduces lock ups of the inter- nal bus. priority of pci dma highest pr iority option to move this to lower priority level original user manual covering the z revision incorrectly stated that pci dma was con- figured for lowest priority. low- est priority level potentially useful for applications demanding high memory to memory performance but with relatively low pci bandwidth requirements. table 13.1 dma differences between z and y revisions bits field name description 29 new feature mode 20 sdram to pci arb algorithm sdram to pci arbitration algorithm table 13.2 new fields in dma configuration register value description 1 new feature mode: adds status register readabil- ity. 0 backward compatibility mode value description 1 sdram to pci write arbitration waits for 4 words free or 1 word free in pci master tx fifo depending on the burst size of the transfer. 0 backward compatibility mode (default). dma controllers block diagram 79rc32334/332 user reference manual 13 - 3 june 4, 2002 notes block diagram functional units of the dma dev ice are shown in figure 13.1. figure 13.1 diagram of dma general block with ip bus interface dma operations the rc32334 has four general purpose dma channels to transfer data between memory, i/o and pci. channels 2 and 3 are recommended for use of pci initiat ed read/write. 8/16/32 bit i/o devices are treated as memory mapped word aligned devices. the rc32334 dma supports byte, half-word (16-bi t), word, and quad-word burst transfer modes. quad-word burst transfers that cross over quad-word boundaries are automatically split into single word transfers till a quad-word boundary is reached. t he dma automatically prev ents burst transfers from crossing page boundaries. the flexible descriptor structure allows the dma contro ller to efficiently perform data transfers to or from memory without host cpu intervention. each dma channel has four registers to hold the current descriptor information. these are the status, source addres s, destination address and the next descriptor address registers. the functions of these registers are described later in the register definition section. to begin a dma transfer, the endmach bit (bit 31 of th e configuration register) must first be set to 1 and the base descriptor address register set to point to t he first descriptor of a chain of descriptors in memory. the last descriptor in this chain is a dummy and as such is not affiliated with any valid data, but it is required to aid in terminating the dma transfer. the status field of this dummy descriptor is set to 0, which sets the dmaown bit to 0. the dma loads the first descriptor from memory into its internal registers. t he data transferred from the source device in to an internal fifo and from this internal fifo to the destination device. a dma done interrupt can be generated. for this the user needs to set dmadnlnt bit to 1, (i.e., bit 27 of the status register) for each transaction to tell the host that the current transaction has completed. the dma will proceed to load the next descriptor via the address in the next descriptor address register to start a new transaction. this will continue until a dummy descriptor is detected in the chain. the dmaown bit informs the dma if the current de scriptor is a valid data transaction descriptor. the lastdesc bit (bit 28 of the status register) informs t he dma if the current descriptor is the last valid data descriptor. if the dma detects the dummy descriptor (i .e., when the dmaown bit is set to 0) the dma will exit. however, if the dma detects the dummy descrip tor and does not detect the last valid data descriptor beforehand, then the dma will still exit but will generate a dma_not_ow ner interrupt via the external interrupt_n[2] pin. please see figure 13.2 for a detailed diagram of a dma transfer configuration. the rc32334 dma internally supports byte swapp ing between little endian and big endian devices, which bridges the compatibility problems between two systems with differ ent endianness. the rc32334 dma supports last partial word accesses in any m ode by generating the appropriate byte enable signal for the last partial data. in this way, a transfe r of any byte length can occur in any dma mode. dma state machine dma register file dma fifo ip bus (8 words) dma controllers dma transfer modes 79rc32334/332 user reference manual 13 - 4 june 4, 2002 notes two dma modes (ready and done) are available for data transfer when access ing slow i/o devices. in the ready mode, when a slow i/o device is ready, the slow device asserts the dm a_ready_n pin (low active) to initiate the data transfer. in the done mode, when a slow i/o device is done, the slow device asserts the dma_ready_n pin to signal to the dma that the slow device is done receiving the current data. in both modes, the slow i/o device can keep the dma_ready_n pin de-asserted (high) if the slow device is not ready. this holds the dma engine in the current stat e and does not start a new data transfer. only dma channels 0 and 1 have the dma_ready_n pins, so only t hese channels may be used to transfer data to or from slow i/o devices. the dma module includes a option (enabled via bit 20 in the configuration register) to allow sdram to pci dma transfers to occur without locking up the in ternal bus. when enabled, t he bus is only requested once the pci master tx fifo has enough space to accept the transfer. this featur e is specifically designed to improve sdram to pci transfers. however the read operation may occur from any type of memory, including that located on the local bus. note that when this mode of operation is selected, the user must set up descriptors for that channel su ch that all destination addresses point to the memory space mapped to the pci master tx fifo. if incorrectly configured, unnec essary delays may occur, since the arbitration for that channel will always check the pci master tx fi fo status, without checking whether the destination address resides in the pci master tx fifo range or (for example) sdram memo ry. thus, for example, if the destination is sdram memory, the pci tx fifo may be full due to an independent access from the cpu or other dma channel. this would delay the sdram access, even though it is independent from the pci master tx transaction. endianness swapping the rc32334 dma internally supports byte sw apping between little-endi an and big-endian devices, which bridges the compatibility issues that oc cur between two systems with different endianness. the rc32334 dma supports last partial word accesses in any mode by generating the appropriate byte enable signal for the last partial data. in this way, a trans fer of any byte length can occur in any dma mode. the user must program the srcend bit (source e ndianness) and the dstend bit (destination endianness). examples of endianness swapping for word or half-word transfers are shown below. dma transfer modes for word/burst transfers (32<->32), the starti ng address must be word aligned. however, the rc32334 dma will complete unaligned transfers also (32<->32) by automatically converting to the byte transfer mode, independent of the word or the quad-word burst transfer settings. 1. byte transfers : used for non-word aligned transfers ? program maxburstsz = 000, 1 byte. ? both source and destination devices can have any starting address. depending on the address and endianness, the data will show up on the proper byte lanes. ? for each transfer, the dma will request the bus, r ead one byte from the source into internal fifo, write that byte from internal fifo to the destinat ion, then release the bus. the dma will repeat this procedure until all the data are transferred. 31...24 23...16 15...8 7...0 big endian abcd little endian dcba 31....................................16 15.....................................0 big endian b a d c little endian d c b a dma controllers dma transfer modes 79rc32334/332 user reference manual 13 - 5 june 4, 2002 notes 2. half-word transfers : typically used for data that ar e represented as a 16-bit integer ? program maxburstsz = 001, 2 bytes. ? both source and destination starting addresses must be half-word aligned. depending on the address and endianness (must be 32 bits wide), the dat a will show up in the proper byte lanes. ? for each transfer, the dma will request the bus, read one half-word from the source into an internal fifo, write that half-word from this internal fifo to the destination, then release the bus. the dma will repeat this procedure until all the data are transferred. ? if the last data is one byte only, the dma will generate the appropriate byte enable signal for that byte. 3. word transfers with word-aligned starting address ? program maxburstsz = 010, 4 bytes. ? both source and destination have word-aligned starting addresses. ? for each transfer, the dma will request the bus, r ead one word from the source into internal fifo, write that word from this internal fifo to the des tination, then release the bus. the dma repeats this procedure until all the data are transferred. ? if the last data is a partial word, the dma will generate the appropriate byte enable signal for that partial word. 4. quad-word burst transfers with word-aligned starting address ? program maxburstsz = 100, 16 bytes. ? both source and destination starting addresses are word-aligned and not decremented. ? for burst transfer, the dma will request the bus, r ead four words from the source into an internal fifo, write four words from this internal fifo to the destination, then rel ease the bus. the dma will repeat this procedure until all the data are transferred. ? if either the source or the destination starti ng address is not at a quad-word boundary, then the dma will read or write single words until the address reaches a quad-word boundary. then the dma will start quad-word burst transfers. ? if the last data is a partial word, the dma will generate the appropriate byte enable signal for that partial word. 5. unaligned word/burst transfers ? the dma will automatically detect unaligned tr ansfers and ignore the user-programmed max- burstsz and degrade the dma transfer into the byte mode transfer. ? for each transaction, the dma will request the bus, r ead one byte from the source into an internal fifo, write that byte from this internal fifo to the destination, then release the bus. the dma will repeat this procedure until the data are transferred. dma transfer operations a dma sequence begins after the dma channel has been enabled via its configuration register. the dma engine begins by accessing the ba se descriptor register to loca te the physical address pointer for the first descriptor, which consists of 4 words and is usually located in a large memory buffer. each descriptor has four fiel ds. fields one and two describe the status and source address that are to be read. fields three and four describe the destination addr ess that are to be written and the next descriptor pointer. descriptors are often located one after another; howev er, because each descriptor contains a full 32-bit pointer in the next descriptor address register, they can be located anywhere in memory on a quad-word aligned boundary. the next descriptor address register points to the memory location from which the next descriptor is to be fetched. the dma engine then uses the base descriptor to fetch (read) the first descriptor. thus, a 4-word burst r ead of the descriptor will occur. dma controllers dma transfer modes 79rc32334/332 user reference manual 13 - 6 june 4, 2002 notes note that the bus turnaround on the physical syste m data bus after a descriptor fetch is hardcoded to 1.0 clock. thus, descriptor memory tables should be se t up in physical memory that uses 1.0 clock bta or less. once the first descriptor is fetched, the dma engine arbitrates for the system data bus; when granted, the dma engine executes a read to the source address as pointed to by the descriptor. a write is then immediately issued to the destination address, as pointed to by the descriptor. the dma engine continues to request/grant/read/write until its status indicates that the transaction is complete. when the dma engine completes the request/grant/read/write loop for a descripto r, then the status is written back to the status word within the descriptor?s 4-word memory locati on. if more descriptors ar e pending, then the dma engine uses the next descriptor address register to fetch the next descripto r from memory, via a burst 4-word read. a diagram of the dma tr ansfer configuration details is provided in figure 13.2. the dma engine is often instructed by the descriptor chains to endlessly loop through the descriptor pool. one exception is to run out of descriptors ?o wned? by the controller; fo r example, to run out of memory buffers. in this case, after fetching the nex t descriptor, the dma engi ne examines the previous ?lastdesc? status bit and ends/disables if ?lastdesc? is set to?1.? this method is also the typical way to end a fixed-size chain of descriptors, such that the dma engine fetches one extra dummy descriptor with the dma own status bit set to the cpu. a second exception is to fetch a controller owned descrip tor with the ?lastdesc? status bit set to ?0?, to indicate an unexpected last condition such that a ?lastd esc? interrupt is generated. in this case, dma may be restarted/re-enabled with the ?c ontinuation? control set by the in terrupt handler when a descriptor becomes available, such that a new descriptor is re-fetched from the ne xt descriptor address register. this optional restart feature allows software to maintain the dma channels with a base descriptor address as a constant, if desired. figure 13.2 dma transfer configuration rc32334 dma chan nel 1 registers configuration : b10xx_xxxx_xxxx_xxxx base descriptor address: 0x100 status: 0x8xxx 0x100 0x104 source address destination address next descriptor address: 0x120 0x108 0x10c transfer #1 0x120 0x124 0x128 0x12c status: 0x8xxx source address destination address next descriptor address: y . . . status : 0x9xxx dummy descriptor dma transaction done status: 0x0xxx source address destination address next descriptor address: z 0x200 0x204 0x208 0x20c next descriptor address: 0x200 source address destination address transfer #2 transfer #n x x x x last dma transfer dma controllers dma arbitration methods 79rc32334/332 user reference manual 13 - 7 june 4, 2002 notes last partial word transfers for word or burst transfers , if the last data is a partial word (for example, 1, 2 or 3 bytes), the dma will always read the data from the low address of the source and write it to the low address of the destination, if the address is incremented (or high address if the addre ss is decremented). for example, if the last transfer is one byte and the address is incremented, the last byte will show up on the following byte lane: for half-word transfers , if the last data is a byte, the dma will always read the last byte from the low address (in little endian order) of t he source and write it to the low address (in little endian order) of the destination. for example, if a1 is 0, the last byte will show up on the following byte lane: if a1 is 1, the last byte will show up on the following byte lane: transfer restrictions when implementing dma operations, the followi ng transfer restrictions must be considered: ? when the source or destination address is a const ant (such as in i/o devices), the address must be word-aligned, and the i/o devices must be connected to the appropriate byte lanes according to endianness ? the following transfers are not supported: ? (1) source is incremented and destination is decremented ? (2) source is decremented and destination is incremented ? unaligned word/burst transfers can only be done in byte mode (user-programmed maxburstsz is ignored for unaligned word/burst transfer) ? when an address is decremented or constant, the dma will not support burst transfers ? the starting address must be half-word aligned for half-word transfers ? devices must have the same port width when doing dma transfers from i/o to i/o ? dma channels 2 and 3 do not have the dma_ready_n pi ns, therefore they can not be used to do dma transfers with slow i/o devices. dma arbitration methods the rc32334?s four independent dma channe ls are functionally identical?w ith the exception of priority coding?and initialized with a set of chaining register s to determine the dma sour ce start base address, the dma target start base address, the data transfe r number, and the protocol style selection. as discussed earlier in the transfer operations secti on of this chapter, to begin a data transfer operation, the channel will first arbitrate for the system data bus. with multiple dma requests pending, after a dma access, the system data bus is granted to the cont roller instead of the next highest requestor; as such, there are two priority tiers: bus re questors and controller. if dma receives the bus, the dma will use either the fixed or rotating priority schemes. 1 the rotating arbitration scheme is illustrated in figure 13.3. 31...24 23...16 15...8 7...0 big endian little endian a a 31...24 23...16 15...8 7...0 big endian little endian a a 31...24 23...16 15...8 7...0 big endian little endian a a dma controllers dma arbitration methods 79rc32334/332 user reference manual 13 - 8 june 4, 2002 notes figure 13.3 diagram showing the rotating arbitration scheme the fixed priority encoding scheme is illustrated in table 13.3. once arbitration is settled, the dma channel generates a read cycle with the source base address. the control register determines whether it is a burst. typically, the sour ce address will be through an internal memory controller, which will take the address and generate data, acknowledges, etc., back to the dma controller channel. the dma controller uses the dma 4-word deep buffer fifo to absorb the potential burst read data. after the read is completed, the dma channel initiate s a write to the target address by emptying the read buffer fifo. as in the read, the write is typically th rough an internal memory controller on the i/o controller. this internal memory controller takes the addre ss and data from the dma fifo and generates a write transaction. at the end of the transaction, the dma c hannel's block size register is decremented by the transaction length. if the block size register has not reached 0, the source and target addresses are incremented to their next value (which could be by +0, +1, +2, +4, or +16, depending on whether incrementing is enabled and whether a mini-burst or burst occu rred). if the block size register has reached 0, then the dma channel is finished with its current descriptor link chaining register assignment and t he status word is written back to the memory descriptor. if the control register so in structs, the channel may set an interrupt and/or stop, and/or it may reload a new descriptor of chaining r egisters. if a new descriptor is loaded, then the dma channel will repeat the basic dma channel transaction by copying the new des criptor?s instructions into the current instructions and then executing them. 1.dram refreshes occur in the background and may override an access to dram by delaying the start of the access. fixed priority agent highest biu ?pci ?dma0 ?dma1 ?dma2 lowest dma3 table 13.3 fixed priority encoding controller dma3 dma2 dma1 dma0 biu pci dma controllers signal definitions 79rc32334/332 user reference manual 13 - 9 june 4, 2002 notes bus turnaround (bta) clock cycles wi ll only be inserted if the dma wr ite after a read is going to take less than the bta value programmed. see bus interfac e unit register descriptions for more information. dma access on a dma access that results in an ipbus error, such as to a non-existent pci target, the biu arbiter behavior is changed to more gracefully generate an ipbus timeout rather than a watchdog timeout. signal definitions two modes are available to the user for completi ng data transfers to or from slow i/o devices: dma_done_n and dma_ready_n 1 . dma ready the rc32334 dma controller has a dma throttling option called dma ready. the dma ready option is typically used for one of several cases: ? external read i/o device where overall data rate is much slower than cpu, such that occasional reads are done in the process background on a request demand basis ? external write i/o device where ov erall data rate is much slower than cpu, such that occasional reads are done in the process background on a request demand basis ? external read i/o fifo device t hat has fifo almost full flag ? external write i/o fifo device that has fifo almost full flag. the dma_ready_n input signal can be used by an ex ternal i/o device to demand that the rc32334 dma controller initiate one transfer of data to or from the i/o device. dma_ready_n[0] can be used to control dma channel 0, and dma_ready_n[1] can be used to control dma channel 1. note: on the rc32332, there is one flow cont rol signal, dma_ready_n[0] for dma channel 0. dma_ready_n is first sampled 1.0 clock after the fourth/last debug_cpu_ack_n asserts from the dma channel descriptor fetch. this is similar to figure 13.4, except that the transaction is a four-word burst read. dma_ready_n can be a 1.0 clock pulse , or it can be asserted longer, as long as it is de-asserted (if it is intended to be de-asserted) before the next dma_ready_n sampling point for the next dma transfer. if dma_ready is kept asserted at this sampling point, then the dma controller will assume that the next transfer is to occur (as might be the case if t he external i/o device is a fifo device that keeps dma_ready_n asserted until empty). as shown in figure 13.4, the next dma_ready_n sampli ng point first occurs on the clock after write debug_cpu_ack_n occurs for the current dma transaction write. note that if the transaction has multiple data, then the sampling point is after the last data. whether or not the external i/o device is reading or writing (source or destination), the sampling always occurs after the read portion of the dma transaction and the write portion have both occurred. after the sampling point occurs, if dma_ready_n is not asserted, then the dma controller will pause on that channel until dma_ready_n is asserted. finally, after being sampled, dma_ready_n is internally double registered. thus the nex t dma transaction cannot possibly occur until at least 2.0 cloc ks after dma_ready_n is asserted. 1.as noted under dma restrictions, only dma channels 0 and 1 have the dma_ready_n pin, making these two channels the only dma channels available for this type of data transfer. channels 2 and 3 are restricted from this type of dma transfer operation. the rc32332 only includes the dma_ready_n pin for dma channel 0. dma controllers signal definitions 79rc32334/332 user reference manual 13 - 10 june 4, 2002 notes figure 13.4 dma ready sampling point figure 13.4 shows the end of a dma transaction, where the read port ion has already occurred and the write portion is occurring via the 32-bi t memory controller location. note that the sdram controller, as well as the other modes of the memory controller, have similar cases relative to the final assertion of debug_cpu_ack_n. the first possible poi nt at which dma_ready_n is sampled to initiate another dma trans- action occurs 1.0 clock after debug_cpu_ack_n occurs. note that if the enable dma channel bit in the cha nnel configuration register is disabled during a burst transfer where dma_ready_n is being us ed, the burst transfer may abort the writeback of words from the dma fifo if the write is not block aligned. if the enable dma channel is to be used (to disable the channel) in conjunction with the dma_ready_n mode, the transfe r address should be aligned with the maxburstsz so that the final writes are flushed to memory. dma done dma done mode uses the dma_ready_n pin. the dma channel configur ation register bit 27, dmadone bit turns this mode on or off. block devices which in itially request or send more data than may be necessary can benefit from the use of the dma done mode. dma pin type function dma_ready_n[1:0] input dma_ready mode: input pins for dma channels 0 and 1 to indicate that the i/o device is ready for the next data in the current dma descriptor transaction dma_done_n[1:0] input dma_done mode: input pins for dma channels 0 and 1 to indicate that the i/o device is finished with the current descriptor transaction table 13.4 dma signal pins and definitions 1 2 3 4 5 6 7 8 9 10 40000 next dma transaction 1fc00004 abcd0000 next dma transaction 1111 0000 1111 tp tp tp tp tp tp tp tp tp tp tp tp tp tp thld tsu thld tsu cpu_masterclk dma_ready_n[x] debug_cpu_ack_n mem_addr[25:2]<<2 mem_data[31:0] mem_cs_n[0] mem_oe_n mem_we_n[3:0] cpu_dt_r_n mem_245_oe_n mem_wait_n dma controllers signal definitions 79rc32334/332 user reference manual 13 - 11 june 4, 2002 notes the dma done mode allows the dma_done_n pin to abort and disable the dma channel either: ? at the end of the current dma bus transaction or ? at the end of the next dma bus transaction. dma channel interrupt #3 is asserted and an interr upt service routine can setup and re-enable the dma channel as desired. the dma_done_n pin is required to be asserted for at le ast one clock cycle. it is internally synchronized by double clocking to help avoid meta stability issues if asserted asyn chronously. as shown in figure 13.5, at the end of clock state cycle #11, dma_done_n is sa mpled by each dma bus transaction exactly 5.0 clocks previous to the final internal cpu_a ck_n signal which can be seen on the rc32334 as the debug_cpu_ack_n signal. both single data and burst accesses sample the dma_done_n signal 5.0 clocks previous to the final debug_cpu_ack_n of the read/writ eback phase. for example, in a 4 word burst dma bus transaction, the final debug_cpu_ack_n is the 8th ack, which occurs after the 4 word dma read ack's, on the 4th word of the dma writeback. if the dma_done_n pin is asserted after the dma_done_n internal sample point, then the dma channel will cease after the next dma bus transaction from this dma channel. the next dma bus transaction address cycle which can be started from the same dm a channel will take at least 11.0 clocks from the previous dma_done_n internal sample point. the dma channel interrupt #3 for the dma_done_n pi n occurs concurrently with the final debug_cpu_ack_n assertion and will occur whether or not the dma channel coincidently ends because of the descriptor finishing normally. note that interrupt #3 is different from the dma done interrupt as setup by the descriptor status field which typically is used to denote the end of a normal descriptor finish. after the interrupt for the dma_done_n pin occurs, an in terrupt service routine can setup or reuse a new descriptor and restart the dma channel by re-enabling it. figure 13.5 dma done timing diagram internal dma interrupt signals each of the four dma channels has 3 interrupts that are routed to the expansion interrupt controller, which provides the logic for softw are to analyze the various interrupts generated by the overall system. these internal interrupts perform the functions de scribed in table 13.5. more details on the expansion interrupt controller are provi ded in chapter 14 of this manual. internal dma interrupt pin type function interrupt_n[0] output dmadnint, dma done interrupt, which is generated at the end of each descriptor frame if the descriptor status register has the dmadnint interrupt bit 27 enabled. interrupt_n[1] output dma_end_early interrupt, which is caused by bus error or timeout. interrupt_n[2] output dma_not_owner interrupt, which is caused by the following situation: dmaown = 0 for current descriptor frame and lastdesc = 0 for the previous descriptor frame. table 13.5 dma interrupt definitions (part 1 of 2) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1f000004 dma read data 000 01004 dma writeback data next bus transaction thld tsu cpu_masterclk dma_done_n[x] (dma_ready_n[x]) debug_cpu_ack_n mem_data[31:0] cpu_int_n[3] (internal signal) dma controllers register mapping and descriptions 79rc32334/332 user reference manual 13 - 12 june 4, 2002 notes restarting dma channels dma channels are restarted by re-enabling the en dmach field in the dma channel configuration register after this field has been cleared by the dma engine. an idle dma channel can be detected using one of the following methods: 1. use the dma_clr_en interrupt. after the interrup t occurs, clear the interrupt and re-enable the dma channel. after the interrupt occurs, clear the interrupt and re-enable the dma channel. 2. program dma done interrupt to occur on the las t descriptor. then clear the interrupt and wait until the dummy descriptor is fetched before re-enabli ng the dma channel. usually, the interrupt handler has sufficient delay for the dummy descriptor to be fetched. alternatively, the dma channel?s config- uration register (or any other dma channel register) can be poll ed (if any of the fields beside the configuration register?s endmach field were init ially set to non-zero) because the registers return zeroes until the dummy descriptor fetch is fini shed. if the dma configuration register?s new feature field is set, the endmach field (in the configuration regist er) itself can be polled to detect if the dummy descriptor fetch is finished. 3. program the last descriptor to not have the last desc field set. the dummy descriptor will be fetched and dma_not_owner interrupt will occur. from c ontext, if the descriptors are not added dynamically, or if the interrupt does not occur immediately after a descriptor is added dynamically, the interrupt can be cleared, and the dma channel can be re -enabled using the configuration register?s endmach field. note that, if applicable, in the inte rrupt after a dynamic descriptor case, either of the following may occur: ? update (if necessary) the next descriptor r egister and set the configuration register cont field ? update the base descriptor register and set the configuration register cont field. then, the interrupt can be cleared and the dma channel can be re-enabled using the configura- tion register?s endmach field. register mapping and descriptions each of the four dma channel?s control register s determines channel usage, data transfer modes, and descriptor ownership of the four independent, gener al purpose channels. as pr ogrammed, these channels move data between source and destination ports, such as system memory, pci, or external i/o devices. for the address mapping tables listed in this section, t he effective address for a specific set of registers for that channel is the base address plus the offs et, as indicated in the tables that follow. interrupt_n[3] output dma done pin asserted when in the dma_ready_n pin?s dma_done mode and dma_done_n is asserted and once the current dma transaction completes. still asserted even if the channel completes simultaneously or if the channel is dis- abled. interrupt_n[4] output dma halt asserts dma interrupt bit 4 when the dma channel completes all descriptor frames, including the flushing of the fifo of a final transfer and the dummy descriptor fetch. this interrupt is also asserted when the enable dma- channel bit in the dma channel configuration register is cleared while the chan- nel is active and allows software to monitor when the channel has completed its current transfer. internal dma interrupt pin type function table 13.5 dma interrupt definitions (part 2 of 2) dma controllers register mapping and descriptions 79rc32334/332 user reference manual 13 - 13 june 4, 2002 notes base address channel 0 register name offset address effective address channel 0 1800_1400 configuration register 00 base + offset base descriptor register 04 current address register 08 status/block size register 10 source address register 14 destination address register 18 next descriptor address register 1c table 13.6 dma channel 0 register address map base address channel 1 register name offset address effective address channel 1 1800_1440 configuration register 00 base + offset base descriptor register 04 current address register 08 status/block size register 10 source address register 14 destination address register 18 next descriptor address register 1c table 13.7 dma channel 1 register address map base address channel 2 register name offset address effective address channel 2 1800_1900 configuration register 00 base + offset base descriptor register 04 current address register 08 status/block size register 10 source address register 14 destination address register 18 next descriptor address register 1c table 13.8 dma channel 2 register address map dma controllers configuration register 79rc32334/332 user reference manual 13 - 14 june 4, 2002 notes configuration register the configuration register is a 32-bit register containing the data used to implement and manage dma controller functions, as shown in table 13.10. when set to 1, bit 31 of this register is used to enable a dma channel after the descriptor information and address hav e been established. once initiated, dma transfers can only be disabled after the current transaction is complete. when the dma channel is active, this register reads as 0. on dma channels 0 and 1, the dma done (bit 27) and dm a ready (bit 28) modes are available for data transfers from slow i/o devices. in the ready mode, once a slow i/o dev ice is ready to begin a data transfer, the i/o device will set the dma_ready_n pin, which initia tes the transfer. in the done mode, the slow device asserts the dma_ready_n pin to signal the dma that the slow device is done receiving the data. in both modes the slow device can hold the dma_ready_n pin high if the device is not ready, which holds the dma engine in the current state and a new data transfe r is not initiated. note that if the dma transfers are to be modulated using the dma_ready_n pin, with the dma enable bit in t he configuration register disabled, burst transfers s hould be word (4 bytes) sized. figure 13.6 illustrates the fields of the configura- tion register and table 13.10 provides the des cription and initial value of those fields. the dma status registers are readable during ac tive channel operation whenever the new feature mode is turned on. figure 13.6 configuration register fields base address channel 3 register name offset address effective address channel 3 1800_1940 configuration register 00 base + offset base descriptor register 04 current address register 08 status/block size register 10 source address register 14 destination address register 18 next descriptor address register 1c table 13.9 dma channel 3 register address map bits field name description initial value 31 endmach enable dma channel used to enable a dma channel after descriptor information and address is set up. note: this bit is not normally cleared (dma disabled) by the user after a dma transfer has started. usually, the dma engin e itself will clear this bit after the transaction has been completed. 0 table 13.10 configuration register field descriptions (part 1 of 3) reserved maxburstsz dma done dma rdy new cont endmach 31 30 29 28 27 26 24 23 20 0 feature reserved 21 sdram to pci arb 19 value description 1 enable dma channel 0 dma channel is idle dma controllers configuration register 79rc32334/332 user reference manual 13 - 15 june 4, 2002 notes 30 cont continuation after a dma transfer failure, this bit specifies which descriptor to restart the trans- fer from. 0 29 new feature mode 0 28 dmardy dma ready external pin wait for dma_ready_n input (in ready mode). wait for the dma_ready_n input before the next bus arbitration. do not assert bits 28 and 27 simultaneously, since it will lead to undefined behavior. 0 27 dmadone dma done external pin wait for dma_ready_n input (in done mode). put the dma_ready_n pin into dma_done_n mode. if asserted, dma_done_n will stop the dma channel immediately after the current dma bus transaction com- pletes and disable the dma channel (also see endmach bit 31). if the dma channel is waiting for bus mastership, then asserting dma_done_n will stop the dma channel immediately after the next dma bus transaction completes and disable the dma channel. do not assert bits 28 and 27 simultaneously, since it will lead to undefined behavior 0 bits field name description initial value table 13.10 configuration register field descriptions (part 2 of 3) value description 1 restart from failed descriptor 0 restart from the first descriptor value description 1 new feature mode: adds status register readability. 0 backward compatibility mode. value description 1 enable dma_ready_n pin (in ready mode) 0 ignore dma_ready_pin (in ready mode) value description 1 enable dma_ready_n pin (in done mode) 0 ignore dma_ready_pin (in done mode) dma controllers base descriptor address register 79rc32334/332 user reference manual 13 - 16 june 4, 2002 notes base descriptor address register this 32-bit register is used in c onjunction with bit 31 of the configur ation register, to initiate a dma transfer. however, before a dma transaction can begin, the base descriptor address register must be set to point to the physical address of the first descriptor in a chain of descriptors in memory. the base address does not change after the transfer has started. when th e dma channel is active, th is register reads as 0. fields of the base descriptor address register are shown in figure 13.7. fields of this register are described in table 13.11. figure 13.7 base descriptor address register field 26:24 maxburstsz maximum burst transaction size bit field 000 23:21 reserved 0 20 sdram to pci arb algo- rithm sdram to pci arbitration algorithm note: for pci master write transactions only, this field should be enabled. for all other types of transactions, such as memory to memory transactions or pci mas- ter read transactions, this field should be disabled. 19:0 reserved 0 bits field name description initial value table 13.10 configuration register field descriptions (part 3 of 3) value description 111 reserved 110 reserved 101 reserved 100 16 bytes 011 reserved 010 4 bytes 001 2 bytes 000 1 byte value description 1 sdram to pci write arbitration waits for 4 words free or 1 word free in pci master tx fifo depending on the burst size of the transfer. 0 backward compatibility mode (default). base descriptor address 31 0 dma controllers base descriptor address register 79rc32334/332 user reference manual 13 - 17 june 4, 2002 notes dma example /* use dma channel 0 to read/write 3 words, 1 word at a time to/from sram memory buffer a, to/from sram memory buffer b, and from buffer b to sram memory buffer c. */ /* algorithm: 1. setup dma command registers 2. initialize descriptors 2.1. initialize descriptors 2.2. initialize dummy descriptor 3. setup interrupt controller 4. enable dma 5. wait for dma done interrupt */ /* 1. setup dma command registers */ $display($stime,": cpu 32bit 1wd write to dma config reg"); // address data be cpu_wr_1wd('h1800_1400, `dwidth'h0000_0000, `bwidth'h0); $display($stime,": cpu 32bit 1wd write to dma base desc reg"); // address data be cpu_wr_1wd('h1800_1404, `dwidth'h1fc0_0200, `bwidth'h0); /* 2.1. initialize descriptor 0 */ $display($stime,": cpu 32bit 1wd write to mem0: desc.0.0 (status)"); // address data be // dmaown bit31 needs to be set to dma, no dmadnint bit27 // read/write 1 wd at a time for 3 wds cpu_wr_1wd('h1f c0_0200, `dwidth'h8000_000c, `bwidth'h0); $display($stime,": cpu 32bit 1w d wr to mem0: descriptor.0.1 (source)"); // address data be cpu_wr_1wd('h1fc 0_0204, `dwidth'h1fc0_0100, `bwidth'h0); $display($stime,": cpu 32bit 1w d wr to mem0: descriptor.0.2 (dest)"); // address data be cpu_wr_1wd('h1fc 0_0208, `dwidth'h1fc0_0600, `bwidth'h0); $display($stime,": cpu 32bit 1w d wr to mem0: descriptor.0.3 (next)"); bits field name description 31:0 base descriptor address used in conjunction with bit 31 of the configuration regis- ter, this quad-word boundary physical address pointer points to the first descriptor of a chain of descriptors in memory table 13.11 base descriptor address field description dma controllers base descriptor address register 79rc32334/332 user reference manual 13 - 18 june 4, 2002 notes // address data be cpu_wr_1wd('h1fc 0_020c, `dwidth'h1fc0_0210, `bwidth'h0); /* 2.2. initialize descriptor 1:last */ $display($stime,": cpu 32bit 1wd write to mem0: desc.1.0 (status)"); // address data be // dmaown bit31 needs to be set to dma, dmadnint bit27 // dma lastdesc bit 28 needs to be set // dma dnint bit 27 optionally set // read/write 1 wd at a time for 3 wds cpu_wr_1wd('h1f c0_0210, `dwidth'h9800_000c, `bwidth'h0); $display($stime,": cpu 32bit 1w d wr to mem0: descriptor.1.1 (source)"); // address data be cpu_wr_1wd('h1fc 0_0214, `dwidth'h1fc0_0600, `bwidth'h0); $display($stime,": cpu 32bit 1w d wr to mem0: descriptor.1.2 (dest)"); // address data be cpu_wr_1wd('h1fc 0_0218, `dwidth'h1fc0_1000, `bwidth'h0); $display($stime,": cpu 32bit 1w d wr to mem0: descriptor.1.3 (next)"); // address data be cpu_wr_1wd('h1fc 0_021c, `dwidth'h1fc0_0260, `bwidth'h0); /* 2.3. initialize dummy descriptor */ $display($stime,": cpu 32bit 1wd write to mem0: desc.0.0 (status)"); // address data be // dmaown bit31 needs to be set to cpu cpu_wr_1wd('h1f c0_0260, `dwidth'h0000_0000, `bwidth'h0); $display($stime,": cpu 32bit 1w d wr to mem0: descriptor.0.1 (source)"); // address data be cpu_wr_1wd('h1fc0_0264, `dwidth'hffff_ffff, `bwidth'h0); $display($stime,": cpu 32bit 1w d wr to mem0: descriptor.0.2 (dest)"); // address data be cpu_wr_1wd('h1fc0_0268, `dwidth'hffff_ffff, `bwidth'h0); $display($stime,": cpu 32bit 1w d wr to mem0: descriptor.0.3 (next)"); // address data be cpu_wr_1wd('h1fc0_026c , `dwidth'hffff_ffff, `bwidth'h0); /* 3. setup interrupt controller */ $display($stime,": cp u 32bit 1wd write to int clear reg"); // address data be cpu_wr_1wd('h1800_0578, `dwidth'hffff_ffff, `bwidth'h0); #(10.0*`clk_period+000); // align for next transaction; dma controllers current address register 79rc32334/332 user reference manual 13 - 19 june 4, 2002 notes $display($stime,": cp u 32bit 1wd write to int mask reg"); // address data be cpu_wr_1wd('h1800_0574, `dwidth'h0000_0001, `bwidth'h0); /* 4. enable dma */ $display($stime,": cpu 32bit 1wd write to dma config reg"); // address data be // 1 wd at a time cpu_wr_1wd('h1800_1400, `dwidth'h8200_0000, `bwidth'h0); current address register this 32-bit register is managed by the dma and c ontains the physical address of the descriptor in memory associated with the current transaction. when t he dma channel is active, th is register reads as 0. figure 13.8 next descriptor address field source address register this 32-bit register contains the physical address of the memory location from which the next data is to be read. figure 13.9 and table 13.13 describe and illustrate t he fields of this register . this register is inter- nally updated after each dma read transfer. however, the register can only be accessed by software when the dma channel is idle. when the dma channel is active, this register reads as 0. figure 13.9 source address field destination address register this 32-bit register contains the physical address of the memory location where data is to be written. fields of the destination register are illustrated and described in figur e 13.10 and table 13.14. this register is internally updated after each dma read transfer. howe ver, the register can only be accessed by software when the dma channel is idle. when the dma channel is active, this register reads as 0. bits field name description 31:0 current descriptor address quad-word boundary physical address pointer points to the current descriptor in the chain of descriptors table 13.12 current descriptor address field description bits field name description 31:0 source address points to the next physical address to be read table 13.13 source address register field description current descriptor address 31 0 source address 31 0 dma controllers next descriptor address register 79rc32334/332 user reference manual 13 - 20 june 4, 2002 notes figure 13.10 destin ation address fields next descriptor address register this 32-bit register contains the physical address of the descriptor in memory that is next in line to be operated on. this register is illustrated and descr ibed in figure 13.11 and table 13.15. when the dma channel is active, this register reads as 0. figure 13.11 next descriptor address field status register each descriptor of 4 words contains a status register that is subdivided into 11 fields, which are illus- trated in figure 13.12 and described in table 13.16. this register is internally updated after each dma read transfer. however, the register can only be access ed by software when the dma channel is idle. when the dma channel is active, this register reads as 0. figure 13.12 status register fields bits field name description 31:0 destination address points to the next physical address to be written to table 13.14 destination address field description bits field name description 31:0 next descriptor address quad-word boundary physical address pointer points to the next descriptor in the chain of descriptors table 13.15 next descriptor address field description bits field name description initial value 31 dmaown dma is owner 0 table 13.16 status register (part 1 of 3) destination address 31 0 next descriptor address 31 0 dmaown errdesown errbusto last desc dmadnint indesrc dstend reserved blocksize srcend indedst 31 30 29 28 27 26 25 24 23 22 21 20 16 15 0 value description 1 dma controller owns the current descriptor 0 the processor owns the current descriptor dma controllers status register 79rc32334/332 user reference manual 13 - 21 june 4, 2002 notes 30 errdes- own error on descriptor ownership (descriptor under flow) if dma does not own the current descriptor and the previous descriptor is not the last one, then this error bit is set in this register, but it is not writ- ten back to the descriptor in memory. 1 - error on the descriptor ownership 0 - no error 0 29 errbusto error due to bus error or timeout if a bus error or timeout occurs during a descriptor fetch, during a dma transaction, or during a descriptor write back, then this error bit is set. this register is not written back to the descriptor in memory. note that errors (for example, to undecoded memory space) during reads are always reported, but errors during writes may not be reported, espe- cially in cases where the write occurs to a write buffer (fifo). for exam- ple, pci master write errors may not necessarily report an error to dma, but will report a pci interface master abort error. 0 28 lastdesc last valid data descriptor this field indicates whether or not the descriptor is the last descriptor in the list of descriptors. if lastdesc is set and the next descriptor?s dmaown bit is not set, the dma channel terminates normally. if last- desc is not set and the next descrip tor?s dmaown bit is not set, the errdesown descriptor ownership error status bit will be set. if the next descriptor?s dmaown bit is set, the lastdesc bit is ignored. 0 27 dmadnint assert dma done interrupt this field generates an interrupt after all the transactions associated with the current descriptor are done. 0 26:25 indesrc increment/decrement source memory 0 bits field name description initial value table 13.16 status register (part 2 of 3) value description 1 bus error or bus timeout 0no error value description 1 is the last descriptor 0 is not the last descriptor value description 1 generate interrupt 0 do not generate interrupt value description 11 reserved 10 constant 01 decrement 00 increment dma controllers timing diagrams 79rc32334/332 user reference manual 13 - 22 june 4, 2002 notes timing diagrams figure 13.13 illustrates an entire dma transaction tr ansferring 2 words of memory to another memory location. the transaction begins with a bus request/grant assertion. t hen a 4-word burst read of the 1st descriptor is fetched. the bus r equest/grant is de-asserted. at this time, another dma channel or the controller could take over the system. note that the bus turnaround after the descriptor fetch is hardcoded to 1.0 clock. another bus request/grant assertion occurs. then the dma source read occurs, in this case 1 word. after the dma read, bus turnaround idle cycles occur. then the dma destination write occurs, in this case 1 word. another bus request/grant de-assertion occurs. at this time, another dma channel or the controller could take over the system bus. in cases were the l ength of the transaction and the burst size allow, a burst read and burst write may occur at this step. another bus request/grant assertion o ccurs. the dma read/write pair repeats. 24:23 indedst increment/decrement destination memory 00 22 srcend source endianness this field specifies endianness of the source/data/part/device. pci dma has endianness controlled via the pci bridge and will always swap pci from little-endian to big-endian. 0 21 dstend destination endianness this field specifies endianness of the destination part/device. pci dma has endianness controlled via the pci bridge. 0 20:16 reserved 0 15:0 blocksize block size this field specifies the number of bytes to be transferred in the current transaction descriptor. this field is internally updated after each dma write transfer. however, the field can only be accessed by software when the dma channel is idle. when the dma channel is active, this field reads as 0. the value ?0? is reserved and should not ordinarily be written to this field/descriptor if the descript or is intended for an actual transfer. the value ?0? will transfer 4 bytes rather than a zero length transfer of 0 bytes. 0 bits field name description initial value table 13.16 status register (part 3 of 3) value description 11 reserved 10 constant 01 decrement 00 increment value description 1big endian 0 little endian value description 1 big endian 0 little endian dma controllers timing diagrams 79rc32334/332 user reference manual 13 - 23 june 4, 2002 notes another bus request/grant assertion occurs. in this case, the length of the dma transfer is only 2 words, so the dma is complete. if more words were to be transferred, dma would co ntinue to loop through the dma read/write sequence until the transfer was complete . since dma has completed, a status writeback of 1 word occurs, writing 1 word back to the descriptor. another bus request/grant de-assertion occurs. at this time, another dma channel or the cont roller could take over the system. another bus request/grant assertion occurs. even if the current descriptor is the last valid descriptor, one more ?dummy? descriptor burst read fetch occurs in order to support descriptor memory buffer underflow algorithms. another bus request/gr ant e-assertion occurs. at this time, another dma channel or the controller could take over the system bus. figure 13.13 two word sram to sram access by dma descriptor 0 fetch cpu arb dma read 1 of 2 dma bta cpu arb dma read 2 of 2 dma bta dma write 2 of 2 cpu arb dma status write cpu arb descriptor 1 fetch cpu arb 98000008 001234500 01234500 01234504 01234504 18000000 10000000 fffffffff 000000 40020c 000000 400100 400180 000000 400104 400184 000000 400200 000000 400210 40021c 000000 b1111 b0000 b1111 b0000 b1111 b0000 b1111 cpu_masterclk mem_data[31:0] (internal cpu_int_n[3]) mem_addr[25:2]<<2 mem_cs_n[0] mem_oe_n mem_we_n[3:0] cpu_dt_r_n mem_245_oe_n mem_wait_n dma write 1 of 2 dma controllers timing diagrams 79rc32334/332 user reference manual 13 - 24 june 4, 2002 notes notes 79rc32334/332 user reference manual 14 - 1 june 4, 2002 chapter 14 expansion interrupt controller introduction the rc32334 expansion interrupt contro ller provides the logic for so ftware to process the overall system interrupts generated by the rc32334, and it adds to the circuitry and cont rol already provided by the rc32300?s cpu core coprocessor 0 (cp0) regi sters. the rc32334 expansion interrupt controller registers each system interrupt and provides the pending status, wh ich can be used to automatically generate a hardware interrupt to the cpu core via t he individual mask bits for each interrupt. these mask bits enable software to allow/disallow each individual interrupt and to propagate or not propagate to the overall interrupt. the pending interrupt status can also be optionally se t or cleared by a direct software write. also, for software convenience, a masked write to the interrupt clear register allows a per bit clearing of pending interrupts. in addition to the cpu interrupt generation, a dedicated register for pci interrupt generation is provided. the same software interface is provided so that interrupts are steered to generate a hardware interrupt on the pci_inta_n (pci_gnt_n[2]) pin, when pci is in the satellite mode. features combines all interrupts into a single cpu interrupt combines all cpu- to- pci mailbox in terrupts into a single pci interrupt pending register bit for each interrupt mask register bit for each interrupt software clear register for clear per bit writes block diagram the expansion interrupt controller diagram is s hown in figure 14.1 and the group/bit-slice diagram is shown in figure 14.2 . figure 14.1 expansion interrupt controller block diagram interrupt_block_with_ip ip_bus ip slave interface interrupt- interrupt_block datain[31:0] dataout[31:0] slave_datain[31:0] slave_dataout[31:0] data_in[] data_out[] data mux int_n[3] interrupt_in[] _bit_slicex interrupt- _bit_slice0 expansion interrupt controller operational overview 79rc32334/332 user reference manual 14 - 2 june 4, 2002 notes figure 14.2 expansion interrupt block diagram group/bit-slice operational overview the expansion interrupt controller extends the rc 32300?s cpu core cp0 interrupt control by collating the rc32334 generated interrupts into a single cpu interrupt. when a general purpose interrupt is received, the interrupt service routine (isr) first sa ves cpu registers, checks its cause register and then checks its pending interrupt register. if the pending in terrupt is from the on-chip peripheral modules, then the isr checks the expansion interrupt controller pendi ng interrupt register. after treating/noting the inter- rupt condition, the isr resets the pending interrupt by writing to the corresponding bit in the expansion interrupt clear register. the isr can then exit by restoring the cpu regist ers and executing an rfe instruction. interrupts can be independently masked by the expansion interrupt mask register. when an isr is first called, the general rc32334 cpu cp0 global interrupt enable bit is disabled. the isr can then implement priority interrupts by first changing the rc32334 expans ion interrupt mask bits accordingly and re-enabling the rc32334 cpu cp0 global interrupt enable bit. device specific interrupt conditions are discussed in the chapter appropriate for the device. for more information on bus errors and their causes, see chapt er 8, rc32334 internal bus; for pci, see chapter 12, pci interface controller; dma interrupts are discuss ed in chapter 13, dma cont rollers; i/o causes and handling options in chapter 15, programmable i/o (pio) controller; timer conditions and causes in chapter 16, timer controller; uart conditions are def ined in chapter 17, uart controller; spi conditions are defined in chapter 18, se rial peripheral interface. signal definitions table 14.1 defines the signals and pi ns used by the interrupt controller to service and clear both rc32334 and externally generated interrupts. the internal cpu_int_n[3] signal is used by the majority of the expansion interrupt pending registers and when the pci bus writes a ?1? to one of the four low order bits in the pci_to_cpu mailbox pending register in group 12. the pci_gnt_n[2] is mode dependent and is used as either a bus grant signal to an exter nal device or a cpu to pci interrupt output pin. for more information on the pci interface controller, refer to chapter 12, pci interface controller. mask_reg pending_reg/ interrupt_bit_slice data_in[] data_out[] and/or gate interrupt_out_n interrupt_in_n[] clear reg expansion interrupt controller registers and address mapping 79rc32334/332 user reference manual 14 - 3 june 4, 2002 notes registers and address mapping as shown in table 14.2, each group?s interrupt c onditions are managed through three registers. these register functions are the same fr om group to group; however, the functions performed by the specific inter- rupt are type-specific. group ?0? (refer to table 14.20) is a special set used as a starting point to determine which group to service. each interrupt indicated in group ?0? is also included in groups 1 through 14. the address mapping for groups 1 through 14 is provided in tables 14.3 through 14.16. the functional descriptions of the interrupt pending, interrupt mask, and interrupt clear registers are shown in table 14.17, table 14.18, and table 14.19, res pectively. the fields of eac h register are illustrated in figures 14.3 through 14.5. pin type function cpu_int_n[3] input cpu interrupt #3 negated this active-low signal is an interrupt indication to the cpu from rc32334?s interrupt controller. note: this signal is internally hooked up to the cpu?s interrupt 3. pci_gnt_n[2] output pci bus grant #2 negated. recommend external pull-up resistor. in host mode, this active-low signal is an output indicating a grant to an external device. in sat- ellite mode, pci_gnt_n[2] is used as the pci_inta_n output pin. note : in host mode, cpu_int_n[1] on the rc32334 can be used for a pci_inta_n input and pci_int[d:c:b]_n can use cpu_int_n[5:4:2] on the rc32334 bus interface. interrupts are gener- ated from the expansion interrupt controller?s group 12. table 14.1 interrupt signal pins and definitions base address group 0 register function offset address effective address group 0 1800_0500 expansion interrupt pending register 0 00 base + offset expansion interrupt mask register 0 04 expansion interrupt clear register 0 08 table 14.2 expansion interrupt register group 0 address map base address group 1 register function offset address effective address group 1 1800_0510 bus error interrupt pending register 1 00 base + offset bus error interrupt mask register 1 04 bus error interrupt clear register 1 08 table 14.3 bus error register group 1 address map base address group 2 register function offset address effective address group 2 1800_0520 pio low interrupt pending register 2 00 base + offset pio low interrupt mask register 2 04 pio low interrupt clear register 2 08 table 14.4 pio low register group 2 address map expansion interrupt controller registers and address mapping 79rc32334/332 user reference manual 14 - 4 june 4, 2002 notes base address group 3 register function offset address effective address group 3 1800_0530 pio high interrupt pending register 3 00 base + offset pio high interrupt mask register 3 04 pio high interrupt clear register 3 08 table 14.5 pio high register group 3 address map base address group 4 register function offset address effective address group 4 1800_0540 timer rollover interrupt pending register 4 00 base + offset timer rollover interrupt mask register 4 04 timer rollover interrupt clear register 4 08 table 14.6 timer rollover interr upt register gr oup 4 address map base address group 5 register function offset address effective address group 5 1800_0550 uart 0 interrupt pending register 5 00 base + offset uart 0 interrupt mask register 5 04 uart 0 interrupt clear register 5 08 table 14.7 uart 0 interrupt register group 5 address map base address group 6 register function offset address effective address group 6 1800_0560 uart 1 interrupt pending register 6 00 base + offset uart 1 interrupt mask register 6 04 uart 1 interrupt clear register 6 08 table 14.8 uart 1 interrupt register group 6 address map base address group 7 register function offset address effective address group 7 1800_0570 dma 0 interrupt pending register 7 00 base + offset dma 0 interrupt mask register 7 04 dma 0 interrupt clear register 7 08 table 14.9 dma channel 0 register group 7 address map base address group 8 register function offset address effective address group 8 1800_0580 dma 1 interrupt pending register 8 00 base + offset dma 1 interrupt mask register 8 04 dma 1 interrupt clear register 8 08 table 14.10 dma channel 1 register group 8 address map expansion interrupt controller registers and address mapping 79rc32334/332 user reference manual 14 - 5 june 4, 2002 notes base address group 9 register function offset address effective address group 9 1800_0590 dma 2 interrupt pending register 9 00 base + offset dma 2 interrupt mask register 9 04 dma 2 interrupt clear register 9 08 table 14.11 dma channel 2 register group 9 address map base address group 10 register function offset address effective address group 10 1800_05a0 dma 3 interrupt pending register 10 00 base + offset dma 3 interrupt mask register 10 04 dma 3 interrupt clear register 10 08 table 14.12 dma channel 3 re gister group 10 address map base address group 11 register function offset address effective address group 11 1800_05b0 pci controller interrupt pending register 11 00 base + offset pci controller interrupt mask register 11 04 pci controller interrupt clear register 11 08 table 14.13 pci controller interr upt register group 11 address map base address group 12 register function offset address effective address group 12 1800_05c0 external interrupt pending register 12 00 base + offset external interrupt mask register 12 04 external interrupt clear register 12 08 table 14.14 external interrupt register group 12 address map base address group 13 register function offset address effective address group 13 1800_05d0 pci to cpu interrupt pending register 13 00 base + offset pci to cpu interrupt mask register 13 04 pci to cpu interrupt clear register 13 08 table 14.15 pci to cpu interrupt register group 13 address map base address group 14 register function offset address effective address group 14 1800_05e0 spi interrupt pending register 14 00 base + offset spi interrupt mask register 14 04 spi interrupt clear register 14 08 table 14.16 spi interrupt re gister group 14 address map expansion interrupt controller interrupt pending register 79rc32334/332 user reference manual 14 - 6 june 4, 2002 notes interrupt pending register note that a write to any of the pending registers, wi th a bit field set, will se t that particular pending bit until cleared by an appropriate write to the interrupt clear register. this allows software debug to test an interrupt service routine (isr), wi thout generating the actual interr upt condition which often depends on an infrequent external condition. figure 14.3 interrupt pending register fields interrupt mask register note that by default, rc32300 cpu core interrupt mask bits are set to allow interrupts but are disabled by the global enable bit being dis abled by default. in contrast, rc32334 interrupt masks are un-set to disallow interrupts by default, in addition to ha ving the rc32300 cpu core global enable bit disabled. figure 14.4 interrupt mask register interrupt clear register the interrupt clear register is a write only register that clears the pending interrupt bit. a masked write to the interrupt clear register allows a per bit clearing of all pending interrupts. figure 14.5 interrupt clear register field bits field name description 31:0 pending interrupt internal interrupts are registered on each rising clock edge, active low, and remain low for at least one clock cycle 1 = interrupt pending 0 = interrupt not pending table 14.17 interrupt pending field description bits field name description 31:0 interrupt clear 1 = interrupt enabled/allowed 0 = interrupt disabled/disallowed (default) table 14.18 interrupt mask register bits field name description 31:0 interrupt mask 1 = clear pending bit 0 = leave pending bit unchanged (default) table 14.19 interrupt clear register field descriptions 0 31 interrupt pending 32 interrupt mask 31 0 32 interrupt clear 31 0 expansion interrupt controller register group settings 79rc32334/332 user reference manual 14 - 7 june 4, 2002 notes register group settings register group 0 settings group ?0? is a special set of registers used as a st arting point to determine which group to service. each interrupt indicated in group ?0? is also included in groups 1 through 14. register group 1 settings register group 2 settings note: only pio pins 10:0 have a direct active low interrupt connection. bit register group 0 expansion register setting 14 interrupt controller[14] indicates that the group indicated has at least one active, unmasked interrupt source 13 interrupt controller[13] 12 interrupt controller[12] 11 interrupt controller[11] 10 interrupt controller[10] 09 interrupt controller[9] 08 interrupt controller[8] 07 interrupt controller[7] 06 interrupt controller[6] 05 interrupt controller[5] 04 interrupt controller[4] 03 interrupt controller[3] 02 interrupt controller[2] 01 interrupt controller[1] table 14.20 group 0 register settings bit register group 1 expansion register setting 13:01 reserved. must be written as ?0?. returns ?0? when read. 00 bus error ?1? if bus error ( group 1 ) bits are set table 14.21 group 1 (bus error) register settings bit register group 2 expansion register setting 11 pio[10] is low ? 1 ? if any of parallel i/o ( group 2 ) bits are set 10 pio[9] is low 09 pio[8] is low 08 pio[7] is low 07 pio[6] is low 06 pio[5] is low 05 pio[4] is low 04 pio[3] is low 03 pio[2] is low 02 reserved 01 pio[1] is low 00 pio[0] is low table 14.22 group 2 (pio low) register settings expansion interrupt controller register group settings 79rc32334/332 user reference manual 14 - 8 june 4, 2002 notes register group 3 settings note: only pio pins 6:0 have a direct active high interrupt connection. register group 4 settings register group 5 settings register group 6 settings bit register group 3 expansion register setting 07 pio[6] is high ?1? if any of pio high ( group 3 ) bits are set 06 pio[5] is high 05 pio[4] is high 04 pio[3] is high 03 pio[2] is high 02 reserved 01 pio[1] is high 00 pio[0] is high table 14.23 group 3 (pio high) register settings bit register group 4 expansion register setting 07 timer7 rollover interrupt for coldreset ?1? if any of the timer rollover interrupt ( group 4) bits are set 06 timer6 rollover interrupt for dramrefresh 05 timer5 rollover interrupt for ip bustimeout (buserror) 04 timer4 rollover interrupt for cpu bustimeout (buserror) 03 timer3 rollover interrupt fo r watchdog (uses coldreset_n instead of reset_n) 02 timer2 rollover interrupt 01 timer1 rollover interrupt 00 timer0 rollover interrupt table 14.24 group 4 (timer roll over interrupt) register settings bit register group 5 expansion register setting 02 uart0 interrupt 2 rxrdy ?1? if any of the uart0 ( group 5 ) bits are set 01 uart0 interrupt 1 txrdy 00 uart0 interrupt 0 iir(0) table 14.25 group 5 (uart 0 interrupt) register settings bit register group 6 expansion register setting 02 uart1 interrupt 2 rxrdy ?1? if any of the uart1 ( group 6) bits are set 01 uart1 interrupt 1 txrdy 00 uart1 interrupt 0 iir(0) table 14.26 group 6 (uart 1 interrupt) register settings expansion interrupt controller register group settings 79rc32334/332 user reference manual 14 - 9 june 4, 2002 notes register group 7 settings register group 8 settings register group 9 settings register group 10 settings register group 11 settings group 11 pending interrupts indicate a pci controller error condition as detailed in table 12.10 in the pci controller interrupt pending register 11 se ction of chapter 12, pci interface controller. bit register group 7 expansion register setting 04 dma ch0 dma clear interrupt ?1? if any of the dma ch0 interrupt 0 ( group 7) bits are set 03 dma ch0 dma transaction complete 02 dma ch0 descriptor not owned error interrupt 01 dma ch0 end too early error interrupt 00 dma ch0 done interrupt table 14.27 group 7 (dma memory2i/o interrupt 0) register settings bit register group 8 expansion register setting 04 dma ch1 dma clear interrupt ?1? if any of the dma ch1 interrupt 1 ( group 8) bits are set 03 dma ch1 dma transaction complete 02 dma ch1 descriptor not owned error interrupt 01 dma ch1 end too early error interrupt 00 dma ch1 done interrupt table 14.28 group 8 (dma memory2i o interrupt 1) register settings bit register group 9 expansion register setting 04 dma ch2 dma clear interrupt ?1? if any of the dma ch2 interrupt 0 ( group 9) bits are set 03 dma ch2 dma transaction complete 02 dma ch2 descriptor not owned error interrupt 01 dma ch2 end too early error interrupt 00 dma ch2 done interrupt table 14.29 group 9 (dma pci master interrupt 0) register settings bit register group 10 expansion register setting 04 dma ch3 dma clear interrupt ?1? if any of the dma ch3 interrupt 1 ( group 10) bits are set 03 dma ch3 dma transaction complete 02 dma ch3 descriptor not owned error interrupt 01 dma ch3 end too early error interrupt 00 dma ch3 done interrupt table 14.30 group 10 (dma pci mast er interrupt 1) register settings expansion interrupt controller register group settings 79rc32334/332 user reference manual 14 - 10 june 4, 2002 notes register group 12 settings when pci is in the satellite mode, pending interrupts in register 12 affect the pci interrupt pin. this register does not affect the internal cpu_int_n[3] si gnal directly. the output always goes to bit 12 of the interrupt0 register, which then may be masked/unmask ed to cause the internal cpu_int_n[3] signal to assert. note: the pci_interrupt_n (pci_gnt_n[2]) signal is in ternally synchronized with the pci_clk signal twice. and as such the output propagation is relative to the rising edge of pci_clk instead of cpu_masterclk. register group 13 settings group 13 pending interrupts indicate a pci controller pci initiated interrupt to the rc32334 cpu, as detailed in chapter 12, table 12.12. bit register group 11 expansion register setting 03 pci controller interrupt 3 ?1? if any of the pci controller ( group 11) bits are set 02 pci controller interrupt 2 01 pci controller interrupt 1 00 pci controller interrupt 0 table 14.31 group 11 (pci controller) register settings bit register group 12 expansion register setting 15 pci cpu2pci mailbox interrupt 3 ?1? if any of the external interrupt ( group 12) bits are set 14 pci cpu2pci mailbox interrupt 2 13 pci cpu2pci mailbox interrupt 1 12 pci cpu2pci mailbox interrupt 0 11 dma mem2io descriptor not owned error interrupt 1 10 dma mem2io end too early error interrupt 1 09 dma mem2io done interrupt 1 08 dma mem2io descriptor not owned error interrupt 0 07 dma mem2io end too early error interrupt 0 06 dma mem2io done interrupt 0 05 uart1 interrupt 2 1 1. not in rc32332. 04 uart1 interrupt 1 1 03 uart1 interrupt 0 1 02 uart0 interrupt 2 ?1? if any of the external interrupt ( group 12) bits are set 01 uart0 interrupt 1 00 uart0 interrupt 0 table 14.32 group 12 register settings expansion interrupt controller timing diagrams 79rc32334/332 user reference manual 14 - 11 june 4, 2002 notes register group 14 settings timing diagrams for the timing of various transactions asserting/ de-asserting internal cpu_i nt_n[3], see figures 14.6 through 14.9. the timing behaviors of transactions asserting/de-asserti ng pci are shown in figures 14.10 and 14.11. the timing requirements for cpu_int_n[5, 4,2,1,0] and cpu_nmi_n are shown in figure 14.12. figure 14.6 pio input asse rting internal cpu_int_n[3] figure 14.7 internal condition assert ing internal cpu_int_n[3] interrupt figure 14.8 pending register write asserting internal cpu_int_n[3] bit register group 13 expansion register setting 03 pci pci2cpu mailbox interrupt 3 ?1? if any of the pci pci12cpu mailbox ( group 13) bits are set 02 pci pci2cpu mailbox interrupt 2 01 pci pci2cpu mailbox interrupt 1 00 pci pci2cpu mailbox interrupt 0 table 14.33 group 13 register settings bit register group 14 expansion register setting 00 spi interrupt 0 ?1? if the spi ( group 14) bits are set table 14.34 group 14 register settings 1 2 3 4 5 tp thld tsu cpu_masterclk dma_ready_n[0] (internal cpu_int_n[3]) 1 2 3 4 5 7 6 7 tp cpu_masterclk (internal dma ch0 int[2:0]) (internal cpu_int_n[3]) 1 2 3 4 5 00 80 tdo2 cpu_masterclk (internal write_n) (internal pending_reg3[7:0]) (internal cpu_int_n[3]) expansion interrupt controller timing diagrams 79rc32334/332 user reference manual 14 - 12 june 4, 2002 notes figure 14.9 pending or clear register write de-asserting internal cpu_int_n[3] interrupt figure 14.10 internal condition asserting pci interrupt figure 14.11 pending or clear regist er write de-asserting pci interrupt figure 14.12 cpu interrupts 1 2 3 4 5 80 00 tdoh2 cpu_masterclk (internal write_n) (internal pending_reg3[7:0]) (internal cpu_int_n[3]) 1 2 3 4 5 0012 1000 1012 tp cpu_masterclk (internal write_n) (internal interrupt_out_n) pending_reg12[15:0] pci_clk (internal int_pci_int_n_sync1) (internal int_pci_int_n_sync2) pci_gnt_n[2] (pci_int_n) 1 2 3 4 5 2012 0012 tp cpu_masterclk (internal write_n) pending_reg12[15:0] (internal interrupt_out_n) pci_clk (internal int_pci_int_n_sync1) (internal int_pci_int_n_sync2) pci_gnt_n[2] (pci_int_n) 1 2 3 4 5 thld13 tsu9 cpu_masterclk cpu_int_n[5,4,2,1,0], cpu_nmi_n expansion interrupt controller rc32334 interrupt flow 79rc32334/332 user reference manual 14 - 13 june 4, 2002 notes rc32334 interrupt flow 1. initialize interrupts 1. disable cpu cp0 status regi ster global interrupt enable bit. 2. enable cpu cp0 status register interrupt mask bi t 3. (optionally disable the other seven cpu inter- rupts.) 3. enable the appropriate rc32334 expansion interrupt mask register bit. (o ptionally disable the other interrupt mask bits.) 4. clear the appropriate rc32334 expansion interrupt clear register bit (for all unmasked interrupt bits). 5. enable cpu cp0 status register global interrupt enable bit. 2. wait for interrupt 1. hardware interrupt generated by pulsing the appropr iate signal/pin low for at least 1.0 clock, either internally or externally; or by software writi ng to the appropriate pending interrupt register bit. 2. the rc32334 expansion interrupt hardware will se t the appropriate expansion interrupt pending bit. the pending bit will remain set until software clears it. 3. if the appropriate expansion interrupt mask bit is not set, then no further hardware action occurs, otherwise an internal interrupt is sent to ex pansion interrupt register set 0 and to the rc32334 cpu_int_n pin. 4. the internal cpu_int_n signal asserts and on a clock by clock basis asserts t he internal cpu interrupt port causing it to assert the cpu cp0 cause r egister interrupt pending bit 3. the cpu_int_n pin remains asserted until software clears the appropria te expansion interrupt pending bit (or disables the appropriate expansion interrupt mask bit). 5. if the cpu cp0 status register interrupt mask bit 3 is enabled, then cpu takes exception and jumps to exception vector. cpu cp0 status register gl obal interrupt enable bit is automatically disabled. 3. software interrupt service routine (isr) 1. if software isr read of cpu cp0 cause register interrupt pending bit 3 is set, then continue with isr. 2. if software isr read of the appropriate rc 32334 expansion interrupt pending register bit is 3. set, then continue with isr. 4. clear the appropriate interrupt source (devic e dependent, for instance read uart data), causing the interrupt source to become de-asserted. 5. clear the appropriate rc32334 expansion interrupt clear register bit. if no other non-masked inter- rupts exist, this will cause the rc32334 pin to de-assert. 6. either check for more interrupts or return from exception (eret instruction automatically re-enables cpu cp0 status register gl obal interrupt enable bit). optional algorithm for priority interrupts the first expansion interrupt register set 0 combines the interrupt output from each of the other expan- sion interrupt register sets. if ex pansion register set 0 is used, t hen the software isr can more quickly find the cause of an expansion interrupt by then ju mping directly to the expansion interrupt pending register that has a register set 0 interrupt pending bit pending. in this case, after receiving the interrupt, do the following: 1. service all the interrupts associated with the ex pansion interrupt set and clear the original causes. 2. clear the interrupt pending bits using the ex pansion interrupt set?s interrupt clear register. 3. clear the appropriate expansion interrupt register set 0 entry using inte rrupt clear register 0. optional algorithm for non-prioritized interrupts the first expansion interrupt register 0 set can be i gnored (masked out) in which case the software isr simply checks each expansion interrupt pending register in a linear search. expansion interrupt controller rc32334 interrupt flow 79rc32334/332 user reference manual 14 - 14 june 4, 2002 notes notes 79rc32334/332 user reference manual 15 - 1 june 4, 2002 chapter 15 programmable i/o (pio) controller introduction the rc32334 provides software programmable i/o (p io) pins, so that unused pins can be used as general purpose discrete i/o pins. as such, if a pin?s function?for example, timer output?is not required, then that pin can be programmed for use as a general purpose pio pin. once programmed to a general purpose function, pi ns can then be software programmed as inputs or outputs. when set in the output mode, the pin?s val ue becomes software programmable. when set to the input mode, the pins are software r eadable. this chapter provides the signal descriptions, register mapping, and programming information needed to use th is software programmable feature. features 16 1 peripheral pins, reusable as pio pins bidirectional pins ? output pins can be programmed hi/low, in parallel ? input pins can be read in parallel. overview the rc32334?s pio pins are programmable in both the input and output directions. when programming to the input mode, data from the input pin are r ead by the rc32300 cpu core as required. in the output mode, data can also control the output level of the pin at any time. the default state of most pins is input. pio pins are multiplexed between peripheral and general purpose use, as shown in the signal definition tables that follow. as such, pio pins on unused per ipherals can be reused on a system basis for the following general purpose uses: as a parallel port as an interrupt input/output from or to another device as status input/output from or to another device. switching between the four possibl e modes is accomplished through t he following general algorithm: 1. optional reset initialization by use of external pull-ups/pull-downs. 2. write the pio direction register bits to be in the input mode. 3. write the pio function regi ster bits to the desired mode. 4. write the pio direction register bits to the desired mode. 5. the pio data register is ready for reading and writing and the internal peripherals are ready. 1. the rc32332 includes 12 pio pins. programmable i/o (pio) controller block diagram 79rc32334/332 user reference manual 15 - 2 june 4, 2002 notes block diagram figure 15.1 shows the pio block diagram and figur e 15.2 shows the pio bit-slice block diagram. figure 15.1 pio block diagram figure 15.2 pio block diagram bit-slice pio_block_with_ip ip_bus ip slave interface pio_bit_slice0 pio_bit_slicex pio_block datain[31:0] dataout[31:0] slave_datain[31:0] slave_dataout[31:0] data_in[] data_out[] data mux pad_out_n[], pad_in_n[], peripheral_out_n[] pad_out_en_n[] peripheral_in_n[] dir_reg effect_sel_reg pio_bit_slice data_in[] data_out[] data_bit_reg peripheral_out_n[] peripheral_in_n[] pad_in_n[] pad_out_n[] pad_out_en_n[] 1?b0 inv function_sel_reg programmable i/o (pio) controller performing initialization programming 79rc32334/332 user reference manual 15 - 3 june 4, 2002 notes performing initia lization programming peripheral function input mode: at reset, the input mode is the default state for most of the pins; therefore, no additional pr ogramming is necessary and the pio pins are ready for use by the internal peripheral. however, in the case where the default is set to the output mode, perform the following steps: 1. write the pio direction register bits to be in the input mode. 2. the pio function bits are already in the function mode. 3. the pio pins are ready for use by the internal peripheral. peripheral function output mode: at reset, some pins may be defaulted to the output mode and are ready for use by the internal peri pheral. however, in the case where the default has been set to the input mode, perform the following steps: 1. optional reset initialization by use of external pull-ups/pull-downs. 2. write the pio direction register bits to be in the output mode. 3. the pio function register bits are already in the function mode. 4. the pio pins are ready for use by the internal peripheral. general purpose input mode: program the unused pins for use in the general purpose input mode function using the following steps: 1. write the pio function register bits to the g eneral purpose mode, so that unused internal peripheral ports will be internally driven to their de-asserted value. 2. if the pin is an output by default, write the pio di rection register bits to be in the input mode. 3. the pio data register is ready for reading. general purpose output mode: program unused pins for use in the general purpose output mode function using the following steps: 1. initialize optional reset by us e of external pull-ups/pull-downs. 2. write the pio function register bits to be in the general purpose mode. 3. write the pio direction register bits to be in the output mode. 4. the pio data register is ready for writing. note 1: pins that are not in the general purpose output mode automatically mask their respective data register bits from being written. note 2: when switching from the input mode to the out put mode, the output will initially drive the value registered by the data register, 1 clo ck previous to the input to output transition. signal definitions the signals listed in the tables that follow control the serial mode protocol, uart interface, timer and dma interface functions. any active-low signals ar e noted by an _n. the alternate pin names?including pio multiplexed pins?and descriptions are also listed nex t to the main signal name. for a summary of the differences between alternate pio names in the rc32334 and rc32332, refer to appendix g, tables g.2 and g.3. spi interface type alternate descriptions spi_mosi i/o pio[10] spi data output serial mode: output pin from rc32334 as an input to a serial chip for the serial data input stream. pci satellite mode: output pin from rc32334 that connects as an input to a serial chip for the serial data input stream for loading pci configuration registers in the rc32334 reset initialization vector pci boot mode. alternate function: pio[10]. defaults to the output direction at reset time. table 15.1 serial mode protocol/alt ernate signal descriptions (part 1 of 2) programmable i/o (pio) controller signal definitions 79rc32334/332 user reference manual 15 - 4 june 4, 2002 notes spi_miso i/o pio[7] spi data input serial mode: input pin to rc32334 from the output of a serial chip for the serial data output stream. pci satellite mode: input pin from rc32334 that connects as an output to a serial chip for the serial data output stream for loading pci config- uration registers in the rc32334 reset initialization vector pci boot mode. defaults to input direction at reset time. alternate function: pio[7]. spi_sck i/o pio[9] spi clock serial mode: output pin for serial clock. pci satellite mode: output pin for serial clock for loading pci configu- ration registers in the rc323334 reset initialization vector pci boot mode. alternate function: pio[9]. defaults to the output direction at reset time. spi_ss_n i/o pio[8] spi chip select output pin selecting the serial protocol device as opposed to the pci satellite mode eeprom device. alternate function: pio[8]. defaults to the output direction at reset time. 16550 uart interface type alternate signals descriptions uart_rx[0] uart_rx[1] i/o pio[6] pio[4] uart receive data bus uart mode: each uart channel receives data on their respective input pin. uart_tx[0] uart_tx[1] i/o pio[5] pio[3] uart transmit data bus recommend external pull-up. uart mode: each uart channel sends data on their respective output pin. note that these pins default to inputs at reset time and must be programmed via the pio interface before being used as uart outputs. uart_cts_n[0] 1 uart_dsr_n[0] 1 uart_dtr_n[0] 1 uart_rts_n[0] 1 1. not in the rc32332. i/o i/o i/o i/o pio[15] pio[14] pio[13] pio[12] uart transmit data bus uart mode: data bus modem control signal pins for uart channel 0 pio mode: these pins are also multiplexed as pio pins. table 15.2 uart interface/alternate signal descriptions timer/counter type alternate signal description timer_tc_n[0] 1 1. not in the rc32332. i/o pio[2] timer terminal count overflow negated output indicating that the timer has reached its count compare value and has overflowed back to zero. table 15.3 timer/altern ate signal descriptions spi interface type alternate descriptions table 15.1 serial mode protocol/alt ernate signal descriptions (part 2 of 2) programmable i/o (pio) controller register mapping and definitions 79rc32334/332 user reference manual 15 - 5 june 4, 2002 notes register mapping and definitions programming pio pins to be used in the peripheral function input/output or general purpose input/ output modes is handled through initialization and setup of the pio data, pio direction control, and pio function control registers. the addr ess mapping for each register is list ed in table 15.6. each register?s description includes the default value. pio register set 0 adds alternative pio usage to the spi, uart data, timer, and dma pins. pio register set 1 adds alternative pio usage to the modem control of uart0. added are: uart_cts_n[0], uart_dsr_n[0], uart_dtr_n[0], uart_rts_n[0] pins via pio register set 1 (starting at physical address 0x18000610) bits 4:1 respecti vely. all modem signals default to inputs. systems may optionally use external pull-ups or pull-downs to init ialize pins that are to be used as outputs. pio register set 1 also adds pci eeprom writeabilit y to the pci eeprom by allowing pci_eeprom_cs to be controlled from a software bit-blasting driv er. the pci_eeprom_cs signal defaults to an output. pio data register 0 bits in this register clock data from the pins, if set in the input direct ion or the special function mode. bits can only be written if that bit is in both the output direction and general purpose mode. figure 15.3 illus- trates the fields of pio data register 0, and tables 15.7 and 15.8 describe the fields. dma interface type alternate signal description dma_ready_n[0] dma_ready_n[1] 1 1. not in the rc32332. i/o pio[1], dma_done_n[0] pio[0], dma_done_n[1] 1 dma ready negated bus requires external pull-up. input pin for general purpose dma channels[1:0] that can initiate the next data in the current dma descriptor frame. dma_done_n[1:0] i/o dma_ready_n[1:0] dma done requires external pull-up. input pin for general purpose dma channels[1:0] that can terminate the current dma descriptor frame. table 15.4 dma interface/alternate signal descriptions pci interface type alternate signal description pci_eeprom_cs i/o pci_gnt_n[1], pio[11] pci eeprom chip select pci_gnt_n[1] i/o pci_eeprom_cs, pio[11] pci bus grant # 1 negated table 15.5 pio interface/alternate signal descriptions base address register name offset address effective address 1800_0600 pio data register 0 00 base + offset pio direction control register 0 04 pio effect select control register 0 08 1800_0610 pio data register 1 00 pio direction control register 1 04 pio effect select control register 1 08 1800_060c pio new feature register 0 0c 1800_060c pio new feature register 1 1c table 15.6 pio register address map programmable i/o (pio) controller register mapping and definitions 79rc32334/332 user reference manual 15 - 6 june 4, 2002 notes figure 15.3 pio data register 0 fields note: timer_tc_n[0], uart_rx[1], and uart_tx[1], show n in figure 15.3, are not in the rc32332. pio data register 1 bits in this register clock data from the pins, if set in the input direct ion or the special function mode. bits can only be written if that bit is in both the output direction and general purpose mode. figure 15.4 illus- trates the fields of pio data register 1, and tables 15.9 and 15.10 describe the fields. figure 15.4 pio data register 1 fields bit field description 31:12 reserved to 1 requires 1 to be written in these fields 11 spi_mosi pio[10] spi control functions brought to external pins 10 spi_sck pio[9] 9 spi_ss_n pio[8] 8 spi_miso pio[7] 7 uart_rx[0] pio[6] uart data brought to external pins 6 uart_tx[0] pio[5] 5uart_rx[1] 1 pio[4] 1. not in the rc32332. 4 uart_tx[1] 1 pio[3] 3 timer_tc_n[0] 1 pio[2] timer function brought to external pin 2 reserved to 1 requires 1 to be written to this field 1 dma_ready_n[0] pio[1] dma control functions brought to external pins 0 dma_ready_n[1] pio[0] table 15.7 pio data register 0 field description bit description 31:0 pio data register 0 table 15.8 pio data regi ster 0 high/low descriptions uart_tx[1] timer_ ready_ dma_ ready_ spi_ss_n uart_rx[0] uart_tx[0] uart_rx[1] dma_ spi_miso spi_sck spi_mosi n[0] n[1] reserved tc_n[0] 1 20 3 4 5 6 7 8 9 10 11 31 pio[0] pio[1] pio[2] pio[3] pio[4] pio[5] pio[6] pio[7] pio[8] pio[9] pio[10] value description 1 pio pin is high (default) 0 pio pin is low pci_eeprom_cs reserved 31 4 3 2 1 0 uart_cts_n[0] uart_dsr_n[0] uart_dtr_n[0] uart_rts_n[0] pio[11] pio[12] pio[13] pio[14] pio[15] programmable i/o (pio) controller register mapping and definitions 79rc32334/332 user reference manual 15 - 7 june 4, 2002 notes note: uart_cts_n[0], uart_dsr_n[0], uart_dtr_n[0], and uart_rts_n[0], shown in figure 15.4, are not in the rc32332. pio direction register 0 this 32-bit register programs t he input/output modes for both the general purpose and special function modes. when programmed to the input mode, data from the input pin can be read by the rc32300 cpu core as required. when in the output mode, data can al so control the output level of the pin at any time. figure 15.5 illustrates the fields of pio direction regi ster 0, and tables 15.11 and 15.12 describe the fields. figure 15.5 pio direction register 0 fields note: timer_tc-n[0], uart_rx[1], and uart_tx[1], show n in figure 15.5, are not in the rc32332. bit field description 31:5 reserved to 1 requires 1 to be written in these fields 4 uart_cts_n[0] 1 pio[15] 1. not in the rc32332. uart modem control functions brought to external pins 3 uart_dsr_n[0] 1 pio[14] 2 uart_dtr_n[0] 1 pio[13] 1 uart_rts_n[0] 1 pio[12] 0 pci_eeprom_cs pio[11] pci eeprom chip select brought to external pin table 15.9 pio data register 1 field description bit description 31:0 pio data register 1 table 15.10 pio data regi ster 1 high/low descriptions bit field description 31:12 reserved to 0 requires 0 to be written in these fields 11 spi_mosi pio[10] spi control functions brought to external pins 10 spi_sck pio[9] 9 spi_ss_n pio[8] 8 spi_miso pio[7] table 15.11 pio function direction register 0 field description (part 1 of 2) value description 1 pio pin is high (default) 0 pio pin is low uart_tx[1] timer_ ready_ dma_ ready_ spi_ss_n uart_rx[0] uart_tx[0] uart_rx[1] dma_ spi_miso spi_sck spi_mosi n[0] n[1] reserved tc_n[0] 1 20 3 4 5 6 7 8 9 10 11 31 pio[0] pio[1] pio[2] pio[3] pio[4] pio[5] pio[6] pio[7] pio[8] pio[9] pio[10] programmable i/o (pio) controller register mapping and definitions 79rc32334/332 user reference manual 15 - 8 june 4, 2002 notes pio direction register 1 this 32-bit register programs t he input/output modes for both the general purpose and special function modes. when programmed to the input mode, data from the input pin can be read by the rc32300 cpu core as required. when in the output mode, data can al so control the output level of the pin at any time. figure 15.6 illustrates the fields of pio direction r egister 1, and tables 15.13 and 15.14 describe the fields. figure 15.6 pio direction register 1 fields note: uart_cts_n[0], uart_dsr_n[0], uart_dtr_n[0], and uart_rts_n[0], shown in figure 15.6, are not in the rc32332. 7 uart_rx[0] pio[6] uart data brought to external pins 6 uart_tx[0] pio[5] 5uart_rx[1] 1 pio[4] 4 uart_tx[1] 1 pio[3] 3 timer_tc_n[0] 1 pio[2] timer function brought to external pin 2 reserved to 0 requires 0 to be written in this field 1 dma_ready_n[0] pio[1] dma control functions brought to external pins 0 dma_ready_n[1] pio[0] 1. not in the rc32332. bit description 31:0 pio direction register 0 table 15.12 pio direction register 0 input/output descriptions bit field description table 15.11 pio function direction register 0 field description (part 2 of 2) value description 1 pio pin is an output (default for pci_eeprom_cs, spi_mosi, spi_sck, spi_cs) 0 pio pin is an input (default for most pins) pci_eeprom_cs reserved 31 4 3 2 1 0 uart_cts_n[0] uart_dsr_n[0] uart_dtr_n[0] uart_rts_n[0] pio[11] pio[12] pio[13] pio[14] pio[15] programmable i/o (pio) controller register mapping and definitions 79rc32334/332 user reference manual 15 - 9 june 4, 2002 notes pio function select register 0 when in the input direction, the pin goes to the gener al purpose data bit regardless of the value in the function select field; however, if the function select field is selected, the pin also goes to the internal module. if the function select field is not selected, then the internal module input is held de-asserted high. when in the output direction, the pin is generated from either the internal module or the data register, depending upon the value of the pio function select bit fiel d. figure 15.7 illustrates the fields of pio func- tion select register 0, and tables 15.15 and 15.16 describe the fields. figure 15.7 pio function select register 0 fields note: timer_tc_n[0], uart_rx[1], and uart_tx[1], show n in figure 15.7, are not in the rc32332. bit field description 31:5 reserved to 0 requires 0 to be written in these fields 4 uart_cts_n[0] 1 pio[15] 1. not in the rc32332. uart modem control functions brought to external pins 3 uart_dsr_n[0] 1 pio[14] 2 uart_dtr_n[0] 1 pio[13] 1 uart_rts_n[0] 1 pio[12] 0 pci_eeprom_cs pio[11] pci eeprom chip select brought to external pin table 15.13 pio direction register 1 field description bit description 31:0 pio direction register 1 table 15.14 pio direction regi ster 1 input/output description bit field description 31:12 reserved to 1 requires 1 to be written in these fields 11 spi_mosi pio[10] spi control functions brought to external pins 10 spi_sck pio[9] 9 spi_ss_n pio[8] 8 spi_miso pio[7] table 15.15 pio function select register 0 field description (part 1 of 2) value description 1 pio pin is an output (default for pci_eeprom_cs, spi_mosi, spi_sck, spi_cs) 0 pio pin is an input (default for most pins) uart_tx[1] timer_ ready_ dma_ ready_ spi_ss_n uart_rx[0] uart_tx[0] uart_rx[1] dma_ spi_miso spi_sck spi_mosi n[0] n[1] reserved tc_n[0] 1 20 3 4 5 6 7 8 9 10 11 31 pio[0] pio[1] pio[2] pio[3] pio[4] pio[5] pio[6] pio[7] pio[8] pio[9] pio[10] programmable i/o (pio) controller register mapping and definitions 79rc32334/332 user reference manual 15 - 10 june 4, 2002 notes pio function select register 1 when in the input direction, the pin goes to the gener al purpose data bit regardless of the value in the function select field; however, if the function select field is selected, the pin also goes to the internal module. if the function select field is not selected, then the internal module input is held de-asserted high. when in the output direction, the pin is generated from either the internal module or the data register, depending upon the value of the pio function select bit fi eld. figure 15.7 illustrates the fields of the pio function select register 1, and t ables 15.17 and 15.18 describe the fields. figure 15.8 pio function select register 1 fields note: uart_cts_n[0], uart_dsr_n[0], uart_dtr_n[0], and uart_rts_n[0], shown in figure 15.8, are not in the rc32332. 7 uart_rx[0] pio[6] uart data brought to external pins 6 uart_tx[0] pio[5] 5uart_rx[1] 1 pio[4] 4 uart_tx[1] 1 pio[3] 3 timer_tc_n[0] 1 pio[2] timer function brought to external pin 2 reserved to 1 requires 1 to be written in this field 1 dma_ready_n[0] pio[1] dma control functions brought to external pins 0 dma_ready_n[1] pio[0] 1. not in the rc32332. bit description 31:0 pio function select register 0 table 15.16 pio special function/general purpose select register 0 description bit field description table 15.15 pio function select register 0 field description (part 2 of 2) value description 1 pio pin is a special function pin connected to/from an internal module (default) 0 pio pin is a general purpose pin pci_eeprom_cs reserved 31 4 3 2 1 0 uart_cts_n[0] uart_dsr_n[0] uart_dtr_n[0] uart_rts_n[0] pio[11] pio[12] pio[13] pio[14] pio[15] programmable i/o (pio) controller register mapping and definitions 79rc32334/332 user reference manual 15 - 11 june 4, 2002 notes new feature register new feature register 0 when the new feature field is selected, the entire group of pins associated with pio register set 0 becomes synchronized with double regist er sampling using the system clock. new feature register 1 when the new feature field is selected, the entire group of pins associated with pio register set 1 becomes synchronized with double regist er sampling using the system clock. figure 15.9 pio new feature register fields bit field description 31:5 reserved to 1 requires 1 to be written in these fields 4 uart_cts_n[0] 1 pio[15] 1. not in the rc32332. uart modem control functions brought to external pins 3 uart_dsr_n[0] 1 pio[14] 2 uart_dtr_n[0] 1 pio[13] 1 uart_rts_n[0] 1 pio[12] 0 pci_eeprom_cs pio[11] pci eeprom chip select brought to external pin table 15.17 pio function select register 1 field description bit description 31:0 table 15.18 pio function select register 1 special function/general purpose description bits field name description 31:1 reserved to 0 requires 0 to be written in these fields 0 new feature mode table 15.19 pio new featur e register field description pio function select register 1 value description 1 pio pin is a special function pin connected to/from an internal module (default) 0 pio pin is a general purpose pin new feature mode reserved 31 1 0 value description 1 new feature mode: adds double registering syn- chronization on external inputs. 0 backward compatibility mode programmable i/o (pio) controller timing diagrams 79rc32334/332 user reference manual 15 - 12 june 4, 2002 notes timing diagrams in figure 15.10 and figure 15.11, timing for pio[7:6] is shown. note that the timing for all other pio signals, pio[15:8] and pio[5:0], is si milar when the appropriate pio data r egister and its bit fields are read or written. figure 15.10 pio input, affecting data register figure 15.11 data register write, affecting pio output 1 2 3 4 5 fff e7f fff 3 0 3 thld9 thld9 tsu7 tsu7 thld9 thld9 tsu7 tsu7 cpu_masterclk (internal pio data register 0) pio[7:6] 0 3 1 2 3 4 5 fff e7f 3 0 tdo16, tdoh7 cpu_masterclk (internal write_n) (internal pio data register 0) pio[7:6] notes 79rc32334/332 user reference manual 16 - 1 june 4, 2002 chapter 16 timer controller introduction in addition to the timer on the rc32300 cpu core, t he rc32334 has eight on-chip timers: three general purpose timers and five timers that are optionally dedicated to watchdog, cpu bus timeout, ip bus timeout, sdram refresh, and warmreset. these eight timers are different and in addition to the timer available on the rc32300 cpu core as part of cp0. these eight system timers count on each system clock beginning from zero, timing out after reachi ng a programmable compare value and resetting to zero automatically. uses for these timers include r eal-time clock, cascaded real-time clock and time-slice clock. features 3 general purpose 32-bit timers 5 8/16-bit peripheral dedicated time rs available for general reuse programmable compare/count roll over value selectable count mode versus input gate mode for timer0 and timer1 timer 0 internally cascaded to timer 1. block diagram figure 16.1 and figure 16.2 show the timing block diagram and individual timer core block diagram, respectively. figure 16.1 timer block diagram timer_block_with_ip ip_bus ip slave interface timer0 timer7 timer_block datain[31:0] dataout[31:0] slave_datain[31:0] slave_dataout[31:0] data_in[] data_out[] data mux tc_n[] gate_in[] coldreset_n, buserr_reset_n, bus_timeout_reset_n ip_bus timer controller overview 79rc32334/332 user reference manual 16 - 2 june 4, 2002 notes figure 16.2 diagram of individual timer core overview the general purpose timers, timer 0 and timer 1, can be used as a real-time clock . to meet real-time clock periods of 1 day or less, the timer 1 (internal signal timer_gate_n[1] ) port is internally connected to the timer 0 (internal signal timer_tc_n[0]) port. this cascades the overflow count from timer 0 into the effective clock for timer 1, thus allowing a 64-bit coun t. general purpose timer 2 can be used as a time-slice clock . the general purpose timers are organized as: count register [31:0] compare register [31:0] control register[1] gate/timer bit control register[0] enable bit in addition to the general purpose timer 0, timer 1, and timer 2, there are five separate dedicated timers for watchdog, cpu bus time-out, ip bus ti me-out, sdram refresh, and warmreset. warmreset timer 7 is used to count out clocks between the de-assertion of coldreset_n and the de-assertion of reset_n. the timers are reset to 0x0000_0000 and count up to and equal to the value in their respective compare register. for the 1 clock of compare, tc_n is asserted. the output pin for timers 0 and 1 are synchronized (delayed) by one clock. at th is point, the count rolls over back to 0x0000_0000 . note that timer 7 is reset during a cold reset but not a warm reset. timers 0 and 1 contain an input gate mode, which uses the timer_gate_n pin as a clock enable for the timer ticks. the input is not synchr onized (delayed) by the clock and feeds directly into the counter. to use the timer pins, the pio direction register of the pi o controller must first be programmed (for programming specifics of the pio direction register, see chapter 15). the default function is the timer_gate_n input pin. timer pin functions are described in table 16.1. timer 3 can only be used as a general purpose timer if the ip bus bridge bus error control register has the watchdog enable bit disabled. timers 4 and 5 can onl y be used as general purpose timers if the ip bus bridge bus error control register has the cpu buserror and/or ip buserror enabl e bits disabled, respec- tively. control_reg count_reg tc_n compare_reg datain[31:0] dataout[31:0] count_en gate_in clk, d-reg equal timer_core reset_n reset_count_n d-reg timer controller signal definitions 79rc32334/332 user reference manual 16 - 3 june 4, 2002 notes signal definitions register mapping the register sets for timers 0 through 3 are mapped as listed in table 16.2, table 16.3 and table 16.4. register sets for the five timers dedicated to per ipherals are mapped as listed in table 16.5, table 16.6, table 16.7, table 16.8, and table 16.9. timer/counter type alternative signals descriptions timer_tc_n[0] i/o pio[2], timer_gate_n[0] terminal count mode (timer_tc_n): output indicating that the timer has reached its count compare value and has overflowed back to 0. timer_gate_n[0] i/o timer_tc_n[0], pio[2] gate mode (timer_gate_n): input indicating that the timer may count one tick on the next clock edge. table 16.1 pin definitions for the timer/counter signals base address register 0 register name offset address effective address register 0 1800_0700 timer control register 0 (32 bits) 00 base + offset timer count register 0 04 timer compare register 0 08 table 16.2 timer register 0 (general purpose) address map base address register 1 register name offset address effective address register 1 1800_0710 timer control register 1 (32 bits) 00 base + offset timer count register1 04 timer compare register 1 08 table 16.3 timer register 1 (general purpose) address map base address register 2 register name offset address effective address register 2 1800_0720 timer control register 2 (32 bits) 00 base + offset timer count register 2 04 timer compare register 2 08 table 16.4 timer register 2 (general purpose) address map base address register 3 register name offset address effective address register 3 1800_0730 timer control register 3 for watchdog (32 bits) 00 base + offset timer count register 3 for watchdog 04 timer compare register 3 for watchdog 08 table 16.5 register 3 for watchdog address map timer controller register mapping 79rc32334/332 user reference manual 16 - 4 june 4, 2002 notes timer control register description to meet real-time clock periods of 1 day or less, the internal signal timer_gate_n[1] port is internally connected to the internal signal timer_tc_n[0] port. ( note : on the rc32332, the signal timer_tc_n[0] is not present.) this cascades the overflow count from timer 0 into the effective clock for timer 1, thus allowing a 64-bit count. note : the five dedicated peripheral ti mers are hardwired internally to their respective module. figure 16.3 timer control register fields base address register 4 register name offset address effective address register 4 1800_0740 timer control register 4 for cpu bustimeout (buserror) (16-bits) 00 base + offset timer count register 4 for cpu bustimeout (buserror) 04 timer compare register 4 for cpu bustimeout (buserror) 08 table 16.6 register 4 for cpu bus time-out address map base address register 5 register name offset address effective address register 5 1800_0750 timer control register 5 for ip bustimeout (buserror) (16-bits) 00 base + offset timer count register 5 for ip bustimeout (buserror) 04 timer compare register 5 for ip bustime- out (buserror) 08 table 16.7 register 5 for ip bus time-out address map base address register 6 register name offset address effective address register 6 1800_0760 timer control register 6 for dram refresh (16-bits) 00 base + offset timer count register 6 for dram refresh 04 timer compare register 6 for dram refresh 08 table 16.8 register 6 for dram refresh address map base address register 7 register name offset address effective address register 7 1800_0770 timer control register 7 for warm reset (8-bits) 00 base + offset timer count register 7 for warm reset 04 timer compare register 7 for warm reset 08 table 16.9 register 7 for warm reset address map gate/count enable reserved 31 2 1 0 timer controller register mapping 79rc32334/332 user reference manual 16 - 5 june 4, 2002 notes timer count register timers are reset to 0x0000_0000 and count up to and equal to the value in their respective compare register. for the 1 clock of compare, tc_n is assert ed. the output pin for timers 0 and 1 are synchronized (delayed) by one clock. the count then rolls back to 0x0000_0000. figure 16.4 count register fields timer compare register each of rc32334?s eight timers count on each syste m clock, beginning from zero and time out after reaching a programmable compare value, resetting back to zero automatically. figure 16.5 compare register fields bit name description 1 gate/count note that the gate option requires that the tc_n_gate_n pin first be set to the input direction. chapter 15 contains more programming specifics of the pio direction register. 0 enable enabled or disabled timers with this bit. table 16.10 timer controller register field descriptions bit name description 31:0 timer count value of 32-, 16- or 8- bit wide count table 16.11 count register fields descriptions bit name description 31:0 timer compare value of 32-, 16- or 8-bit wide compare table 16.12 compare register fields descriptions value description 1 gated count 0 timer count (default) value description 1 enabled (default) 0 disabled current value of the count 31 0 value of compare 31 0 timer controller timing diagrams 79rc32334/332 user reference manual 16 - 6 june 4, 2002 notes timing diagrams figure 16.6 timer rollover causing timer_tc_n to toggle figure 16.7 timer_gate_n input causing timer to count 1 2 3 4 5 fff ffff_fffe ffff_ffff 0000_0000 0000_0001 0000_0002 tdo15, tdo15, cpu_masterclk (internal compare_reg0[31:0]) (internal count_reg0[31:0]) timer_tc_n[0] tdoh6 tdoh6 1 2 3 4 5 0000_0001 0000_0001 0000_0002 0000_0002 0000_0002 thld10 tsu8 thld10 tsu8 cpu_masterclk timer_gate_n[0] (internal count_reg0[31:0]) notes 79rc32334/332 user reference manual 17 - 1 june 4, 2002 chapter 17 uart controller introduction the two uarts 1 in the rc32334 are 16550 compatible. the 16550 uart is an enhanced version of the 16450 uart. functionally similar to the 16450, at pow er-up, the uarts can be put into the 16550 mode, which then relieves the cpu core of software over head. this allows execution of 16450 or 16550 compat- ible software. two sets of 16-byte buffers are enabled during the 16550 mode: one set in the receive data path and one set in the transmit data path. at any time during operation, the cpu core can read the uart status information, which includes the type and condition of the transfer operation as well as an y error condition (parity, ov errun, framing, or break interrupt). a baud rate generator is included that di vides down the system clock by 1 to 65k. the baud rate generator provides the 16x clock for driving the transmitter and receiver l ogic. uart 0 is a full featured 16550 that supports the following features. 16-bit independent programmable bit rate generator baud rates from dc to 1.5m 16 byte tx fifo 16 byte rx fifo programmable data format ? 5, 6, 7, or 8 data bit ? odd, even or no parity ? 1, 1 1/2 or 2 stop bits modem control signal for channel 0 2 ? rts, cts, dtr, dsr maskable interrupt conditions receive data available ? receive line status ? transmit holding register empty ? modem status uart 1 2 does not include flow control support, suppor ting only data transmit and receive pins. it is otherwise software compatible with uart 0. uart 0 registers begin at address location 0x18000800. uart 1 registers begin at address location 0x18000820. block diagram figure 17.1 uart block diagram 1. there is only one uart in the rc32332. 2. not in the rc32332. transmit receive baud rate uart tx uart rx registers and control address data interrupts generator buffer buffer engine engine uart controller overview 79rc32334/332 user reference manual 17 - 2 june 4, 2002 notes overview the rc32334 provides two independent uarts, each wi th a serial data transmit output and a serial data receive input. these uarts each contain a 16-byte transmit buffer and a 16-byte receive buffer in the 16550 mode, a one-byte transmit holding register and a one-byte receive holding register. data flow through the buffers only if enabled in the buffer control register. the user must set up the uart before operation. the transmit and receive parameters are set in the line control register. the baud rate can also be set in the divisor latch most and divisor latch least registers. the 16550 buffer mode may be enabled, if desired, in the buffer control register, and should be chosen after reset is applied. note that dynamically altering the buffer mode during a transmit or receive is not supported. the uart contains a baud rate generator, and both t he transmit and receive engines will run at the baud rate determined by the divisor latches. the di visor latches determine the baud rate by a two-byte divisor that divides down the rc32334 system clock. t he divisor, in binary, loads into the divisor latch least and divisor latch most registers. a divisor value of one will disable the system clock di vider, and the transmit and re ceive circuits will run at the system frequency. a divisor value of zero is modified to a divisor of 32 decimal (0020 hex) by the baud rate generator. to calculate the baud rate, use the following formula (the constant, 16, is used in the formula because the output frequency of the baud rate generator is 16 times the baud): baud rate = (system fr equency) / (divisor * 16) or, to calculate the divisor to load into the divisor latches, use the following formula: divisor = system frequency / (baud rate * 16) example of a baud rate calculation: for a system frequency of 66 mhz and a baud rate of 9600 (values shown are decimal), calc ulate the divisor as follows: divisor = 66,000,000 / (9600 * 16) = 429.6875 round off the ideal divisor to the nearest whole number, 430, and convert 430 to binary. load 0000_0001_1010_1110 into the divisor latches: 0000_0001 into the most, and 1010_1110 into the least. some divisors and system fre quencies will give a more accurate baud rate than others. examples of other divisor values for typical baud rates are shown in table 17.1. to calculate the percent error of the divisor, use the following formula: percent error = ((difference of the whole divisor us ed and the ideal fractional divisor) / ideal fractional divisor) * 100. example of percent error calculation: ((430 - 429.6875) / 429.6875)) * 100 = 0.073% error. system frequency baud rate divisor (decimal) 75mhz 9600 488 75mhz 75 65535 75mhz 1.5 3 66mhz 19200 214 66mhz 9600 430 66mhz 2400 1719 50mhz 9600 326 40mhz 9600 260 33mhz 9600 215 25mhz 9600 163 table 17.1 divisor value examples for typical baud rates. uart controller user interrupts 79rc32334/332 user reference manual 17 - 3 june 4, 2002 notes the user can employ two methods of transmitter empty and receive by te ready notification: interrupt driven or polling. also, by using the bcr dma mode, the transmitter full and receive full conditions are available via the interrupt pending register in the expansion interrupt controller described in chapter 14. uart operation to transmit a byte, the user writes a byte of data to the transmit holding register. the uart controls inserting parity and the stop bit, then serially outputs t he byte of data at the selected baud rate. when a byte of received data is ready for reading, the uart will notify the user with an interrupt, if enabled, through the line status register. the byte of data is then read from the receive holding register by the rc32300 cpu core. receive errors are revealed to the user at the appropriate time (see the line status register). user interrupts in the rc32334 interrupt controller, there is one inte rrupt available to the user, which, unless masked, will activate the rc32334 interrupt pin to the cpu core (see figure 17.2, interrupt flow). the prioritized interrupt is bit (0) in the iir, it is inverted then passed to the rc32334 interrupt controller. it must be cleared in the uart first, then cleared in the rc32334 interrupt controller. interrupt 0 - prioritized interrupt. activated when one of the conditions in the ier is enabled. this is bit (0) in the iir, inverted and sent to the interrupt controller. masking it in the ier will prohibit it from being active in both the iir and the interrupt c ontroller. masking it in the interrupt controller will still prohibit the interrupt from being active in the interrupt controller and downstream to the cpu; however, the iir must still be cleared. interrupt 1 - tx rdy. transmit ready. see bcr dma mode for full description. interrupt 2 - rx rdy. receive ready. see bcr dma mode for full description. figure 17.2 interrupt flow signal definitions pin name type description uart interface uart_rx[0] i uart0 serial data in uart_tx[0] o uart0 serial data out uart_dsr_n[0] 1 i uart0 data set ready uart_cts_n[0] 1 i uart0 clear to send uart_rts_n[0] 1 o uart0 request to send table 17.2 rc32334 pin descriptions (part 1 of 2) enable ier iir uart mask mask pending rc32300 cpu prioritized interrupt cpu interrupt interrupt controller rc32334 core rx rdy tx rdy 2 1 0 uart controller signal definitions 79rc32334/332 user reference manual 17 - 4 june 4, 2002 notes uart 0&1 registers these registers enable uart functionality such as interrupt indication, data flow modes, and data receive/transmit formats. some addresses are used more than once. to accomplish this, some register bits control register selection. the rc32332 has only one serial port (uart0). all feat ures in this user manual referencing uart1 should be ignored if the designer is planning to use the rc32332. additionally, for uart0, all of the modem signals that were bonded out to the external pads in the rc32334?request to send (rts), clear to send (cts), data terminal ready (dtr), and data set ready (dsr)?are not accessible on the rc32332 pins. therefore, the programming of thes e bits in the modem control regist ers does not perform any usable func- tion in the rc32332. uart 0 registers uart 1 registers 1 uart_dtr_n[0] 1 o uart0 data terminal ready uart_rx[1] 1 i uart1 serial data in uart_tx[1] 1 o uart1 serial data out 1. not in the rc32332. address register name descriptions 1800_0800 rbr/thr receiver buffer register/transmitter holding register 1800_0804 ier interrupt enable register 1800_0800 dll baud divisor latch, ls 1800_0804 dlm baud divisor latch, ms 1800_0808 iir/bcr interrupt identity register/buffer control register 1800_080c lcr line control register 1800_0810 mcr modem control register 1800_0814 lsr line status register 1800_0818 msr modem status register 1800_081c scr scratch register 1800_0840 rr reset register table 17.3 uart0 register address map 1. not in the rc32332. address register name descriptions 1800_0820 rbr/thr receiver buffer register/transmitter holding register 1800_0824 ier interrupt enable register 1800_0820 dll baud divisor latch, 8 lsb 1800_0824 dlm baud divisor latch, 8 msb 1800_0828 iir/bcr interrupt identity register/buffer control register table 17.4 uart1 register address map (part 1 of 2) pin name type description table 17.2 rc32334 pin descriptions (part 2 of 2) uart controller signal definitions 79rc32334/332 user reference manual 17 - 5 june 4, 2002 notes receive buffer register (rbr) this is a read-only register, accessed when the dlab bit in the line control register is set to zero. bit 0 is the lsb and is the first bit serially received. figure 17.3 receive buffer register transmit buffer register (tbr) this is a write-only register, accessed when the dlab bit in the line control register is set to zero. bit 0 is the lsb and is the first bit serially transmitted. figure 17.4 transmit buffer register interrupt enable register (ier) this is a read/write register, accessed when the dlab bi t in the lcr is set to zero. disabling an interrupt in the ier prevents it from being indicated active in the iir and from activating the interrupt signal to the interrupt controller. figure 17.5 interrupt enable register 1800_082c lcr line control register 1800_0830 mcr modem control register 1800_0834 lsr line status register 1800_0838 msr modem status register 1800_083c scr scratch register 1800_0860 rr reset register address register name descriptions table 17.4 uart1 register address map (part 2 of 2) rx data 7 0 tx data 7 0 reserved rda thre msc 7 4 3 2 1 0 rls uart controller signal definitions 79rc32334/332 user reference manual 17 - 6 june 4, 2002 notes divisor latch least register (dll) this read/write register is accessed when the dlab bit in the line control register is set to one. writing to the dll or dlm will immediately change the baud ra te. see table 17.1 for additional baud rate informa- tion. figure 17.6 divisor latch least register (dll) divisor latch most register (dlm) this read/write register is accessed when the dlab bit in the line control register is set to one. writing to the dll or dlm will immediately change the baud ra te. see table 17.1 for additional baud rate informa- tion. figure 17.7 divisor latc h most register (dlm) interrupt identity register (iir) this is a read-only register. the ua rt encodes four levels of priority and indicates the code in the iir. when the software accesses the iir, all interrupts ar e frozen and the highest pending interrupt is indicated in this register. the uart continues to record new interrupts while this access is taking place but does not change the contents of the iir until the current access is complete. figure 17.8 interrupt identity register bit field name description initial value 7:4 reserved 0x0 3 msc 1 = enable modem status change interrupt 0 = disable interrupt 0x0 2 rls 1 = enable receiver line status interrupt 0 = disable interrupt in the 16550 mode, enables character timeout interrupt. 0x0 1 thre 1 = enable transmitter holding register empty interrupt 0 = disable interrupt 0x0 0 rda 1 = enable received data available interrupt 0 = disable interrupt 0x0 table 17.5 interrupt enable register field descriptions the least significant baud divisor bits 7 0 the most significant baud divisor bits 7 0 reserved ip current interrupt 16550 buffer mode 7 6 5 4 3 1 0 uart controller signal definitions 79rc32334/332 user reference manual 17 - 7 june 4, 2002 notes bit field name description initial value 7:6 16550 buffer mode these two bits are set to ?1? when bcr(0) is set to ?1? 0x0 5:4 reserved 0x0 3:1 current interrupt a code describing the highest priority interrupt pending. note that bit 3 is set to a ?1? in the 16550 buffer mode only. 0x0 0 interrupt pending this bit is inverted and mirrored in the rc32334 interrupt controller. this bit is active low in the iir and active high in the interrupt controller. 0x0 0x1 table 17.6 interrupt identity register fields and descriptions value status 1 enable 16550 buffer mode 0 disable 16550 buffer mode value status priority level 000 modem status fourth (lowest) 001 transmitter holding register empty writing to the thr will reset this interrupt third 010 received data available rx data are available to read or the specified trigger level is reached. either reading the rbr or if the buffer level drops below the trigger point resets the interrupt. the trigger level is specified in the bcr. second 011 receiver line status occurs during an overrun error, pa rity error, framing error, or break interrupt. reading the lsr resets the interrupt. first (highest) 100 reserved 101 reserved 110 character timeout indication no characters have been removed from or input to the receiver buffer during the last four character times and there is at least 1 character in it during this time. buffer mode only. second 111 receiver line status occurs during an overrun error, pa rity error, framing error, or break interrupt. reading the lsr resets the interrupt. first (highest) value status 1 no interrupt pending 0 interrupt pending uart controller signal definitions 79rc32334/332 user reference manual 17 - 8 june 4, 2002 notes buffer control register (bcr) the bcr register is a write-only register that enables and controls the use of the 16-byte receive and 16-byte transmit buffers. figure 17.9 buffer control register (bcr) fields note: changing from fifo mode to non-fifo mode does not automatically flush the fifo. switching fifo modes dynamic ally while sending or receiving data is not supported. bit field name description initial value 7:6 receive buffer byte status the receive buffer interrupt trigger level describes how many bytes are in the receive buffer. the setting of these bits affects the iir. 0x0 5:4 reserved 0x0 3 dma mode the txrdy and rxrdy signals go to the interrupt controller, where they can act as an interrupt to the cpu. masking these signals can only be accomplished in the interrupt controller 0x0 2 transmit buffer pointer a one resets the transmit buffer pointer 0x0 1 receive buffer pointer a one resets the receive buffer pointer 0x0 0 receive/trans- mit buffers enables the 16-byte transmit and receive buffers for 16550 mode operation. when switching between 16550 and 16450 modes, always reset the buffers. 0x1 table 17.7 buffer control register field descriptions tx/rx dma mode rx buffer pointer buffer pointer tx buffers reserved rx buffer byte status 7 6 5 4 3 2 1 0 value status 11 14 bytes in the receive buffer 10 8 bytes in the receive buffer 01 4 bytes in the receive buffer 00 1 byte in the receive buffer value status 1 txrdy is activated when there are no bytes in the 16-byte buffer and is deactivated only when the buffer is full (16 bytes have been written to the buffer). rxrdy is activated when there are 16 bytes in the buffer and is deactivated only when the buffer is empty. 0 txrdy is activated when there are no bytes in the buffer and is deactivated when there is at least one byte in the buffer. rxrdy is activated when there is at least one byte in the buffer and is deacti- vated only when the buffer is empty. uart controller signal definitions 79rc32334/332 user reference manual 17 - 9 june 4, 2002 notes line control register (lcr) the lcr is a read/write register that controls the format of the data received and transmitted. figure 17.10 line control register fields modem control register (mcr) this is a read/write register that controls the modem operation. for uart0, the data terminal ready (dtr) and request to send (rts) bits in the modem stat us register for this uart are muxed with pio pins of the rc32334 device. for uart1, none of the modem signals in the related modem status register are connected to the external pins and, ther efore, do not perform any usable function. 1 bit field name description initial value 7 divisor latch access bit 0 = rbr,thr and ier registers selected 1 = dll and dlm registers selected 0x0 6 set break control 0 = normal transmit data 1 = transmit data will be forced to a zero (spacing state), causing a break condition to be transmitted 0x0 5 stick parity control 0x0 4 parity select 1 = even parity 0 = odd parity 0x0 3 parity generation and checking 1 = enable parity generation and checking 0 = disable parity generation and checking 0x0 2 stop bits controls the number of stop bits generated 0x0 1:0 word length 0x0 table 17.8 line control re gister field descriptions 1. for uart0 in the rc32332, no modem signals are connected to external pins and therefore do not perform any usable function. also, uart1 is not present in the rc32332. word length stick parity control set break dlab 7 6 5 4 3 2 1 0 control parity and checking generation stop bits parity select bit value status 5:3 111 parity bit transmitted and checked as a zero 5:3 101 parity is transmitted and checked as a one 5 0 stick parity disabled value status 0 one stop bit generated 1 5-bit word length: 1 1/2 stop bits generated 6, 7 or 8-bit word length: 2 stop bits generated value status 00 5-bits 01 6-bits 10 7-bits 11 8-bits uart controller signal definitions 79rc32334/332 user reference manual 17 - 10 june 4, 2002 notes refer to chapter 15, ?programmable i/o (pio) c ontroller,? to configur e these signals to be enabled externally. figure 17.11 modem control register fields line status register (lsr) the lsr is a read/write register that prov ides uart status information to software. figure 17.12 line status register fields bit field name description initial value 7:5 reserved 0x0 4 loopback mode 1 = enable loopback mode for diagnostic testing of the uart in this mode, the transmit data pin is internally directed to the receiver logic, replacing the receive data input of the cpu 0 = disable loopback 0x0 3 out 2 no connection to pin 0x0 2 out 1 no connection to pin 0x0 1 request to send connected to pin b1, uart_rts_n[0] 0x0 0 data terminal ready connected to pin c3, uart_dtr_n[0] 0x0 table 17.9 modem control re gister field descriptions bit field name description initial value 7 receive error 1 = receive error detected on a character in the buffer a receive error could be parity, framing, or break conditions 0 = no receive error 0x0 6 transmit engine status 1 = transmit engine is not active this means that the transmit buffer and the thr are both empty 0 = transmit transfer in progress 0x1 5 thr empty 1 = transmit holding register is empty 0 = thr not empty 0x1 4 break interrupt 1 = receive data is at the spacing (zero) level for more than a full word transmission time the bit is reset when software reads the lsr. the error is regis- tered in the lsr when the associated character is at the top of the buffer in the 16550 buffer mode 0 = no break interrupt 0x0 table 17.10 line status register field descriptions (part 1 of 2) dtr rts out 1 out 2 loopback mode reserved 7 5 4 3 2 1 0 data overrun error parity error framing error break thr empty receive error tx engine status ready interrupt 7 6 5 4 3 2 1 0 uart controller signal definitions 79rc32334/332 user reference manual 17 - 11 june 4, 2002 notes modem status register (msr) the msr is a read/write register that controls modem operation. for uart0, the data set ready (dsr) and clear to send (cts) bits in the modem stat us register for this uart are connected to the external pins of the rc32334 device. for uart1, none of the modem signals in the related modem status register are connected to the external pins and, therefore, do not perform any usable function. 1 figure 17.13 modem status register fields 3 framing error 1 = received data did not have a valid stop bit the bit is reset when software reads the lsr. the error is regis- tered in the lsr when the associated character is at the top of the buffer in the 16550 buffer mode 0 = no framing error 0x0 2 parity error 1 = parity indication of the received data does not match the con- figuration in the lcr the bit is reset when software reads the lsr. the error is regis- tered in the lsr when the associated character is at the top of the buffer in the 16550 buffer mode 0 = no parity error 0x0 1 overrun error 1 = the data in the receive buffer were overwritten before the cpu read them this error is registered in the lsr as it occurs 0 = no overrun error 0x0 0 data ready 1 = at least one byte of data is ready to read 0 = no data in thr or receive buffer 0x0 1. for uart0 in the rc32332, no modem signals are connected to external pins and therefore do not perform any usable function. also, uart1 is not present in the rc32332. bit field name description 7 data carrier detect no connection to pins 6 ring indicator no connection to pins 5 data set ready connected to pin b2, uart_dsr_n[0] 4 clear to send connected to pin a1, uart_cts_n[0] 3 delta data carrier detect no connection to pins 2 trailing edge of ring indicator no connection to pins 1 delta data set ready no connection to pins 0 delta clear to send no connection to pins table 17.11 modem status register field descriptions bit field name description initial value table 17.10 line status register field descriptions (part 2 of 2) dcts ddsr cts dsr dcd teri ri ddcd 7 6 5 4 3 2 1 0 uart controller timing diagram 79rc32334/332 user reference manual 17 - 12 june 4, 2002 notes scratch register (scr) the scr is a read/write register that can be used as temporary storage by the user and has no affect on the uart operation. figure 17.14 scratch register field reset register (rr) writing any data value to this register will reset the uart channel. figure 17.15 reset register field timing diagram timing of the uart inputs and outputs are shown in figure 17.16. note that the uart data setup/hold protocol itself implies asynchronous timing. uar t_rx[0] and uart_tx[0] are shown in an input and output respectively. the other uart signals, including uart_ rx[1:0], uart_tx[1:0], uart_dsr_n[0], uart_cts_n[0], uart_rts_n[0], and uart_dtr_n[0] have simila r timing in their input and output modes. figure 17.16 uart timing bit field name description initial value 7:0 data bits this register has no effect on uart operation and can be used as temporary storage 0x0 table 17.12 scratch register field descriptions data bits 7 0 reset register 31 0 1 2 3 4 5 tdo16, tdoh8 tdo16, tdoh8 thld9 tsu7 cpu_masterclk uart_rx[0] uart_tx[0] notes 79rc32334/332 user reference manual 18 - 1 june 4, 2002 chapter 18 serial peripheral interface introduction the rc32334 supports the serial peripheral interface ( spi) master capability, to provide an interface to low-cost serial peripherals. this interface uses four pins: serial data in (spi_miso), serial data out (spi_mosi), serial clock (s pi_sck) and slave chip select (spi_ss_n) , as shown in figure 18.1. this serial interface includes an 8-bit shift register, a system clock divider, a sck generator, 4 registers, and a state machine. the spi interface provides the following features and capabilities: full-duplex operation master modes only system clock to spi clock divider/prescalar four programmable ma ster mode frequencies serial clock with programmable polarity and phase write collision error flag figure 18.1 spi block diagram the master spi allows fully duplexed, synch ronous serial communication between the rc32334 and other peripheral devices, such as an atmel spi or serial e2proms. when an spi transfer occurs, an 8- bit data is shifted out of spi_mosi, simultaneously as an 8-bit data is shifted into spi_miso. when a master device transmits data to a slave devic e via the spi_mosi line, the slave device responds by sending data to the master device via the master?s spi_miso line. this implie s full duplex transmission, with both data out and data in synchronized with the same clock signal. thus, the byte transmitted is replaced by the byte received and eliminates the n eed for separate transmit-empt y and receiver-full status bits. a single status bit (spif) is used to signify that the i/o operation has been completed. spi_block_with_ip ip_bus ip slave interface status/control dataout/in spi_block datain[31:0] dataout[31:0] slave_datain[31:0] slave_dataout[31:0] data_in[] data_out[] spi_sck, spi_ss_n, spi_mosi spi_miso state shifter i/o formatter machine baud rate generator serial peripheral interface signal descriptions 79rc32334/332 user reference manual 18 - 2 june 4, 2002 notes the spi is double-buffered on read, but not on write. if a write is performed during data transfer, the transfer occurs uninterrupted, and the write will be unsuccessful. this c ondition will cause the write collision (wcol) status bit in the spsr to be set. after a data byte is shifted, the spif flag of the spsr is set. the spi_sck pin is an output pin that idles high or low, depending on the cpol bit in the spcr, until data is written to the shift register, at which point eight clocks are generated to shift the 8 bits of data, and then spi_sck goes idle again. signal descriptions the rc32334?s spi module initiates a transmission by wr iting to the spi data register (spdr), which moves the data to a shift register and transmission immediatel y begins. after eight serial clock cycles, the spi sets the spi flag (spif) and transmission ends. before the spi begins another transmission, spif mu st be cleared by reading the spi status register and then the spdr. interrupts are generated at the end of a transmission, if the spi interrupt enable bit has been set. figure 18.4 lists and descri bes the spi control register fiel ds. serial clock polarity and phase. the rc32334?s spi controller does not implement the spi slave mode or spi multimastering. signal name type alternate signal name description spi_mosi i/o pio[10] spi data output serial mode: output pin from rc32334 as an input to a serial chip for the serial data input stream. in pci satellite mode, acts as an output pin from rc32334 that connects as an input to a serial chip for the serial data input stream for loading pci configuration registers in the rc32334 reset initialization vector pci boot mode. defaults to the output direction at reset time. 1st alternate function: pio[10]. 2nd alternate function: pci_eeprom_mdo. spi_miso i/o pio[7] spi data input serial mode: input pin to rc32334 from the output of a serial chip for the serial data output stream. in pci satellite mode, acts as an input pin from rc32334 that connects as an output to a serial chip for the serial data output stream for loading pci configuration registers in the rc32334 reset initialization vector pci boot mode. defaults to input direction at reset time. 1st alternate function: pio[7]. 2nd alternate function: pci_eeprom_mdi. spi_sck i/o pio[9] spi clock serial mode: output pin for serial clock. in pci satellite mode, acts as an output pin for serial clock for loading pci configuration registers in the rc323334 reset initialization vector pci boot mode. defaults to the output direction at reset time. 1st alternate function: pio[9]. 2nd alternate function: pci_eeprom_sk. spi_ss_n i/o pio[8] spi chip select output pin selecting the serial protocol device as opposed to the pci satellite mode eeprom device. alternate function: pio[8]. defaults to the output direction at reset time. table 18.1 spi signal descriptions serial peripheral interface spi setup and register descriptions 79rc32334/332 user reference manual 18 - 3 june 4, 2002 notes most peripherals require a multibyte command sequenc e. for multibyte commands, the spi_ss_n pin must be programmed via the general purpose pio out put data mode to remain asserted through the multiple bytes. to accommodate the various serial communication requirements of peripheral devices, soft- ware can change the phase and polarit y of the spi serial clock. the clock polarity bit (cpol) and the clock phase bit (cpha), both in the spcr, control the timing rela- tionship between the serial clock and the transmitted dat a. most typical peripherals use either the (0,0) mode or the (1,1) mode, where (cpol cpha) indicate the mode figure 18.2 serial peripheral interface (spi) clock/data timing spi data setup/hold and delay timing the spi protocol specifies its data input and output timing relative to spi_sck transitions. however, in reality, the rc32334 spi channel accepts input and deliv ers output data, based on the cpu_masterclk rising edge, immediately after a spi_sck tr ansition. thus, if the spi setup and hold time is met relative to spi_sck?since spi_sck is much slower than cpu_masterclk?the setup and hold to the spi_sck enabled cpu_masterclk input latch will also be met. similarly, if the spi slave devic e latches data with spi_sck, since spi_sck is much slower than c pu_masterclk, the setup (and hold) to the slave is also met. spi setup and register descriptions msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb spi_sck (cpol=0) spi_sck (cpol=1) sample input data output (cpha=1) sample input data output (cpha=0) spi_ss serial peripheral interface spi setup and register descriptions 79rc32334/332 user reference manual 18 - 4 june 4, 2002 notes the following describes the typical setup of spi, which occurs during boot time: 1. the spi shares data and clock pins with the pci eeprom if the rc32334 is booted in the boot- from-pci reset mode. an internal pci eeprom bu sy flag in the pci controller is used by the pci controller to determine if the pci is finished loading its data from the pci eeprom. the rc32334 internal pci eeprom busy flag automat ically switches the pin effect usage to spi in all boot reset modes by the time of the first instruction fetch after a cpu reset. note: even if the pci is not used, spi usage still requi res the pci to assert pci_rst_n in order to properly set the internal pci eeprom busy flag. 2. spi signal functions are routed via the pio controll er, so the pio controller will generally be initial- ized to the effect mode, with corresponding direct ion for each spi pin. at reset time, the default effect mode and direction are set up for the pci eeprom and also for spi. 3. the spi clock register, spcnt, is written. 4. the spi control register, spcntl, including the spe enable bit is written. 5. the data being sent to the spi slave are written to the spi data register (spdr). 6. the spi controller will initiate the hardware pr otocol on the spi pins. the protocol has the master receive data from the slave at the same time the master sends data to the slave. 7. wait either for: ? spi interrupt. after receiving an spi interrupt via the interrupt controller, read the spi status register spif and modf flags. ? poll the spi status register spif and modf flags. 8. if the spif flag is set, indicating the transaction is complete, reading the spi status register resets the spif flag. 9. read the data from the spi data register. 10. repeat steps 5 through 10, as needed. spi interrupt description spi produces a single interrupt. before feeding into the interrupt controller, the interrupt is enabled/ disabled via the spie interrupt enable bit in the spi control register (spcntl). spi asserts the interrupt line if either the spif and/or the modf bit of the spi status register is set, indicating an unusual slave (mis-)operation or that the pr esent transaction is complete. by disabling spi, via the spi control register spe bi t, the spi signal pins may be reused for other func- tions, including general purpose progra mmable i/o pins, or for bit-bl asting the pci eeprom after pci initialization; for example, to write to the pci eeprom. serial peripheral clock register (spcnt) the spcnt register is used to program the divide- down clock count prescalar, which then goes to the basic spi clock divisor controlled by the spcntl regi ster spr field. the spcnt register is used as a compare value to count the number of system clocks (cpu_masterclks) per 0.5 spi divide-down/prescalar clock. the default is 0x00. spi_sck = system clock / [2*(spcnt+1) * spr] base address register offset address effective address 1800_0900 serial peripheral clock divisor/prescalar register (spcnt) 00 base + offset serial peripheral control register (spcntl) 04 serial peripheral stat us register (spsr) 08 serial peripheral data i/o register (spdr) 0c table 18.2 spi register address map serial peripheral interface spi setup and register descriptions 79rc32334/332 user reference manual 18 - 5 june 4, 2002 notes figure 18.3 spi clock register field serial peripheral control register (spcntl) spi enables features and interrupts through the serial peripheral control register, i.e., the slave mode rates, clock phase and polarity, master/slave state, as listed in table 18.4. fiel ds of the spcntl register are shown in figure 18.4. the default is 0x10. figure 18.4 serial peripheral c ontrol (spcntl) register fields bits field function 7:0 spcnt used to divide the system clock to the 1-4 mhz input clock rate required for spi. table 18.3 spi clock register (spcnt) field description bits field description 7 spie interrupt enable 6 spe system on/off 5 reserved 4 mstr master/slave mode 3 cpol clock polarity. when the clock polarity bit is cleared and data is not being transferred, a steady state low value is produced at the sck pin of the master device. conversely, if this bit is set, the sck pin will idle high. this bit is also used in conjunction with the clock phase control bit to pro- duce the desired clock-data relationship between master and slave. table 18.4 spi control register field descriptions (part 1 of 2) spcnt 7 0 7 6 5 4 3 2 1 0 spie spe reserved mstr cpol cpha spr value description 0 spi interrupts are disabled (default) 1 spi interrupts are enabled if spif is set to one value description 0 spi system is off (default) 1 spi system is on value description 0reserved 1 spi is configured as a master (default) value description 0 spi_sck pin at logic zero between transmissions (default) 1 spi_sck pin at logic one between transmissions serial peripheral interface spi setup and register descriptions 79rc32334/332 user reference manual 18 - 6 june 4, 2002 notes serial peripheral status register (spsr) note that during a transfer, writing to the spdr regi ster (see table 18.6) causes a write collision error and sets the wcol bit of the status register. clear the wcol bit by reading the status register (spsr) with the wcol bit set, and then reading or writing t he spi data i/o register. the default is 0x80. figure 18.5 spi status register (spsr) fields 2 cpha the clock phase bit, in conjunction with cpol bit, controls the clock-data relationship between master and slave. the cpol bit can be thought of as simply inserting an inverter in series with the spi_sck line. the cpha bit selects one of two fundamentally different clocking protocols. 1:0 spr these two bits select one of the following four bit rates when rc32334 is a master. these bits have no effect when in slave mode. bits field description 7 spif spi transfer complete flag the serial peripheral data transfer flag bit is set upon completion of data transfer between the proces- sor and external device. if spif goes high, and the spie is set, a serial peripheral interrupt is gener- ated. clearing the spif bit is ac complished by reading the spsr (with spif set), followed by an access of the spdr. unless spsr is read (with spif set) first, attemp ts to write to spdr are inhibited. table 18.5 spi status register (spsr) field descriptions bits field description table 18.4 spi control register field descriptions (part 2 of 2) value description 0 first edge on spi_sck latches data (default) 1 edge following first edge on spi_sck latches data value description 00 divided by 2 (default) 01 divided by 4 10 divided by 16 11 divided by 32 7 6 5 4 3 0 spif wcol reserved modf reserved value description 0 ready to transfer 1 transfer complete. spdr writes inhibited. serial peripheral interface spi setup and register descriptions 79rc32334/332 user reference manual 18 - 7 june 4, 2002 notes serial peripheral data i/o register (spdr) the serial peripheral data i/o regi ster is used to transmit and receive data on the serial bus. only a write to this register will initiate trans mission/reception of another byte, and this will only occur in the master device. at the completion of transmitting a byte of dat a, the spif status bit is set in both the master and slave devices. when the user reads the serial peri pheral data i/o register, a buffer is actually being read. the first spif must be cleared by the time a second transfer of data from the shift register to the read buffer is initiated or an overrun condition will exist. in cases of overrun, the byte that causes the overrun is lost. a write to the serial peripheral dat a i/o register is not buffered and pl aces data directly into the shift register for transmission. figure 18.6 spi data i/o register 6 wcol write collision the write collision bit is set when an attempt is made to write to the serial peripheral data register while data transfer is taking place. clearing th e wcol bit is accomplished by reading the spsr (with wcol set), followed by an access to spdr. 5reserved 4 modf master error flag asserts an error condition if a write to the spdr is done while the spi interface is in non-master (slave) mode. refer to the mstr field in table 18.4 for more information on the master mode. clear- ing the modf bit is accomp lished by optionally readin g the spsr first, followed by a srite of "1" to the spcr mstr field. 3:0 reserved bits field description 7:0 spdr spi data i/o register a write to this register with the transmit data value automatically initiates simultaneous transmis- sion and reception of data. at the completion of data transfer, the spif status bit is set and the spsr register is read. then the receive data can be read from this register. table 18.6 spi data i/o register (spdr) field description bits field description table 18.5 spi status register (spsr) field descriptions value description 0normal 1 an attempt to write to spi while a transfer was in progress. the write is ignored. value description 0normal 1 this is an error condition. spdr 7 0 serial peripheral interface master programming example 79rc32334/332 user reference manual 18 - 8 june 4, 2002 notes interface to spi serial e2proms by atmel (at25128) figure 18.7 illustration of glueless connection between rc32334 processor and atmel spi serial e2proms master programming example the following sequence initializes the spi to run at 2m hz (for this example, as sume the system clock is running at 67 mhz). 1. write spcnt register with 0x0000_0008. this will divide the internal spi clock down to 3.7mhz (67/ [(8+1)*2]). 2. write spcr register with 0x0000_00f0. spie = 1, spi interrupt enabled. spe=1, enable spi for transmission. mstr=1, this bit is always programmed to 1, since rc32334 spi only supports master mode. use (0,0) mode where cpol=0, clock is low when spi is not active. cpha=0, latch data on the first active edge. spr[1:0]=0, divi de internal clock by 2 to generate spi clock (3.7 / 2 = 1.85mhz). 3. write interrupt mask register 14 (0x 1800_05e4) with 0x0000_0001. enable spi-generated system interrupt. 4. read spsr and spdr to clear spif bit. 5. assert spi_ss_n by using the spi_ss_n pin in its general purpose pio output mode and setting its data low. 6. write spdr with the value to trans mit to start the spi transmission. 7. wait until the spi interrupt occurs, the inte rrupt routine will perfo rm the following step: 8. read spsr. make sure there is no error condition. 9. read spdr. get the receive value from spdr, wh ich clears the spif bit in the spsr register. 10. write spi interrupt clear register (0x 1800_05e8) with 0x0000_0001. clear spi interrupt pending register. 11. if finished with a (multi-) byte command s equence (i.e., a read command/address byte 1/address byte 2/data 4-byte sequence), then de-assert the spi_ss_n pin via the pio data register. 12. repeat steps 5 - 11 as needed. timing diagrams timing of the spi clock-to-data output relationship is shown in figure 18.8, and timing of the relation- ship of clock-to-data input is shown in figure 18.9. note that the spi data setup/hold protocol itself implies 0.5 spi_sck clock setup/hold relative to the master and slave devices. hold cs so si sck wp at m e l spi serial e2proms at25128 spi_ss_n spi_miso spi_mosi spi_sck vdd rc32334 vdo spi master spi slave serial peripheral interface timing diagrams 79rc32334/332 user reference manual 18 - 9 june 4, 2002 notes figure 18.8 spi clock-to-data output relationship figure 18.9 spi clock-to-data input relationship 1 2 3 4 5 tdo16, tdoh9 tdo16, tdoh9 cpu_masterclk spi_sck spi_mosi 1 2 3 4 5 tdo16, tdoh9 thld9 tsu7 cpu_masterclk spi_sck spi_miso serial peripheral interface timing diagrams 79rc32334/332 user reference manual 18 - 10 june 4, 2002 notes notes 79rc32334/332 user reference manual 19 - 1 june 4, 2002 chapter 19 clocking, reset, and initialization introduction this chapter provides a description of the cl ock signals (?clocks?) that are used on the rc32334 processor. for a discussion of t he basic system clocks and system timing parameters, see chapter 8. signal terminology in this chapter and throughout the manual, when describ ing signal transitions, t he following terminology is used: rising edge indicates a low-to-h igh (0 to 1) transition. falling edge indicates a high-to -low (1 to 0) transition. clock-to-q delay is the amount of time it takes for a signal to move from the input of a device (clock) to the output of the device (q). these terms are illustrated in figure 19.1 and figure 19.2. figure 19.1 signal transitions figure 19.2 clock-to-q delay basic system clocks the rc32334 processor has a single input clock, cpu_masterclk. cpu_masterclk the cpu_masterclk input must meet the maximum rise time (t mcrise ), maximum fall time (t mcfall ), minimum clock high (t mckhigh ) time, minimum clock low (t mcklow ) time, and input jitter (t jitterin ) parame- ters for proper phase locked loop (pll) operation. 1 2 3 4 high-to-low transition low-to-high transition single clock cycle clock input q data in data out clock-to-q delay clocking, reset, and initialization phase-locked loop (pll) operation 79rc32334/332 user reference manual 19 - 2 june 4, 2002 notes the processor bases all internal clocking on the single cpu_masterclk ( mclk ) input signal. the rc32334 uses cpu_masterclk to sample data at the system interface and to clock data into the processor system interface output register. the external agent should use c pu_masterclk for the global system clock and for clocking the output registers of an external agent. figure 19.3 shows t he input, output and hold time parameters measured at the midpoint of the rising clock edge. figure 19.3 system clocks data setup, output, and hold timing pclock by multiplying cpu_masterclk 2, 3, or 4 times (p rogrammed during the reset or initialization sequence through the clock multiplier configuration mode bits), the processor generates the internal pipeline clock rate, pclock, which is used by a ll internal registers and latches. figure 19.4 shows the clocks for a cpu_mas terclk-to-pclock multiply by 2. figure 19.4 timing illustration of cpu_masterclk-to-pclock multiply by 2 phase-locked loop (pll) operation the processor aligns the pipeline cl ock, pclock, to the cpu_mastercl k by using an internal phase-locked loop (pll) circuit that generates aligned clocks. by t heir nature, pll circuits are only capable of generating aligned clocks for cpu_masterclk frequencies within a limited range. clocks generated using pll circuits contain some inherent inaccuracy , or jitter; a clock aligned with cpu_masterclk by the pll can lead or trail cpu_masterclk by as much as the maximum clock jitter specified in the clock parameters table in the data sheet for this device. pll components and operation the storage capacitor required for the phase- locked loop circuit is contained in the rc32334. however, it is recommended that the system designer provide a filter network of passive components for the pll power supply. the phase locked loop circuit requires several pas sive components for proper operation, which are connected to vcc, vss, vccp, and vssp, as illustrated in figure 19.5. t ds t dh t do cpu_masterclk input output t doh cycle 1 2 3 4 cpu_masterclk t mckhigh t mcklow t mckp pclock clocking, reset, and initialization pll analog power filtering 79rc32334/332 user reference manual 19 - 3 june 4, 2002 notes figure 19.5 pll passive components it is essential to isolate the analog power and ground for the pll circuit ( vccp / vssp ) from the regular power and ground ( vcc / vss ). initial evaluations have yielded good results with the following values: c1 = 1 nf c2 = 3.3 f c3 = 10 f because the optimum values for the filt er components depend upon the application and the system noise environment, these values shou ld be considered as starting points for further experimentation within your specific application. pll analog power filtering for noisy module environments, a filt er circuit of the following form is recommended as shown in figure 19.6. figure 19.6 pll filter circuit for noisy environments reset function the rc32334 reset uses the cpu_coldreset_n input signal: power-on reset starts when the power supply is turned on and completely re-initializes the internal state machine of the processor without saving any state information. then, the modebit[9:0]are read, and the processor allows its internal phas e locked loops to lock, stabilizing the processor internal clock. after the internal clock is stabiliz ed, the reset exception will be taken. the timing of the cold reset signal is illustrated in figure 19.7. vcc vccp vssp vss cpu board rc32334 c1 c2 note: c1, c2, c3 are board caps. c3 10 uf 0.1 uf 100 pf vcc vss vccp vssp 10 ohm clocking, reset, and initialization reset function 79rc32334/332 user reference manual 19 - 4 june 4, 2002 notes reset and initialization interface during the reset sequence, the cpu rc32300 core of the rc32334 obtains configuration information using its mode configuration inte rface. the initialization val ues for the rc32334 are obtained from ejtag_pcst [2:0], mem_addr [19:17], debug_cpu_i_d_n, debug_cpu_ads_n, debug_cpu_dma_n and debug_cpu_ack_n signals which are modebit[9:0] during the power-on reset. the modebit[9:0] are latched with the rising edge (negating edge) of the cpu_coldreset _n signal. timing of the mode configuration inter- face reset sequence is shown in figure 19.7. additi onal system controller c onfiguration information is obtained from mem_addr[22:20] as explained in section reset of on-chip system controller logic later in this chapter. the boot-mode configuration settings are listed in table 19.1. figure 19.7 mode configurat ion interface reset sequence boot-mode configuration settings pin mode bit description value mode setting ejtag_pcst[2:0] 2:0 msb (2) clock multiplier cpu_masterclk is multiplied internally to generate pclock 0 multiply by 2 1 multiply by 3 2 multiply by 4 3reserved 4reserved 5reserved 6reserved 7reserved debug_cpu_i_d_n 3 endbit 0 little-endian ordering 1 big-endian ordering debug_cpu_ack_n 4 reserved 0 debug_cpu_ads_n 5 reserved 0 debug_cpu_dma_n 6 tmrinten enables/disables the timer interrupt on cpu_int_n[5] 0 enables timer interrupt 1 disables timer interrupt table 19.1 boot-mode configur ation settings (part 1 of 2) vcc cpu_coldreset_n modebit[9:0] >= 110 ms cpu_masterclk >= 10 ms (mclk) 120 ms clocking, reset, and initialization reset function 79rc32334/332 user reference manual 19 - 5 june 4, 2002 notes reset_boot_mode settings the rc32334 reset-boot mode initialization setting va lues and mode descriptions are listed in table 19.2. pci_host_mode settings during reset initialization, the rc32334?s pci interface can be set to the satellite or host mode settings. when set to the host mode, the cpu must configur e the rc32334?s pci configuration registers, including the read-only registers. if the rc32334?s pci is in the pci-boot mode satellite mode, read-only configura- tion registers are loaded by the serial eeprom. reset of on-chip system controller logic for the on-chip system logic, the reset sequenc e occurs in conjunction with the rc32300 cpu core reset sequence described above. on power up, cpu_col dreset_n is asserted. when cpu_coldreset_n is de- asserted, the rc32300 cpu core reset vector mode bits are latched in. this is followed by the reset vector from the on-chip system peripherals being latched in. after cpu_coldreset_n de- asserts, the cpu_reset_n signal is provided, back to the rc32300 cpu core and remains asserted for 256 clocks. after cpu_reset_n de-asserts, the cpu will firs t issue the reset boot address at physical address 0x1fc0_0000, then initiate a boot memory cycle using mem_cs_n[0] set to 32 wait-states. the rc32334 uses mem_addr[22:17] to read in part of the reset vect or. as shown in figure 19.8, mem_addr[22:17] is tri- stated during coldreset and continues to be tri-stated until the 2nd clock after cpu_reset_n de-asserts. typi- cally, the system uses pull-up or pull-down resistors of 5k ohm to select the reset initialization vector when cpu_coldreset_n de-asserts. mem_addr[17] 7 reserved for future use. 1 mem_addr[19:18] 9:8 msb (9) boot-prom width specifies the memory port width of the memory space which contains the boot prom. 00 8 bits 01 16 bits 10 32 bits 11 reserved mem_addr[22:21] mem_addr[20] description 1 1 x tri-state memory bus and eeprom bus during coldreset_n assertion. 1 0 x reserved 0 1 1 pci-boot mode (pci_host_mode must be in satellite mode) rc32334 will reset either from a cold reset or from a pci reset. boot code is provided via pci. pci is initialized via the pci eerom. 0 1 0 not allowed 0 0 1 standard-boot mode (satellite mode) boot from the rc32334?s memory controller (typical system). serial eeprom not supported. 0 0 0 standard-boot mode (host mode) boot from the rc32334?s memory controller (typical system). serial eeprom not supported. table 19.2 rc32334 reset_boot_mode initialization settings pin mode bit description value mode setting table 19.1 boot-mode configur ation settings (part 2 of 2) clocking, reset, and initialization reset function 79rc32334/332 user reference manual 19 - 6 june 4, 2002 notes figure 19.8 reset vector initialization part 1 of 2 the rc32334 usually drives debug_c pu_i_d_n, debug_cpu_ads_n, debug_cpu_dma_n, and debug_cpu_ack_n. during boot time, these four debug signal s are used as reset initialization vector bits. thus, the rc32334 tri-states these four debug signals duri ng the assertion of cpu_coldreset_n, as shown in figure 19.9. during coldreset, the system c an pull-up or pull-down these four debug signals. figure 19.9 reset vector initialization part 2 of 2 coldreset memaddr latched 256 clks warmreset memaddr valid driven by system/pullups/pulldowns 'b000 driven by r c rv driven by system/pullups/pulldowns 'b000 driven by r c tp thld10 tsu10 tsu22 thld22 thld21 tsu21 cpu_masterclk cpu_coldreset_n e set_n (internal_signal) mem_addr[22:20] mem_addr[19:17] coldreset riv 256 clocks warm reset riv driven by rc32334 riv driven by rc32334 riv driven by rc32334 riv driven by rc32334 riv driven by rc32334 tdo20, tdoh20 tdo20, tdoh20 tdo20, tdoh20 tdo20, tdoh20 tdo20, tdoh20 tdoh20 thld20 tsu20 thld21 tsu21 cpu_masterclk cpu_coldreset_n cpu_reset_n debug_cpu_ads_n debug_cpu_ack_n debug_cpu_dma_n debug_cpu_i_d_n ejtag_pcst[2:0] (internal signal) notes 79rc32334/332 user reference manual 20 - 1 june 4, 2002 chapter 20 jtag boundary scan introduction as previously described, the rc32334 is a logical integration of both the rc32364 standalone cpu and the rc32134 system controller. because each of these discrete devices includes a tap controller, there are 2 tap controllers on the rc32334, one for the cpu core (referred to as the rc32300 cpu core tap controller), described in the next chapter, and one for sy stem logic controller, described in this chapter. the system controller tap controller is used to provide conventional standard jtag boundary scan access to the rc32334 pin interface. the rc32300 cpu co re tap controller is used to provide access to the ejtag interface on the cpu core. the two tap controllers are connected in parallel as shown in figure 20.1 and share the jtag control pins, except for separate jtag_tms and ejtag_tms pins. t hus at least one of the two tap controllers must be in test-logic-reset at any given time, so that the jtag_tdo pin is only actively being driven from no more than one of the tap controllers. for example, if neither tap controller is in use, they both can be reset by asserting jtag_trst_n, or by asserting both jtag_tms and ejtag_tms high for 5 consecutive jtag_tck clocks. if the rc32300 cpu core tap controller is to be used, t hen the system controller tap controller must be reset by asserting jtag_tms high for 5 consecutive jtag_t ck clocks. if the system controller tap controller is to be used, then the rc32300 cpu core tap controller must be reset by asserting ejtag_tms high for 5 consecutive jtag_tck clocks. the rc32300 cpu core tap controller is one of t he two tap controllers on the rc32334. as such, the rc32300 cpu core tap controller is used prim arily for ejtag support, si nce many ejtag functions are accessed via the rc32300 cpu core tap controller jtag port. note that the boundary scan register for the internal cpu co re must never be used, as it will access internally connected cpu core ports/pins. instead the system controller tap contro ller boundary scan register is provided for rc32334 conventional jtag pin access, control, and boundary scan. figure 20.1 dual tap controller block diagram boundary scan cells system controller tap cpu core tap ejtag jtag_tck, jtag_tdi, jtag_tms ejtag_tms jtag_tdo boundary scan cells boundary scan cells boundary scan cells jtag_trst_n jtag boundary scan system logic tap controller overview 79rc32334/332 user reference manual 20 - 2 june 4, 2002 notes system logic tap controller overview the system logic utilizes a 16-state, four-bit tap c ontroller, a four-bit instruction register, and five dedi- cated pins to perform a variety of functions. the primary use of the jtag tap controller state machine is to allow the five external jtag control pins to cont rol and access the rc32334's m any external signal pins. the jtag tap controller can also be used for identif ying the device part number. the jtag logic of the rc32334 is depicted in figure 20.2. figure 20.2 diagram of the jtag logic signal definitions jtag operations such as reset, state-transiti on control and clock sampling are handled through the signals listed in table 20.1. a functional overview on the tap controller and boundary scan registers is provided in the sections following the table. the system logic tap controller transitions from st ate to state, according to the value present on jtag_tms, as sampled on the rising edge of jtag_tck. t he test-logic reset state can be reached either by asserting jtag_trst_n or by applying a 1 to jtag_tms fo r five consecutive cycles of jtag_tck. a state diagram for the tap controller appears in figure 20.3. the val ue next to state represent the value that must be applied to jtag_tms on the next rising edge of jtag_tck, to transition in the direction of the associated arrow. pin name type description jtag_trst_n input jtag reset asynchronous reset for jtag tap. jtag_tck input jtag clock test logic clock. jtag_tms and jtag_tdi are sampled on the rising edge. jtag_tdo is output on the falling edge. jtag_tms input jtag mode select requires an external pull-up. controls the state transitions for the tap controller state machine (internal pull-up). jtag_tdi input jtag input serial data input for bsc chain, instructio n register, idcode register, and bypass register (internal pull-up). jtag_tdo output jtag output serial data out. tri-stated except when shifting while in shift-dr and shift-ir tap con- troller states. table 20.1 jtag pin descriptions bypass register instruction register decoder 4-bit instruction register tap controller m u x m u x device id register boundary scan register jtag_tdi jtag_tms jtag_tck jtag_trst_n jtag_tdo jtag boundary scan test data register (dr) 79rc32334/332 user reference manual 20 - 3 june 4, 2002 notes figure 20.3 state diagram of rc32334?s tap controller test data register (dr) the test data register contains the following: the bypass register the boundary scan registers the device id register these registers are connected in parallel betw een a common serial input and a common serial data output, and are described in the following sections. for more detailed descriptions, refer to ieee standard test access port (ieee std. 1149.1-1990). boundary scan registers the rc32334 scan chain is 330 bits long and compri ses 171 logical elements--where each logical element represents a signal pin. the five jtag pi ns do not have scan elements associated with them, nor does the ejtag ejtag_tms pin. of the 171 logical elem ents, 125 are two-bit bidirectional cells, 33 are two- bit tri-statable outputs, and 14 are one-bit dedicated inputs. the rc32332 scan chain is 303 bits long, has 157 elem ents: 116 bidirectional, 30 outputs, 11 inputs. this boundary scan chain is connected between jt ag_tdi and jtag_tdo when the extest or sample/ preload instructions are selected. once extest is selected and the tap controller passes through the update-ir state, whatever value is currently held in the boundary scan register?s output latches is immedi- ately transferred to the corresponding outputs or output enables. therefore, the sample/preload instruction must first be used to load suitable values into the boundary scan cells, so that inappropriate values ar e not driven out onto the system pins. all of the boundary scan cells feature a negative edge latch, which guarantees that clock skew cannot cause incor- rect data to be latched into a cell. the input cells ar e sample-only cells. the simp lified logic configuration is shown in figure 20.4. test- logic reset run-test/ idle select- dr-scan capture-dr shift-dr exit1 -dr pause-dr exit2-dr select- ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-dr update-ir 11 0 0 0 1 1 0 0 1 1 0 1 0 1 0 0 1 1 1 0 0 11 0 1 0 1 1 0 00 0 jtag boundary scan test data register (dr) 79rc32334/332 user reference manual 20 - 4 june 4, 2002 notes figure 20.4 diagram of observe-only input cell the simplified logic configuration of t he output cells is shown in figure 20.5. figure 20.5 diagram of output cell the output enable cells are also bas ically output cells. the simp lified logic appears in figure 20.6. figure 20.6 diagram of output enable cell input pin shift_dr from previous cell clock_dr dq to next cell to core logic mux data from core data from previous cell shift_dr to next cell to output pad clock_dr update_dr mux d q dq extest mux dq d q from core data from previous cell extest to output enable clock_dr shift_dr update_dr output enable to next cell mux mux jtag boundary scan instr uction register (ir) 79rc32334/332 user reference manual 20 - 5 june 4, 2002 notes the bidirectional cells are composed of only two boundary scan cells. they contain one output enable cell and one capture cell, which contains only one register. the input to this single register is selected via a mux that is driven selected by the output enable cell and the extest mode. when the output enable cell is driving a high out to the pad (which enables the pad for output) and extest is disabled, the single capture register will be configured to capture from the output signal from the core to the pad. however, in the case where the output enable is lo w, signifying a tri-state c ondition at the pad, then the capture register will capture from the input from the pad. the configur ation is shown graphically in figure 20.7. figure 20.7 diagram of bidirectional cell instruction register (ir) the instruction register allows an instruction to be sh ifted serially into the processor at the rising edge of jtag_tck. the instruction is then used to select the test to be performed or the test register to be accessed, or both. the instruction shifted into the register is latched at the completion of the shifting process, when the tap controller is at the update-ir state. the instruction register contains four shift-register-based cells that can hold instruction data. these mandatory cells are located near the serial outputs and ar e the least significant bits . the values of the bits are 0 and 1 (1 is the least significant bit). this register is decoded to perform the following functions: to select test data registers that may operate wh ile the instruction is current. the other test data registers should not interfere with ch ip operation and selected data registers. to define the serial test data register path used to shift data between jtag_tdi and jtag_tdo during data register scanning. the instruction register is comprised of 4 bits to decode instructions as follows in table 20.2. instruction definition opcode extest mandatory instruction allowing the testing of board level interconnections. data is typ- ically loaded onto the latched parallel outputs of the boundary scan shift register using the sample/preload instruction prior to use of the extest instruction. extest will then hold these values on the outputs while being executed. also see the clamp instruction for similar capability. 0000 table 20.2 instructions supported by rc 32334?s jtag boundary scan (part 1 of 2) from previous cell output enable cell output enable from core extest output from core input to core capture cell to next cell i/o pin mux jtag boundary scan instr uction register (ir) 79rc32334/332 user reference manual 20 - 6 june 4, 2002 notes extest the external test (extest) instruction is used to control the boundary scan register, once it has been initialized using the sample/preload instruction. using extest, the user can then sample inputs from or load values onto the external pins of the rc32334. on ce this instruction is selected, the user then uses the shift-dr tap controller state to shift values into the boundary scan chain. when the tap controller passes through the update-dr state, these values w ill be latched onto the output pins or into the output enables. sample/preload the sample/preload instruction has a dual use. the prim ary use of this instruction is for preloading the boundary scan register prior to enabl ing the extest instruction. failure to preload will result in unknown random data being driven onto the output pins when extest is selected. the secondary function of sample/preload is for sampling the system state at a particular moment. using the sample function, the user can halt the device at a certain state and shift out the status of all of the pins and output enables at that time. bypass the bypass instruction is used to truncate the boundary scan register to a single bit in length. during system level use of the jtag, the boundary scan chains of all the devices on the board are connected in series. in order to facilitate rapid testing of a gi ven device, all other devices are put into bypass mode. sample/ preload mandatory instruction that allows data values to be loaded onto the latched parallel output of the boundary-scan shift register prior to selection of the other boundary- scan test instruction. the sample instruction allows a snapshot of data flowing from the system pins to the on-chip logic or vice versa. 0001 device_id provided to select device identification to read out manufacturers identity, part, and version number 0010 highz tri-states all output and bidirectional boundary scan cells. 0011 reserved behaviorally equivalent to the bypass instruction as per the ieee std. 1149.1 speci- fication. however, the us er is advised to use th e explicit bypass instruction. 0100 reserved 0101 reserved 0110 reserved 0111 clamp provides jtag user the option to bypass the part?s jtag controller while keeping the part outputs controlled similar to extest. 1000 unused the unused instru ctions are behaviora lly equivalent to the bypass instruction as per the ieee std. 1149.1 specification. however, the user is advised to use the explicit bypass instruction, as the inte rnal usage of these curr ently unused instructions could possibly vary in future implementations of the device. 1001 unused 1010 unused 1011 unused 1100 validate automatically loaded into the instruction register whenever the tap controller passes through the capture-ir state. the lower two bits ?01? are mandated by the ieee std. 1149.1 specification. 1101 unused same as other unused instructio ns above 1110 bypass the bypass instruction is us ed to truncate the boundary scan register as a single bit in length 1111 instruction definition opcode table 20.2 instructions supported by rc 32334?s jtag boundary scan (part 2 of 2) jtag boundary scan instr uction register (ir) 79rc32334/332 user reference manual 20 - 7 june 4, 2002 notes therefore, instead of having to shift 307 times to get a value through the rc32334, the user only needs to shift one time to get the value from jtag_tdi to jtag_tdo. when the tap controller passes through the capture-dr state, the value in the bypass register is updated to be 0. if the device being used does not have a device_id r egister, then the bypass instruction will automat- ically be selected into the instruction register whenever the tap controller is reset. therefore, the first value that will be shifted out of a device without a device_i d register is always 0. devices such as the rc32334 that include a device_id register will automatic ally load the device_id instruction when the tap controller is reset, and they will shift out an initial val ue of 1. this is done to allow the user to easily distin- guish between devices having device _id registers and those that do not. clamp this instruction, listed as optional in the ieee 1149.1 jtag specifications, allows the boundary scan chain outputs to be clamped to fixed values. when t he clamp instruction is issued, the scan chain will bypass the rc32334 and pass through to devic es further down the scan chain. deviceid the deviceid instruction is automatically loaded when the tap controller state machine is reset either by the use of the jtag_trst_n signal or by the applicat ion of a ?1? on jtag_tms for five or more cycles of jtag_tck as per the ieee std 1149.1 specification. the leas t significant bit of this value must always be 1. therefore, if a device has a device_id register, it will sh ift out a 1 on the first shift if it is brought directly to the shift-dr tap controller state after the tap c ontroller is reset. the board- level tester can then examine this bit and determine if the dev ice contains a device_id register (t he first bit is a 1), or if the device only contains a bypass r egister (the first bit is 0). however, even if the device contains a device_id r egister, it must also contain a bypass register. the only difference is that the bypass register will not be the default register selected during the tap controller reset. when the device_id instruction is active and the t ap controller is in the shift-dr state, the thirty- two bit value that will be shifted out of the device-id register is 0x10018067 . validate the validate instruction is automatically loaded into the instruction register whenever the tap controller passes through the capture-ir state. the lower two bits ?01? are mandated by the ieee std. 1149.1 specification. bit(s) mnemonic description r/w reset 0 reserved reserved 0x1 r 1 11:1 manuf_id manufacturer identity (11 bits) idt 0x33 r0x33 27:12 part_number part number (16 bits) this field identifies the part number of the processor derivative. for the rc32334 this value is: 0x0018 for the rc32332 this value is: 001ah rimpl. dep. 31:28 version version (4 bits) this field identifies the version number of the processor derivative. for the rc32334/rc32332, this value is 0x1 rimpl. dep. table 20.3 system controller device identification register version part number vendor id lsb 0001 0000|0000|0001|1000 0000|0110|011 1 figure 20.8 system controller device id instruction format jtag boundary scan usage considerations 79rc32334/332 user reference manual 20 - 8 june 4, 2002 notes reserved reserved instructions implement various test modes used in the device manufacturing process. the user should not enable these instructions. unused 1 the unused instructions are behaviorally equivalent to the bypass instruction as per the ieee std. 1149.1 specification. however, the user is advised to use the explicit bypass instruction as the internal usage of these currently unused instructions could possi bly vary in future implementations of the device. usage considerations as previously stated, there are internal pull-ups on jtag_trst_n, jtag_tms, and jtag_tdi. however, jtag_tck also needs to be driven to a known value. however, it is best to drive a zero on the jtag_tck pin when it is not in use or use an external pull-down resistor. in order to guarantee that the jtag does not interfere with normal system operation, the tap controller should be fo rced into the test-logic-reset controller state by continuously holding jtag_trst_n low and/or jtag_tms high when the chip is in normal operation. if jtag will not be used, externally pull-down jtag_trst_n low to disable it. 1. any unused instruction is defaul ted to the bypass instruction notes 79rc32334/332 user reference manual 21 - 1 june 4, 2002 chapter 21 ejtag (in-circuit emulator) interface introduction as previously described, the rc32334 is a logi cal integration of both the rc32364 stand-alone cpu and the rc32134 system controller. because each of t hese discrete devices includes a tap controller, there are 2 tap controllers on the rc32334, one for th e cpu core (referred to as the rc32300 cpu core tap controller), described in this chapter, and one fo r system logic controller, described in the previous chapter. the system logic controller tap controller is used to provide conventional standard jtag boundary scan access to the rc32334 pin interface. the rc32300 cpu core tap controller is used to provide access to the ejtag interface on the cpu core. t he ejtag version implemented in the rc32334 is 1.5.3. the two tap controllers are connected in parallel as shown in figure 21.1 and share the jtag control pins, except for separate jtag_tms and ejtag_tms pins. t hus at least one of the two tap controllers must be in test-logic-reset at any given time, so that the jtag_tdo pin is only actively being driven from no more than one of the tap controllers. thus for example, if nei ther tap controller is in use, they both can be reset by asserting jtag_trst_n, or by asserting both jtag_t ms and ejtag_tms high for 5 consecutive jtag_tck clocks. if the rc32300 cpu core tap controller is to be used, then the system controller tap controller must be reset by asserting jtag_tms high for 5 consecutive jtag_t ck clocks. if the system controller tap controller is to be used, then the rc32300 cpu core tap controller must be reset by asserting ejtag_tms high for 5 consecutive jtag_tck clocks. note that the boundary scan register for the in ternal cpu core must never be used, as it will access internally connected cpu core ports/pins. instead the system logic controller tap controller boundary scan register is provided for rc32334 conv entional jtag pin access, control, and boundary scan. figure 21.1 dual tap controller block diagram boundary scan cells system controller tap cpu core tap ejtag jtag_tck, jtag_tdi, jtag_tms ejtag_tms jtag_tdo boundary scan cells boundary scan cells boundary scan cells jtag_trst_n ejtag (in-circuit emulator) interface overview 79rc32334/332 user reference manual 21 - 2 june 4, 2002 notes on-chip support for low-cost in-circuit emulat ion (ice) equipment is featured on the rc32334. the rc32300 cpu core on the rc32334 implements the standard mips enhanced jtag (ejtag) interface, which includes the following key ice interface capabilities: breakpoints debug exception handlers execution trace capability overview the following features ar e supported by the ejtag: two additional instructions are added to the rc32300 cpu core: set software debug breakpoints (sdbbp) and return from debug exception (deret). the ejtag module doesn?t support si ngle step execution in hardware. however, it can be accom- plished in software. hardware breakpoints can be set at: ? virtual instruction address (with address bit masking) ? virtual data address (with address bit maski ng) and data value (with byte lane masking) ? physical processor core address (with lower add ress bit masking) and physical processor core data (with data bit masking) trace trigger points can be specified instead of ha rdware breakpoints. the trace trigger is limited by the max speed of the ejtag_dclk that the ejtag probe can sustain. debug breaks can be initiated by the ejtag probe via a jtag pin ( jtag_tdi / ejtag_dint_n ). pc trace information is provided by additi onal status pins and the processor clock. the ejtag unit on the rc32300 cpu core is used for debugging the state of the cpu core and is unaware of the peripherals around the core (memory c ontroller, dram controller, etc.) that are used to create the rc32334. to access the peripherals around t he cpu core, the ice probe must execute standard load and store instructions to interrogate the register contents of these modules. the block diagram of the ejtag unit on the rc32300 cpu is given in figure 21.2, and the simplified block diagram is shown in figure 21.3. the following main blocks provide debug functionality: instruction address match logic data address & data value match logic processor address bus & processor data bus match logic pc trace logic software debug breakpoint (sdbbp) instruction and debug exception return (deret) instruction debug registers ejtag (in-circuit emulator) interface block diagrams 79rc32334/332 user reference manual 21 - 3 june 4, 2002 notes block diagrams figure 21.2 block diagram figure 21.3 simplified ejtag block diagram debug support unit this section describes the ejtag debug support unit. it covers the debug instructions added to the rc32300 cpu core instruction set as well as support functions and registers for debugging. the debug unit is used to access the internal stat e of the rc32300 cpu core, through a standard jtag interface that is compatible with the ieee std. 1149.1 specification (refer to c hapter 20 in this manual for additional information). additional status pins (f or run-time and real-time data collection) along with m i ps core i nstructi on cache data cache i nstr. a ddress i nstr./data i nst r . dat a a ddress dat a r0 r31 hi lo pc stat us cause badva epc pri d desave debug depc alu/shifter on chip bus m/s interface pr oc. a ddr ess pr oc. d at a instruction address match logic data address & data value m atch l ogi c pr oc. a ddr ess bus & pr oc. d at a b us m atch l ogi c m i ps processor cor e d su sl av e i nt er f ace (r ead/ w r i t e d su r egi st ers) dsu on chip bus bus interface unit inst.addr.brk data brk or sst ep jta g brk debug excepti on excep. cntl sd bb p deret other ex cept i ons dm (debug mode) dm load data st ore d at a pc trace logic tpc pcst [2:0] dclk dm dsu or trace trigger trace trigger instr type inst.addr trigger data trigger dsu_tif dsu_tof tm set t i f rsttof dmaacc rstjtagbrk jt agrst proben doze prrst run real t i me clrrealtime rc 32300 core cpu core cpu core inst. addr bkpoint. inst. addr bkpoint. debug control unit debug control unit = data addr bkpoint. data addr bkpoint. = phys. addr bkpoint. phys. addr bkpoint. = jtag control jtag control to biu tdo tdi va 0000_0000 to ff00_0000 va ff00_0000 to ffff_ffff inst. va data va ejtag (in-circuit emulator) interface ejtag interface 79rc32334/332 user reference manual 21 - 4 june 4, 2002 notes external third-party hardware and software creates an enhanced jtag interface - referred to as ejtag - which provides a real-time debugging system. information on instructions that have been added to the mips isa instruction set and real-time debug- ging register descripti ons are also included. instruction address match logic if a match occurs between the processor?s virtual in struction address and the address value set in the instruction address break register, a debug excepti on is generated to the core and/or a trace trigger code is applied to the ejtag_pcst[2:0] lines. address bits can be excluded from comparison by setting mask bits in a mask register. data address & data value match logic if a match occurs between the processor?s virtual data address and the address value set in the data address break register, then a debug exception is generated to the core and/or a trace trigger code is applied to the ejtag_pcst[2:0] lines. status bits in t he debug register indicate l oad or store access. address bits can be excluded from com parison by setting mask bits in a mask register. processor address bus & processor data bus match logic if a match occurs between the processor?s physica l address bus and the address value set in the processor address bus break register and there is also a match between the processor?s accompanying data and the value in the processor data bus break register, then a debug exception is generated to the core and/or a trace trigger code is applied to the ej tag_pcst[2:0] lines. the lower 24 address bits can be excluded from comparison by setting mask bits in a ma sk register; the processor data bus bits can be excluded from comparison by setting mask bits in a mask register. the hardware match logic is not the only way to generate a debug exception. it can also be accom- plished by the sdbbp instruction and by the ejtag probe (through jtag). the cause of the debug exception can be found in status bits of the debug register. ejtag interface the ejtag interface consists of the standard jt ag signals (i.e. jtag_tck, jtag_tms, jtag_tdi, jtag_tdo, jtag-trst), extended with extra signals that provide real time program counter output. a description of the ejtag pins is shown in table 21.1. name type drive strength/ capability description jtag_tck input ? jtag test clock requires an external pull-down. an input test clock used to shift into or out of the boundary-scan register cells. jtag_tck is independent of the system and the processor clock with nominal 50% duty cycle. jtag_tdi, ejtag_dint_n input ? jtag test data in requires an external pull-up. on the rising edge of jtag_tck, serial input data are shifted into either the instruction or data register, depending on the tap controller state. during real mode, this input is used as an interrupt line to stop the debug unit from real time mode and return the debug unit back to run time mode (standard jtag). this pin is also used as the ejtag_dint_n signal in the ejtag mode. table 21.1 ejtag pins (part 1 of 2) ejtag (in-circuit emulator) interface ejtag interface 79rc32334/332 user reference manual 21 - 5 june 4, 2002 notes note: all input signals require pull-ups at the bonding pads per the jtag specifications. note: the sharing of the jtag pins for scan chai n and debug requires that the scan chain of the board, if used, is disconnected from the ejta g interface when it is being used for debugging. operating modes the rc32300 cpu core has two operating modes: normal mode and debug mode . the normal mode is when the processor is not executing the debug exception handler routine. jtag_tdo, ejtag_tpc output high jtag test data out the jtag_tdo is serial data shifted out from instruction or data register on the falling edge of jtag_tck. when no data is shifted out, the jtag_tdo is tri- stated. during real time mode, this signal provides a non-sequential pro- gram counter at the processor clock or at a division of processor clock. this pin is also used as the ejtag_tpc signal in the ejtag mode. jtag_tms input ? jtag test mode select requires an external pull-up. the logic signal received at the jtag_tms input is decoded by the tap con- troller to control test operation. jtag_tms is sampled on the rising edge of the jtag_tck. jtag_trst_n input ? jtag test reset the jtag_trst_n pin is an active-low signal for asynchronous reset of the debug unit, independent of the processor logic. an external pull-up on the board is recommended to meet the jtag specification in cases where the tester can not access this signal. however, specific systems ordinarily should either: 1) drive low this signal 2) use an external pull-down on the board 3) clock jtag_tclk ejtag_dclk output ? ejtag test clock processor clock. during real time mode, this signal is used to capture address and data from the ejtag_tpc signal at the processor clock speed or any division of the internal pipeline. ejtag_pcst[2:0] i/o low ejtag pc trace status information 111 (stl) pipe line stall 110 (jmp) branch/jump forms with pc output 101 (brt) branch/jump forms with no pc output 100 (exp) exception generated with an exception ve ctor code output 011 (seq) sequential performance 010 (tst) trace is outputted at pipeline stall time 001 (tsq) trace trigger output at performance time 000 (dbm) run debug mode alternate function: modebit[2:0]. ejtag_debugboot input ? ejtag debugboot requires an external pull-down. the ejtag_debugboot input is used during reset and forces the cpu core to take a debug exception at the end of the reset sequence instead of a reset exception. this enables the cpu to boot from the ice probe without having the external memory working. this input signal is level sensitive and is not latched internally. this signal will also set the jtagbrk bit in the jtag_control_register[12]. ejtag_tms input ? ejtag test mode select requires an external pull-up. the ejtag_tms is sampled on the rising edge of jtag_tck. name type drive strength/ capability description table 21.1 ejtag pins (part 2 of 2) ejtag (in-circuit emulator) interface ejtag interface 79rc32334/332 user reference manual 21 - 6 june 4, 2002 notes figure 21.4 shows a state diagram where the proces sor modes and the ejtag interface functions are indicated. the debug mode is entered after a debug exception (derived from hardware breakpoints, single step etc.) is taken and continues until the debug exception re turn (deret) has been executed. in this time the processor is executing the debug exception handler routine. in debug mode, the proben bit determines the debug e xception vector address: in case proben=0 the debug exception handler starts at 0xbfc0-0480 and a debug monitor program will be entered and executed through regular system memory. when pr oben=1, the debug exception vector address is 0xff20-0200 and a debug monitor program can be executed in a ?serial? way through the ejtag protocol. (in this case, the monitor program is located on the ejtag probe, not requiring any physical eprom on the target board). in debug mode mode the standard ieee 1149.1 test access port (tap) interface (referred to as jtag) is used to control the on-chip debug support unit blo ck (dsu). all operations such as read and write to internal registers, to external sy stem memories and to other on-chip peripherals is performed by the ejtag protocol. in this case, the pins jtag_tdi/ejtag_dint_n* and jtag_tdo/ejtag_tpc function as jtag_tdi input and jtag_tdo output. by executing a pc trace instruction, defined as an extended jtag instruction, the pc trace mode is entered. this can only be done in debug mode and when the ejtag probe is present (proben=1). prior to execution of the pc trace instruction the tap controll er must be placed in run-test/idle state by toggling the jtag_tms signal. in pc trace mode, program count er trace information is output via additional status pins in conjunction with the jtag pins jtag_tdi/e jtag_dint_n* and jtag_tdo/ejtag_tpc. these pins now func- tion as ejtag_dint_n* input and ejtag_tpc output. non-s equential program counter data is available at the jtag_tdo/ejtag_tpc pin clocked out at the processor s peed using the ejtag_dclk pin. the type of execution is available as status at the ejtag_pcst[2:0] pins. t he pc trace mode can be switched off by a debug excep- tion caused e.g. by a breakpoint or when the ejtag probe activates the interrupt signal at the jtag_tdi/ ejtag_dint_n* pin (which sets the jtagbrk bit in the ejtag_control_register[12]). when the pc trace mode is switched off by a debug exception, the jtag instru ction register will be set to the bypass code (0x1f). ejtag (in-circuit emulator) interface jtag operation 79rc32334/332 user reference manual 21 - 7 june 4, 2002 notes jtag operation figure 21.4 rc32334 debug operating modes test interface and boundary-scan architecture the ieee 1149.1 architecture is shown in the shaded part of figure 21.2. it consists of an instruction register, a bypass register, a device id register, an implementation regi ster and several user data regis- ters (like the ejtag address/data/cont rol registers) and a test interface referred to as a test access port (tap) controller. the instruction register and data registers ar e separate scan paths arr anged between the primary test data input (jtag_tdi) pin and primary test data out put (jtag_tdo) pin. this architecture allows the tap controller to select and shift data through one of the two types of scan paths, instruction or data, without accessing the other scan path. test access port operation the tap controller is controlled by the test clo ck (jtag_tck) and test mode select (ejtag_tms) inputs. these two inputs determine whether an instruction register scan or data register scan is performed. the tap consists of a small controller design, driven by the jtag_tck input, which responds to the ejtag_tms input as shown in the state diagram in figure 21. 5. the ieee 1149.1 test bus uses both clock edges of jtag_tck. jtag_tms and jtag_tdi are sampled on the risi ng edge of jtag_tck, while jtag_tdo changes on the fall the state diagram for the tap controller is shown in figure 21.5. debug mode normal mode pc = 0xbfc0 0480 pc trace mode off jtag_tdi/ejtag_dint_n pin: jtag_tdi input jtag_tdo/ejtag_tpc pin: jtag_tdo output dm = 1 (debug mode) "normal" memory execution no cpu access to probe mem. pc = 0xff20 0200 pc trace mode off tag_tdi/ejtag_dint_n pin: jtag_tdi input jtag_tdo/ejtag_tpc pin: jtag_tdo output dm = 1 (debug mode) cpu access probe memory . if ejtag pc trace inst.: pc trace mode on jtag_tdi/ejtag_dint_n pin: ejtag_dint_n jtag_tdo/ejtag_tpc pin: ejtag_tpc deret debug exception pc = application program no cpu access to probe mem. dm = 0 (normal mode) pc trace mode off jtag_tdi/ejtag_dint_n pin: jtag_tdi input jtag_tdo/ejtag_tpc pin: jtag_tdo output pc trace mode on jtag_tdi/ejtag_dint_n pin: ejtag_dint_n jtag_tdo/ejtag_tpc pin: ejtag_tpc output probeen=0 probeen=1 instruction ejtag (in-circuit emulator) interface jtag operation 79rc32334/332 user reference manual 21 - 8 june 4, 2002 notes figure 21.5 tap controller state diagram refer to ieee standard test access port (ieee std. 1149.1), for the full state diagram. the main state diagram consists of six steady stat es: test-logic-reset, run-te st/idle, shift-dr, pause- dr, shift-ir, and pause-ir. a unique feature of this pr otocol is that only one steady state exists for the condition when jtag_tms is set high: the test-logic-reset state. this means that a reset of the test logic can be achieved within five jtag_tck(s) or less by setting the jtag_tms input high. at power up or during normal operation of the proces sor, the tap is forced into the test-logic-reset state by driving jtag_tms high and applying five or more jtag_tck(s). in this state, the tap issues a reset signal that places all test logic in a condition that does not impede norma l operation of the processor. when test access is required, a protocol is applied via the jtag_tms and jtag_tck inputs, causing the tap to exit the test-logic-reset state and move through the appropr iate states. from the run-test/idle state, an instruction register scan or a data register scan can be issued to transition the tap through the appro- priate states shown in figure 21.5. the states of the data and instruction register scan blocks are mirror images of each other adding symmetry to the protocol sequences. the first action that occurs when either bloc k is entered is a capture operation. for the data registers, the capture-dr st ate is used to capture (or parallel load) the data into the selected serial data path. in the instruction register , the capture-ir state is used to capture status infor- mation into the instruction register. from the capture state, the tap transitions to either the shift or exit1 state. normally the shift state follows the capture state so that test data or stat us information can be shifted out for inspection and new data shifted in. following the shift state, the tap eit her returns to the run-test/idle state via the exit1 and update states or enters the pause state via exit1. the reason for entering the paus e state is to temporarily suspend the shifting of data through either the data or instruction register while a required operation, such as refilling a host memory buffer, is performed. from t he pause state shifting can resume by re-entering the shift state via the exit2 state or terminated by ent ering the run-test/idle state via the exit2 and update states. test- logic reset run-test/ idle select- dr-scan capture-dr shift-dr exit1 -dr pause-dr exit2-dr select- ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-dr update-ir 11 0 0 0 1 1 0 0 1 1 0 1 0 1 0 0 1 1 1 0 0 11 0 1 0 1 1 0 00 0 ejtag (in-circuit emulator) interface jtag operation 79rc32334/332 user reference manual 21 - 9 june 4, 2002 notes upon entering the data or instruction register sc an blocks, shadow latches in the selected scan path are forced to hold their present state during the capt ure and shift operations. the data being shifted into the selected scan path is not output through the s hadow latch until the tap enters the update-dr or update-ir state. the update state c auses the shadow latches to update (or parallel load) with the new data that has been shifted into the selected scan path. li mitations of tap controller are rc32300 cpu core as part of the rc32334. tap controller state assignments all state transitions within the tap controller oc cur at the rising edge of the tclk pulse and?depending on the jtag_tms signal level (0 or 1)?it proceeds to the next state. test-logic-reset ? the test logic is disabled so that normal operat ion of the on-chip system logic can continue unhin- dered. run-test/idle ? a controller state between scan operations. select-dr-scan ? this is a temporary controller state in which all test data registers selected by the current instruc- tion retain their previous state. capture-dr ? in this controller state, data may be parallel-loaded into test data registers selected by the current instruction on the riding edge of tclk. shift-dr ? in this controller state, the test data regist er connected between jtag_tdi and jtag_tdo, as a result of the current instruction, shifts data one stage towards its serial output on each rising edge of tclk. the test data register content is being sh ifted out serially, lsb first, at the falling edge of tclk towards the jtag_tdo output. exit1-dr ? this is a temporary controller state. if jtag_t ms is held high, a rising edge applied to tclk while in this state causes the controller to enter the update-dr state, which terminates the scanning process. if jtag_tms is held low and a rising edge is applied to tclk, the controller enters the pause-dr state. pause-dr ? this controller state allows shifting of the test data register in the serial path between jtag_tdi and jtag_tdo to be temporarily halted. exit2-dr ? this is a temporary controller state. if jtag_t ms is held high and a rising edge is applied to tclk while in this state, the scanning process termi nates and the tap controller enters the update-dr state. update-dr ? data is latched onto the parallel output of these te st data registers from t he shift-register path on the falling edge of tclk. select-ir-scan ? this is a temporary controller state in which all test data registers selected by the current instruc- tion retain their previous state. capture-ir ? in this controller state, the shift-register contained in the instruction register loads a pattern of fixed logic values on the rising edge to tclk. shift-ir ? in this controller state, the shift-register cont ained in the instruction r egister is connected between jtag_tdi and jtag_tdo and shifts data one stage towards its serial output on each rising edge to tclk. the instruction shift register content is bei ng shifted out serially, lsb first, at the falling edge of tclk towards the jtag_tdo output. ejtag (in-circuit emulator) interface jtag operation 79rc32334/332 user reference manual 21 - 10 june 4, 2002 notes exit1-ir ? this is a temporary controller state. while in this state, if jtag_tms is held high, a rising edge applied to tclk causes the controller to enter the update-dr state, which terminates the scan- ning process. if jtag_tms is held low and a rising edge is applied to tclk, the controller enters the pause-dr state. pause-ir ? this controller state allows shifting of the instruction register to be halted temporarily. exit2-ir ? this is a temporary controller state. while in this state, if jtag_tms is held high and rising edge is applied to tclk termination of the scanning proc ess occurs. the tap controller then enters the update-ir controller state. if jtag_tms is hel d low and a rising edge is applied to tclk, the controller enters the shift-ir state. update-ir ? the instruction shifted into the instruction regist er is latched to the parallel output from the shift- register path on the falling edge of tclk, in this controller state. once the new instruction has been latched, it becomes the current instruction. instruction register (ir) the instruction register is responsible for prov iding the address and control signals required to access a particular data register in the scan path. the inst ruction register is accessed when the tap receives an instruction register scan protocol. during an instruction register scan operation, the tap controller selects the output of the instruction register to drive the tdo pin. the instructi on register consists of an instruc- tion shift register and an instruction shadow latch. the inst ruction shift register consists of a series of shift register bits arranged to form a single scan path between tdi and tdo. during instruction register scan operations, the tap controls the instruction shift regi ster to capture status information and shift data from tdi to tdo. both the capture and shift operations occur on the rising edge of tck; however, the data shifted out from the tdo occurs on the falling edge of tck. the status inputs ar e user-defined observability inputs, except for the two least si gnificant bits, which are always 01 for scan-path testing purposes. (the instruction register has a minimum length of two bits.) in the test-logic-reset state, the instruction shift register is set to all ones. this forces the device into the functional mode and selects the bypass register (or the device identification register if one is present). the instruction shadow register c onsists of a series of latches, one latch for each instruction shift register bit. during an instruction regi ster scan operation, the latches remain in their present state. at the end of the instruction register scan operation, t he instruction register update input updates the latches with the new instruction installed in the instruction sh ift register. in the test-logic-reset state, the latches are set to all ones. test data register (dr) the ieee 1149.1 standard requires two data regist ers: boundary-scan register and bypass register, with a third, optional, device identification regist er. additional user-defi ned data registers may be included. the data registers are arranged in parallel fr om the primary tdi input to the primary tdo output. the instruction register supplies the address that allo ws one of the data registers to be accessed during a data register scan operation. during a data register scan operation, the address ed scan register receives tap control signals to pre-load test response and shift data from tdi to tdo. during a data register scan operation, the tap selects the output of the data regi ster to drive the tdo pin. when one scan path in the data register is being accessed, all other scan paths remain in their present state. however, additional specific test data registers are available for va rious operations during run-time and real-time debugging. these registers are connected in parallel between a common serial input and a common serial data output. the following sections provide a brief description of these elements. for a complete description, refer to ieee standard test access port (ieee std. 1149.1 - 1990). ejtag (in-circuit emulator) interface jtag operation 79rc32334/332 user reference manual 21 - 11 june 4, 2002 notes bypass register the bypass register is used to allow test data to flow through the device from tdi to tdo. it contains a single-stage shift register for a minimum length in se rial path. when an instruction selects the bypass register and the tap controller is in the capture-dr stat e, the shift register stage is set to a logic zero on the rising edge of tclk. bypass register operations should not have any effect on the device?s operation in response to the bypass instruction. boundary scan register the boundary scan register allows serial data to be loaded into or read out of the processor input/ output ports. the boundary scan register is a part of the ieee 1149.1 - 1990 standard jtag implementa- tion. the boundary scan register for the in ternal cpu core must never be used. device identification register the device identification register is an optional register defined by i eee 1149.1, to identify the device's manufacturer, part number, revision, and other device-s pecific information. table 21.2 shows the bit assign- ments defined for the (read only) device identificati on register. these bits can be scanned out of the iden- tification register after being selected. although the de vice identification register is optional, ieee 1149.1 specification has dedicated an instruction to select th is register. the device identification register is selected when the instruction register is loaded with the idcode instruction. . implementation register this is a 32-bit read only register to identify the features of the debug support unit which are imple- mented by the rc32334. bit(s) mnemonic description r/w reset 0 reserved reserved 0x1 r 1 11:1 manuf_id manufacturer identity (11 bits) idt 0x33 r0x33 27:12 part_number part number (16 bits) this field identifies the part number of the processor derivative. for the rc32300 cpu core, this value is: 0x0026 rimpl. dep. 31:28 version version (4 bits) this field identifies the version number of the processor derivative. for the rc32300 cpu core, this value is 0x0 rimpl. dep. table 21.2 cpu core device identification register version part number vendor id lsb 0000 0000|0000|0010|0110 0000|0110|011 1 figure 21.6 cpu core device id instruction format ejtag (in-circuit emulator) interface jtag operation 79rc32334/332 user reference manual 21 - 12 june 4, 2002 notes bit(s) mnemonic description r/w reset 0 mips32/64 mips 32-bit or 64 indicates the type of mips cpu, informing the width of the mips cpu datapath, the debug registers implemented in the dsu, and the ejtag_data_register. 0: 32-bit wide data registers 1: 64-bit wide data registers set to 0 for rc32334 r0 4..1 ch[3:0] number of break channels : these 4 bits used to indicate the number of break channels implemented in the dsu. debug sw should check instrbrk, databrk and procbrk to know what break types are implemented. 0000 = no break channels 0001 = 1 break channel (default) ... 1111 = 15 break channels r0001 5 noinstbrk instruction address break : this bit indicates if the instruction address break function is implemented in the dsu. 0: instruction address break is implemented 1: instruction address break is not implemented r0 6 nodatabrk data address break : this bit indicates if the data address break function is implemented in the dsu. 0: data address break is implemented 1: data address break is not implemented r0 7 noprocbrk processor bus break : this bit indicates if the processor bus break function is implemented in the dsu. 0: processor bus break is implemented 1: processor bus break is not implemented r0 10..8 pcstw pcst width and dclk division factor 000,111 3 bits (dclk is 1/1 of cpu pipeline clk) 001 6 bits (dclk is 1/2 of cpu pipeline clk) 010 9 bits (dclk is 1/3 of cpu pipeline clk) 011 12 bits (dclk is 1/4 of cpu pipeline clk) others reserved r000 13..11 tpcw tpc width 000,111 1 bit 000 is standard ejtag 001 2 bits reserved 010 4 bits reserved 011 8 bits reserved others reserved r000 14 nodma no ejtag dma support 0: ejtag dma is supported by implementation 1: ejtag dma is not supported by implementation r1 15 nopctrace no pc trace support 0: pc trace is supported by implementation 1: pc trace is not supported by implementation r0 16 mips16 mips16 support 0: mips cpu does not support mips16 1: mips cpu supports mips16 r0 17 icachec instruction cache coherency 0: instruction cache does not keep dma coherency 1: instruction cache keeps coherency with dma r0 18 dcachec data cache coherency 0: data cache does not keep coherency with dma 1: data cache keeps coherency with dma r0 table 21.3 implementation register (part 1 of 2) ejtag (in-circuit emulator) interface jtag operation 79rc32334/332 user reference manual 21 - 13 june 4, 2002 notes ejtag address register the length of the ejtag address regist er is 32 bits. the length is identical to the length of the physical processor address bus, and is determined by shifting a pattern through the register. this register can be used as follows: processor access: in this mode the rc32334 can ac cess memory on the ejtag probe in a serial way through the jtag interface. a 32 bit address is captured and is shifted out via the jtag_tdo/ ejtag_tpc pin to the ejtag probe. depending on the dire ction of the access, data is shifted into the jtag_tdi pin (processor read) or shifted out of the jtag_tdo/ejtag_tpc pin (processor write). ejtag data register this register is used with the ejtag_ address_register in the following mode: processor access: in this mode the rc32334 can ac cess memory located on the ejtag probe in a serial way through the jtag interface. a 32 bit data word is captured and is shifted out via the jtag_tdo/ejtag_tpc pin to the ejtag probe for a processor write action; for a processor read action 32 bits of data is shifted into the jtag_tdi /ejtag_dint_n* pin and is m ade available to the pro- cessor. the organization of the bytes in the 32 bit ejtag data register depends on the endianess of the cpu, as shown in figure 21.7 and figure 21.8. figure 21.7 byte organization in a 32-bit ejtag data register 19 physaw physical address width informs the size of ejtag_address_register 0: physical addresses are 32-bit in length 1: physical addresses is from 33 to 64-bits in length the exact length of can be determined by shifting a pattern through the ejtag address register. r0 22..20 reserved reserved, ejtag probe must shift 0s in r 0 23 sdbbpcode sdbbp us es special2 opco de (for mips-i/ii/ii/iv) 0: sdbbp is encoded according to ejtag rw 1.3 specification 1: sdbbp is encoded using a special2 opcode r0 31..24 reserved reserved, ejtag probe must shift 0s in r 0 bit(s) mnemonic description r/w reset table 21.3 implementation register (part 2 of 2) least significant byte is at low est address w ord is addressed by byte address of least significant byte bit 31 23 24 15 16 8 7 0 a[n:0] = 4 lsb little-end ian bit 31 23 24 15 16 8 7 0 msb lsb msb a[n:0] = 0 5 6 7 3 2 1 a[n:2] = 0 a[n:2] = 1 a[n:0] = 7 6 5 4 a[n:0] = 3 2 1 0 a[n:2] = 0 a[n:2] = 1 big -end ian m o s t s ig n ific a n t b y t e is a t lo w e s t a d d r e s s w ord is addressed by byte address of m ost significant byte ejtag (in-circuit emulator) interface jtag operation 79rc32334/332 user reference manual 21 - 14 june 4, 2002 notes figure 21.8 examples of byte organi zation in a 32-bit ejtag data register ejtag control register this is a 32 bit register to control the various operations of the debug support and the jtag unit. this register is selected by shifting in the jtag_control_ir instruction. bits in the ejtag_control_register can be set/cleared by shifting in data; status is read by shifting out this register. this ejtag_control_register, shown in table 21. 4, can only be accessed by the jtag interface. bit(s) mnemonic description r/w reset 0 clken dclk output enable bit when this bit is set to 0 it disables the dclk output (making it high impedance or 0). when it is set to 1 it will enable the dclk output dur- ing real time tracing mode. r/w 0 1 unused this bit is always 0. w0/r 0 2 unused this bit is always 0. w1/r 0 3 brkst break status this bit is set to 1 when the processor takes a debug exception and is cleared when the processor executes the deret instruction. this bit is the same as the dm (debug mode) bit in debug register [30]. r 0 4 unused this bit is always 0. r/w 0 5 unused this bit is always 0. r/w 0 6 reserved r 0 8,7 dsz[1:0] unused these bits are always 00. r/w 00 table 21.4 ejtag_control_register (part 1 of 3) ejtag_data_reg bit 0 bit 31 bit 7 0 memory address 2 address 3 address 0 address 1 mips cpu litlle endian transfer size = byte ejtag_address_reg[1:0] = 11 dsz[1:0]=00 a b c d d ejtag_data_reg bit 0 bit 31 bit 7 0 memory address 2 address 3 address 0 address 1 mips cpu big endian transfer size = byte ejtag_address_reg[1:0 = 11 dsz[1:0]=00 a b c d d bit 0 ejtag_data_reg bit 31 bit 7 0 memory address 2 address 3 mips cpu big endian transfer size = half word ejtag_address_reg[1:0] = 10 dsz[1:0]=01 address 1 address 0 a b c d cd ejtag_data_reg bit 0 bit 31 bit 7 0 memory address 2 address 3 address 0 address 1 mips cpu litlle endian transfer size = byte ejtag_address_reg[1:0] = 00 dsz[1:0]=00 a b c d a ejtag_data_reg bit 0 bit 31 bit 7 0 memory address 2 address 3 address 0 address 1 mips cpu big endian transfer size = byte ejtag_address_reg[1:0] = 00 dsz[1:0]=00 a b c d a bit 0 ejtag_data_reg bit 31 bit 7 0 memory address 2 address 3 mips cpu little endian transfer size = half word ejtag_address_reg[1:0] = 10 dsz[1:0]=01 address 1 address 0 a b c d dc ejtag (in-circuit emulator) interface jtag operation 79rc32334/332 user reference manual 21 - 15 june 4, 2002 notes 9 unused this bit is always 0. r/w 0 10 unused this bit is always 0. r 0 11 unused this bit is always 0. w1/r 0 12 jtagbrk jtag break setting this bit to 1 causes a debug exception to the processor. this bit is also set by activating the jtag_tdi/ejtag_dint_n* pin (stopping the pc trace mode). when the debug exception occurs, the processor core will be waken up if it was in sleep mode. this bit is cleared by hardware when the debug exception is taken. jtag break is ignored if the cpu is in debug mode. w1/r 0 14..13 reserved reserved r 00 15 proben ejtag probe enable this bit must be set to 1 by the probe?s software to indicate that a probe is present and active. if it is set to 0, it indicates that the probe is not present or inactive and the ejtag module will not allow the processor to access the probe, and the result is undefined (may result in bus error). the clock at the dclk pin is disabled in this case. the debug exception is set at 0xbfc0-0480. r/w 0 16 prrst processor reset when this bit is set to 1, a soft reset exception is forced to the proces- sor. the reset is sustained as long as the prrst bit is 1. the processor will set the sr bit in the processor?s status register. the processor reset bit is not masked by mrst* in debug control register[1]. r/w 0 17 unused this bit is always 0. r/w 0 18 pracc processor access this bit is set to 1 by hardware when the processor accesses the probe?s reserved addr esses (0xff20- 0000 through 0xff2f-ffff). the probe?s software must set this bit to 0 to indicate the end of the access action. w0/r 0 19 prnw processor access read not write internal hardware sets this bit to 1 when the processor access action is a write action, it is set to 0 for a read action. r 0 20 perrst peripheral reset when this bit is set to 1 it will force a reset to all the peripherals of the processor (except for the ejtag interface and the debug support unit). r/w 0 21 run run when this bit is read as 1, the processor was in the run state (the pro- cessor clock was running) at the moment that the ejtag_control_register was captured. r 1 22 unused this bit is always 0. r 0 bit(s) mnemonic description r/w reset table 21.4 ejtag_control_register (part 2 of 3) ejtag (in-circuit emulator) interface jtag operation 79rc32334/332 user reference manual 21 - 16 june 4, 2002 notes figure 21.9 shows examples of the sync operation. figure 21.9 examples of the sync operation pc trace instruction (only if pc trace is supported) this jtag instruction is used to enable pc trac e mode. the real-time trace mode is set when the tap controller has reached the run-test/idle state. in this mode, the jtag_tdo/ejtag_tpc pin provides non- sequential program counter output at the ejtag_dclk speed. the ejtag_pcst[2:0] pins are used to show the type of instruction execution. a debug exception disables the pc trace mode. the instruction register will be set to bypass code (0x1f). 23 sync sync (only used when pctrace is supported) this bit will synchronize the end of the processor read access (instruc- tion fetch) with the setting of the pc trace mode. when this bit is set, the processor will be stalled for the last processor read access until the ejtag module has been placed into the pc trace mode (i.e. the pc trace instruction is in the instruction register and the tap controller is in the run-test/idle state). this bit can only be set at the end of a proces- sor read access, i.e. the pracc bit was 1 and is written with a 0 and prnw is 0. in all other cases, writing a 1 will be ignored. the bit is cleared by hardware when the pc trace mode is entered. the bit can also be cleared by writing a 0 to it: this will then also generate the acknowledge for the processor read. this bit is read-only 0 when pc trace is not supported (nopctrace = 1). w/r 0 25..24 pclen target pc output length set to 00 for rc32334. r 0 31..26 reserved reserved r 0 bit(s) mnemonic description r/w reset table 21.4 ejtag_control_register (part 3 of 3) pracc prnw sync trace mode debug mode tdi input tdo/tpc by processor; address latched processor fetches instruction prior to deret -5 bits sel ejtag_ctrl_reg -32 bits ejtag_ctrl_reg shift -5 bits sel ejtag_address_reg -32 bits ejtag_address_reg -5 bits sel ejtag_data_reg -32 bits ejtag_data_reg -5 bits sel ejtag_control_reg -32 bits ejtag_control_reg processor probe resets pracc processor executes instruction prior to deret processor fetches deret instruction processor executes deret processor probe shifts in pc trace instruction into tap ir processor is stalled debug exception tdi/dint* dint* input tdi input tdo output tpc output tdo output processor probe resets pracc and sets sync synchronisation of processor access and setting of trace mode jtag_tdi ejtag_dint_n jtag_tdo ejtag_tpc jtag_tdi jtag_tdo jtag_tdi jtag_tdo ejtag_dint_n ejtag_tpc synchronization of processor ac cess and setting of trace mode ejtag (in-circuit emulator) interface jtag operation 79rc32334/332 user reference manual 21 - 17 june 4, 2002 notes processor access the cpu can then execute code taken from the ejta g probe and it can access data (via load or store) which is located on the ejtag probe. this occurs in a serial way through the ejtag interface: the core can thus execute instructions e.g. debug monitor code, without occupying the user?s memory. accessing the ejtag probe?s memory can only be done when the processor accesses an ejtag address (which is in the range from 0xff20-0000 to 0xff2f-ffff), when the proben bit is set and when the processor is in debug mode (dm=1). when a debug exception is taken, while the proben bit is set, the processor will start fetching instruc- tions from address 0xff20-0200. instruction fetch/read from the ejtag probe 1. the internal hardware latches the requested address into the jtag_address_capture register (in case of the debug exception: 0xff20-0200). 2. the internal hardware sets the followi ng bits in the ejtag_control_register: pracc = 1 (selects processor access operation) prnw = 0 (selects processor read operation) dsz[1:0] = value depending on the transfer size 3. the ejtag probe selects the ejtag_control_regi ster, shifts out this control register?s data and tests the pracc status bit (processor access): when the pracc bit is found 1, it means that the requested address is available and can be shifted out. 4. the ejtag probe checks the prnw bit to determi ne the required access and shifts in a dmaacc = 0 bit into the ejtag_control_register. 5. the ejtag probe selects the ejtag_address_ register and shifts out the requested address. 6. the ejtag probe selects the ejtag_data_register and shifts in the instruction corresponding to this address. 7. the ejtag probe selects the ejtag_control_register and shifts a pracc = 0 bit into this register to indicate to the processor that the instruction is available. 8. the instruction becomes available in the instru ction register and the proc essor starts executing. 9. the processor increments the program counter and outputs an instruction read request for the next instruction. this will start the whole sequence again. using the same protocol, the processor can also execute a load instruction to access the ejtag probe?s memory. for this to happen, the processor must execute e.g. a lw, lb,... instruction with the target address in the appropriate range. almost the same protocol is used to execute a store instruction to the ejtag probe?s memory. the store address must be in the range: 0xff20-0000 to 0xff2f-ffff, the proben bit must be set, and the processor has to be in debug mode (dm=1). the sequence of actions is found below. processor write access 1. the internal hardware latches the requested addr ess into the jtag_address_capture register 2. the internal hardware latches the data to be written in to the jtag_data_capture register. 3. the internal hardware sets the followi ng bits in the ejtag_control_register: pracc = 1 (selects processor access operation) prnw = 1 (selects pr ocessor write operation) dsz[1:0] = value depending on the transfer size 4. the ejtag probe selects the ejtag_control_regi ster, shifts out this control register?s data and tests the pracc status bit (processor access): when the pracc bit is found 1, it means that the requested address is available and can be shifted out. 5. the ejtag probe checks the prnw bit to deter mine the required access and shifts in a dmaacc=0 bit into the ejtag_control_register. 6. the ejtag probe selects the ejtag_address_ register and shifts out the requested address. 7. the ejtag probe selects the ejtag_data_regi ster and shifts out the data to be written. 8. the ejtag probe selects the ejtag_control_register and shifts a pracc = 0 bit into this register to indicate to the processor that the write access is finished. 9. the ejtag probe writes the data to the requested address in its memory. 10. the processor detects that pracc bit = 0, wh ich means that it is ready to handle a new access. ejtag (in-circuit emulator) interface jtag operation 79rc32334/332 user reference manual 21 - 18 june 4, 2002 notes figure 21.10 depicts the processor and probe actions for the processor read and processor write access. . figure 21.10 ejta g processor access reset overview the processor core, processor peripherals, ejta g module and the dsu can be reset as follows (see also figure 21.11): the hard reset (general reset) si gnal resets the processor, the ejtag, the dsu and the peripher- als. the ejtag probe can soft reset the processo r core by setting the prrst bit in the ejtag_control_register. the ejtag probe can reset the peripherals on the processor by setting the perrst bit in the ejtag_control_register. the processor can reset both the ejtag module and the dsu by setting the jtagrst bit in the debug register. a system reset can be provided by the ejtag probe by activating the comb ination. of reset control bits: prrst and perrst. a full system reset through the ejtag is by the jtag reset pin to the master reset on the board. probe detects pracc=1 processor hardware: - address -->jtag_address_ capture_reg - data --> jtag_data_capture register - pracc=1, prnw=1, psz=xy pracc probe shifts out address probe shifts out data probe clears pracc bit probe writes data to its memory processor write access probe detects pracc=1 processor hardware: - address -->jtag_address_ capture_reg - pracc=1, prnw=0, psz=xy pracc probe shifts out address. probe reads instruction probe shifts in read instruction probe clears pracc bit processor executes instruction processor read access ejtag (in-circuit emulator) interface jtag operation 79rc32334/332 user reference manual 21 - 19 june 4, 2002 notes . figure 21.11 reset overview ejtag module clocking the bus clock may be used to clock a ll registers within the ejtag module which are not part of the tap- controller or the jtag registers (e.g. used for proces sor access or dma access). these latter registers are clocked by jtag_tck. instruction register the instruction register is a 5-bit field (such as ir4, ir3, ir2, ir1, ir0) that is used to decode 32 different possible instructions and allows instructions to be serially input to the device, when the tap controller is in the shift-ir state. instructions are decoded to perform the following tasks: to select test data registers that may operate wh ile the instruction is current. the other test data registers should not interfere with ch ip operation and selected data registers. to define the serial test data register path t hat is used to shift data between tdi and tdo during data register scanning. instructions are decoded as shown in table 21.5. brie f descriptions of each instruction are included in the table, but for a more complete description, refer to ieee standard test access port (ieee std. 1149.1- 1990). hex value instruction name/description function 0x00 extest extest is a mandatory instruction provided for external circuitry and board level interconnection check. select boundary scan register. 0x01 idcode selects the device identification register to read out manufac- ture?s identity, part number, and version number. select chip identification data register. 0x02 sample/preload sample instruction allows a snapshot of data flowing from the system pins to the on-chip logic, or vice versa. preload allows data values to be loaded onto the latched parallel outputs of the boundary-scan shift register, prior to selection of the other boundary-scan test instruction. select boundary scan register. table 21.5 instruction decoding (part 1 of 2) ejtag module dsu mips processor core or or hard reset hard reset jtagrst jtagrst or perrst hard reset prrst peripherals mips processor soft reset jtag reset (trst*) periph. reset mips processor rc32300 ejtag (in-circuit emulator) interface jtag operation 79rc32334/332 user reference manual 21 - 20 june 4, 2002 notes 0x03 impcode select implementation register. 0x04 intest tests the processor?s internal logic. test simulations are shifted in one at a time and applied to the on-chip system logic. the test results are captured into the boundary-scan register and exam- ined by subsequent shifting. jtag 0x05 hi-z places all of the device?s output pins into a high impedance state. an external ice can then drive all of the pins, and would not damage on-chip logic as well as the input pins. jtag 0x06 clamp allows the state of the signals driven from the ic pins to be deter- mined from the boundary-scan register, while the bypass register is selected as the serial path between tdi and tdo. jtag 0x07 bypass bypass mode 0x08 jtag_address_ir selects the jtag_address_register from external ice probe to load 32-bits of tdi data into the jtag_address_register. at the dr-update moment, the shifting stops and the 320bits of data are then loaded into the update register for the internal bus. select jtag_address register. 0x09 jtag_data_ir selects the jtag_data_register from external ice probe to load 32-bits of tdi data into the jtag_data_register. in addi- tion, data written to external ice probe are captured from the processor or any slave at data_capture register. data latched are at capture_dr stage are shifted out via tdo. select jtag_data register. 0x0a jtag_control_ir select the jtag_control_register from the external ice probe, to load 32-bits of tdi data into jtag_control_register bits or read the jtag_control_register bits. select jtag_control register 0x0b jtag_all_ir this register is the concatenation of the address_shift, data_shift and jtag_contrl_register. it can be used if switch- ing instructions in the instruction register cost too many tclk cycles. the first bit shifted out is bit 0 as shown in figure 21.12 select jtag_all register 0x10 pctrace decoded to switch from run-time mode to real-time mode. after executing this instruction, the pcst[2:0] pins, in conjunc- tion with tdo, provides a non-sequential program counter at the dclk speed. tdi/dint* is used in real-time mode to switch back to run-time mode by setting the jtagbrk bit. the instruc- tion register will be set to bypass code (0x1f). prior to execut- ing the pctrace instruction, the tap controller is placed into the run-test/idle state. pctrace instruction 0x1f bypass contains a single shift-register stage and is set to provide a mini- mum-length serial path between tdi and the tdo pins of the device, when no device test operations are required. any unused instruction is defaulted to the bypass instruction. bypass mode hex value instruction name/description function table 21.5 instruction decoding (part 2 of 2) ejtag (in-circuit emulator) interface extended instructions 79rc32334/332 user reference manual 21 - 21 june 4, 2002 notes note: as mentioned in the definition of the byp ass instruction, any unused instruction will default to the bypass instruction. figure 21.12 shift order sequence of the jtag_all_ir register the debug unit the debug unit section describes the debug unit implemented in the processor, and covers the extended instruction to mips isa instruction set as well as support functions and registers for real time debugging. note: the external instructions are slightly different from the original definition. similarly, the debug register is also different. extended instructions the following instructions are added to the standard mips isa instruction set to provide a software debug breakpoint exception and debug exception return. sdbbp (software debug breakpoint) format sdbbp code description this instruction raises a debug breakpoint exception, passing control to an exception handler. the code field can be used for passing information to the exception handler, but the only way to have the code field retrieved by the exception handler is to load the contents of the memory word containing this instruction, using the depc register. the sd bbp instruction is nop when it is used in debug mode (dm=?1?). the code field of the sdbbp is available for use as a software parameter only, and is retrieved by the debug exception handler only by loading the contents of the memory work contain- ing the instruction. the code field is not used in any way by the hardware. operation t: if not in debug mode pc ejtag (in-circuit emulator) interface extended cp0 registers (debug registers) 79rc32334/332 user reference manual 21 - 22 june 4, 2002 notes deret (debug exception return) extended cp0 registers (debug registers) the standard ejtag specification (version 1.5.3) def ines three registers to be added to the cp0 regis- ters to support debug exceptions: debug register debug exception pc debug exception save register the rc32334 only implements the debug register and t he debug exception pc register in the cp0. the debug exception save register is implemented as an on-chip register located at physical address 0xffff-e210. debug register debug register, cpo register 24 the debug register is used to control the debug e xception and provide status information about the cause of the debug exception. the read only status bits are automatically updated every time the debug exception is taken. description the opcode above was used by mips cpus following ejtag specification 1.3.1, and its use is dis- couraged because it may conflict with a future mips isa. format deret description this instruction executes a return from a debug exception. it has a branch delay slot, the same as the branch or jump instruction cycle, executing with a delay of one instruction cycle. the deret instruc- tion can not be used in the delay slot itself. the return address stored in the depc register is copied to the pc and processing returns to the original program. the debug mode bit (dm in debug [30]) and the brkst bit (ejtag_control_register[3]) are reset. note: if a mtc0 instruction was used to set the return address in the depc register, a minimum of two instructions must be executed before executing the deret. operation t: temp <- depc t+1: pc <- temp dm <- ?0? brkst <- ?0? exceptions coprocessor unusable exception 31 0 26 31 0 15 16 28 3 4 7 8 11 12 19 20 23 24 27 1110 0000 00 code 00 31 0 26 24 25 31 0 15 16 28 3 4 7 8 11 12 19 20 23 24 27 1111 0001 1 0100 00 0000 0000 0000 0000 0 ejtag (in-circuit emulator) interface extended cp0 registers (debug registers) 79rc32334/332 user reference manual 21 - 23 june 4, 2002 notes bit(s) mnemonic description r/w reset 0 unused this bit is always 0. r0 1dbp debug breakpoint exception status this bit is set to ?1? when a debug exception occurred due to execution of the sdbbp instruction. r0 2ddbl debug data address break load exception status this bit is set to ?1? when a data address break caused the debug excep- tion during execution of a load memory instruction. r0 3ddbs debug data address break store exception status this bit is set to ?1? when a data address break caused the debug excep- tion during execution of a store memory instruction. r0 4dib debug instruction address break exception status this bit is set to ?1? when an instruction address break caused the debug exception. r0 5dint debug processor bus br eak exception status this bit is set to ?1? when a processor bus break or a jtag break (from the ejtag probe) caused the debug exception. r0 6 dbes debug boot bit this bit is set to ?1? when debug boot is active during reset and forces the cpu to take the debug exception at the end of the reset sequence. it is cleared by software. w0/ r 0 7jtagrst jtag reset setting this bit to ?1? will reset both the ejtag module and the dsu. r/w 0 8 unused this bit is always 0. r0 9 reserved reserved r 0 10 bsf bus error exception flag this bit is set to ?1? when a bus error exception occurred during a load or store instruction while the debug exception handler was running (dm=?1?). the bus error exception will set this bit to ?1? regardless of writing a ?0?. it is cleared by writing a ?0? and writing ?1? is ignored. w0/r 0 11 tlf tlb exception flag this bit is set to ?1? when a tlb related exception occurs during the load or store instruction while the debug exception handler is running (dm=?1?). the tlb exception will set this bit to ?1?, and it is cleared by writing ?0?. writ- ing ?1? is ignored. w0/r 0 12 oes other exception status when this bit is set it indicates an exception other than reset, cache error, nmi or utlb miss/tlb refill was raised at the same time as a debug exception. in this case the status, cause, epc and badvaddr registers assume the usual status after occurrence of such an exception, but the address in the depc is not the ?other exception? vector address. in this case the proper exception handler address has to be placed in depc by the debug exception handler software, after which processing returns directly from the debug exception to the other exception handler. r0 13 trs tlb refill miss status this bit is the same as oes, but it is set when tlb refill occurs at the same time as a debug exception. depc must be set to tlb refill exception vec- tor, that is, 0xbfc0_0200 (bev=1) or 0x8000_0000 (bev=0), by debug exception handler software, after which processing returns directly from the debug exception to the tlb refill exception handler. for a description of the exception vector locations for the rc32334, refer to the exception vector loca tions section in chapter 6 (table 6.16) of this manual. r0 table 21.6 debug register (part 1 of 2) ejtag (in-circuit emulator) interface extended cp0 registers (debug registers) 79rc32334/332 user reference manual 21 - 24 june 4, 2002 notes debug exception program counter register (depc) for the rc32334, depc is cp0 register 23. . 14 nis non maskable interrupt status when this bit is set it indicates that a non-maskable interrupt has occurred at the same time as a debug exception. in this case the status, cause, epc and badvaddr registers assume the usual status after occurrence of a non-maskable interrupt, but the address in depc is not the non- maskable exception vector address (0xbfc0-0000). instead, 0xbfc0- 0000 has to be placed in depc by the debug exception handler software, after which processing returns directly from the debug exception to the non-maskable interrupt handler. r0 15 ces cache error status: this bit indicates that a debug exception and a cache error occurred at the same time. 0: no cache error. 1; cache error occurred at the same time with debug exception. r0 16 itrpt interrupt when cause.iv is set: this bit indicates that a debug exception and an interrupt with the cause.ivbit set occurred at the same time. 0: no interrupt with cause.iv bit set. 1; interrupt with cause.iv bit set. r0 17-29 reserved reserved r 0 30 dm debug mode status when this bit is set it indicates that a debug exception has been taken. it is cleared upon return from the debug exception (execution of deret). while this bit is set all interrupts (including nmi), tlb exception, bus error exception and debug exception are masked and the cache line locking function is disabled. a copy of the dm status is available in the brkst bit (ejtag_control_register[3]) and the ejtag_pcst[2:0] status lines (dbm code). r0 31 dbd debug branch delay this bit is set to ?1? when a debug exception occurs while an instruction in the branch delay slot is executing. the depc points to the branch or jump instruction preceding the instruction causing the debug exception. r0 bit(s) mnemonic description r/w reset 31:0 depc the depc register holds the address where processing resumes after the debug exception routine has finished. the address that has been loaded in the depc register is the virtual address of the instruction that caused the debug exception. if the instruction is in the branch delay slot, the virtual address of the immediately preceding branch or jump instruction is placed in this reg- ister. if the preceding instruction was a branch not taken, depc may be implemented point directly to the instruction in the delay slot. execution of the deret instruction causes a jump to the address in the depc. if the depc is both written from software (by mtc0) and by hardware (debug exception) then the depc is loaded by the value generated by the hardware. bit 0 of the depc indicates the mips16 mode, and is 1 when the inter- rupted instruction is a mips16 instruction. bit 0 always set to 0 for rc32334. r/w undefined table 21.7 debug exception program counter bit(s) mnemonic description r/w reset table 21.6 debug register (part 2 of 2) ejtag (in-circuit emulator) interface register map 79rc32334/332 user reference manual 21 - 25 june 4, 2002 notes debug exception save register (desave) in the rc32334, this register is external to t he core and implemented at physical address 0xffff-e210. register map the following registers are implemented in a deb ug support unit. these registers contain the data, address, control and status of the break channels, and are only accessible for read when the processor is executing in debug mode (dm=?1?) and for write when dm =1 and the memory protection bit is switched off (mp=?0?). when these conditions are not met, an atte mpt to access will cause an undefined result, e.g., invalid data may be read or a bus/address error ex ception may be raised. the dsu registers are non- cached memory locations, although they are in the kseg2 area. only word/double word accesses are allowed to these registers. the base address for all of these registers is: 0xff300000 and the actual address can be obtained by adding the offset value in table 21.9. debug control register the debug control register is located at address-offset 0x0000. bit(s) mnemonic description r/w reset 31:0 desave this register is used by the debug exception handler to save one of the gprs, that is then used to save the rest of the context to a pre- determined memory are, e.g. in the ejtag probe. this register allows the safe debugging of exception handlers and other types of code where the existence of a valid stack for context saving cannot be assumed. r/w undefined table 21.8 debug exception save register offset mnemonic description 0000 dcr debug control register 0004 ibs instruction address break status 0008 dbs data break status 000c pbs processor break status 0100 iba0 instruction address break 0 0104 ibc0 instruction address break control 0 0108 ibm0 instruction address break mask 0 0110 iba1 instruction address break 1 0114 ibc1 instruction break control 1 0118 ibm1 instruction address break mask 1 0200 dba0 data address break 0 0204 dbc0 data break control 0 0208 dbm0 data address break mask 0 0300 pba0 processor a ddress bus break 0 0304 pbd0 processor data bus break 0 0308 pbm0 processor data bus mask 0 030c pbc0 processor bus break control 0 and address mask table 21.9 32-bit register map (base address = 0xff30 0000) ejtag (in-circuit emulator) interface register map 79rc32334/332 user reference manual 21 - 26 june 4, 2002 notes bit(s) mnemonic description r/w reset 0 tm trace mode 0: this mode will output pc trace information at the jtag_tdo/ejtag_tpc pin in real-time. the serial address output may be incomplete. 1: this mode will output the complete pc address as trace information at the jtag_tdo/ejtag_tpc pin. the real-time behavior of the processor is not guaranteed. the rc32334 implements a single level deep buffer to store pc trace information. r/w 0 1 mrst* mask soft reset 0: soft reset to the core is masked during debug mode (dm=?1?) 1: no effect soft reset is always permitted during normal mode. this bit will not mask the processor reset bit prrst in ejtag_control_register[16]. r/w 1 2 mp memory protection 0: write to the dsu + ejtag reserved area (0xff20-0000 - 0xff3f-ffff) is possible in debug mode. 1: write to the dsu + ejtag reserved area (0xff20-0000 - 0xff3f-ffff) is protected in debug mode, except for the debug control register (dcr). when the processor is not in debug mode, accesses to this area are not allowed. r/w 1 3 mnmi mask non-maskable interrup t (in non debug mode) 0: mask the nmi signal to the core. 1: enable the nmi signal to the core. in debug mode all interrupt inputs to the core are masked r/w 1 4 mint mask interrupt (in non debug mode) 0: mask the interrupt inputs [int(5:0)] to the core 1: enable the interrupt inputs [int(5:0)] to the core in debug mode all interrupt inputs to the core are masked. r/w 1 5 unused w1/r 0 6 unused w0/r 0 7.28 reserved reserved r 0 29 enm endianess this bit indicates the default endianess. for some implementations it is a copy of the end bit in the core?s config register. 0: little endian 1: big endian r0 30 his halt status it indicates the sleeping state (power-down) when the debug excep- tion was taken. the precise definition of this power down mode is implementation specific. 0: processor was not in sleeping state 1: processor was in sleeping state when the rc32334 executes the wait instruction, this bit is set. r 0 31 unused r0 table 21.10 debug control register - dcr ejtag (in-circuit emulator) interface register map 79rc32334/332 user reference manual 21 - 27 june 4, 2002 notes instruction address match registers instruction address break status instruction address break n this register contains the upper 30/62 bits of t he instruction address break. table 21.12 shows the format of the instruction address break n register. this address is a virtual address. instruction address break mask n these registers specifies the mask value fo r the instruction address break register n (iba n ). each bit corresponds to a bit in the address register, and when: 0: address bit is not masked, address bit is compared. 1: address bit is masked, address bit is not compared. bit(s) mnemonic description r/w reset 0 bs0 break status 0 this bit, when set, indicates that an instruction address break or instruction address trigger has occurred. bs0 can be cleared by activating jtagrst, hard reset and also by writing a ?0? to it. r//w 0 14..1 bs[1] bs n break status [1] these bits are similar to the bs0 bit and are implemented accord- ing to the number of channels available. r//w 0 23..15 reserved reserved r 0 27..24 bcn break channel number : these bits indicate the total number of channels implemented for instruction address break. 0000: reserved 0001: channel 1 0002: channel 2 (implemented value) ... 1111: channel 15 r 0010 31..28 reserved reserved r 0 table 21.11 instruction address break status register - ibs bit(s) mnemonic description r/w reset 0- zero r0 1 1 reserved reserved r 0 31..2 iba n[ 31..2] instruction address break n r/w ? table 21.12 instruction address break register n - iban bit(s) mnemonic description r/w reset 0zero r0 1 1 reserved reserved r 0 31..2 ibm n [31..2] instruction address break mask n r/w ? table 21.13 instruction address break mask register n - ibmn ejtag (in-circuit emulator) interface register map 79rc32334/332 user reference manual 21 - 28 june 4, 2002 notes instruction address break control n this register selects the instruction address ma tch function to enable debug br eak or trace trigger. data address and data match registers data address break status this register provides the status of the possible 15 data breakpoints. bit(s) mnemonic description r/w reset 0 be break enable this bit enables the instruction address break function. 0: instruction address break function is disabled 1: instruction address break function is enabled if the instruction address break function is valid and the processor?s virtual instruction address and the address set by the iba n register (masked by ibm n ) match, a debug exception to the processor is generated. the bs n bit in the instruction address break status reg- ister is set and the dib bit in the debug register is set to identify the cause of the debug exception. when the instruction address break occurs, the debug exception happens just before the instruction is executed. if the debug excep- tion handler is already running (dm=?1?), then the debug exception will not be taken. r/w 0 1 reserved reserved r 0 2te trace trigger enable this bit enables the trace trigger function. 0: instruction address trace trigger function is disabled 1: instruction address trace trigger function is enabled. if the trace trigger function is valid and the processor?s virtual instruction address and the address set by the iba n register (masked by ibm n ) match, the trace trigger information tst(010) or tsq(001) is output to the ejtag_pcst[2:0] pins; also the bs0 bit in the instruction address break status register bit is set. when an address match occurs with both be=?1? and te=?1?, the instruction address break exception is taken after the trace trigger information is output to the ejtag_pcst[2:0] pins. r/w 0 31..3 reserved reserved r 0 table 21.14 instruction address break control n register - ibcn bit(s) mnemonic description r/w reset 0 bs0 break status 0 this bit, when set, indicates that a data address break or data address trigger has occurred. bs0 can be cleared by activating jtagrst, hard reset and also by writing a ?0? to it. r/w 0 14..1 bs[1] bs n break status [1] these bits are similar to the bs0 bit and are implemented accord- ing to the number of channels available. r/w 0 23..15 reserved reserved r 0 27..24 bcn break channel number these bits indicate the total number of channels implemented for data address break. 0000: reserved 0001: channel 1 (implemented value) ....... 1111: channel 15 r 0001 31..28 reserved reserved r 0 table 21.15 data address break status - dbs ejtag (in-circuit emulator) interface register map 79rc32334/332 user reference manual 21 - 29 june 4, 2002 notes data address break n this register contains the upper 30 bits of the data address break dba n . this address is a virtual address. processor bus match registers the processor bus match registers monitor the bus interface of the mips cpu and provide debug exception or trace trigger for a given physical addr ess and data. since the cpu bus is implementation specific, processor bus breaks may not work identically for different mips cpus. processor bus break status the following table shows the format of the processor bus break status register. processor address bus break n this register contains the bits of the physical processor address bus break. bit(s) mnemonic description r/w reset 0 w data break match on write 0: data address break disable for writes 1: data address break enabled for writes r0 1 r data break match on reads 0: data address break disable for reads 1: data address break enabled for reads r0 31..2 dba n [31..2] data address break n r/w ? table 21.16 data address break n register - dban bit(s) mnemonic description r/w reset 0 bs0 break status 0 this bit, when set, indicates that a processor bus break or proces- sor bus trigger has occurred. bs0 can be cleared by activating jtagrst, hard reset and also by writing a ?0? to it. r/w 0 14..1 bs[14..1] bs n break status [14..1] these bits are similar to the bs0 bit and are implemented accord- ing to the number of channels available. r/w 0 23..15 reserved reserved r 0 27..24 bcn processor bus break channel number these bits indicate the total number of channels implemented for processor bus break. 0000: reserved 0001: channel 1 (implemented value) ....... 1111: channel 15 r 0001 31..28 reserved reserved r 0 table 21.17 processor bus break status - pbs bit(s) mnemonic description r/w reset 0 reserved reserved r 0 1 1 reserved reserved r r/w 0 ? 31..2 pba n [31..2] processor address bus break n r/w ? table 21.18 processor address bus break register n - pban ejtag (in-circuit emulator) interface register map 79rc32334/332 user reference manual 21 - 30 june 4, 2002 notes processor data bus break n this register specifies the data val ue for the processor data bus match. processor data bus mask n this register specifies the mask value for the pr ocessor data bus break register. each bit corresponds to a bit in the data register: 0: data bit is not masked, data bit is compared 1: data bit is masked, data bit is not compared processor bus break control and address mask n this register selects the processor bus match function to enable debug break or trace trigger. it also includes control bits to enable comparison as well as mask bits to exclude address bits from comparison. bit(s) mnemonic description r/w reset 31..0 pbd n [31..0] processor data bus break n r/w ? table 21.19 processor data bus break n register - pbdn bit(s) mnemonic description r/w reset 31..0 pbm n [31..0] processor data bus mask n r/w ? table 21.20 processor data bus mask n register - pbmn bit(s) mnemonic description r/w reset 0be break enable this bit enables the processor bus break function. 0: processor bus break function is disabled 1: processor bus break function is enabled if the processor bus break function is valid and the processor?s physical address = pba n register (masked by lam) and the processor?s data bus = pbd n register (masked by pbm n ), then a debug exception to the pro- cessor is generated. the bs n bit in the processor bus break status regis- ter is set and the dint bit in the debug register is set to identify the cause of the debug exception. if the debug exception handler is already running (dm=?1?), then the debug exception will not be taken. r/w 0 1 reserved reserved r 0 2te trace trigger enable this bit enables the trace trigger function. 0: processor bus trace trigger function is disabled 1: processor bus trace trigger function is enabled. if the trace trigger function is valid and the processor?s physical address = pba n register (masked by lam) and the processor?s data bus = pbd n register (masked by pbm0), then the trace trigger information tst(010) or tsq(001) is output to the ejtag_pcst[2:0] pins; also the bs n bit in the pro- cessor bus break status register is set. when a processor bus match occurs with both be=?1? and te=?1?, the processor bus break exception is taken after the trace trigger information is output to the ejtag_pcst[2:0] pins. r/w 0 3 reserved reserved r 0 4 ifuc instruction fetch from un-cached area this bit enables the comparison on processor address and data bus for instruction fetches in the un-cached area. 0: processor address and data bus is not compared for instruction fetches in the un-cached area. 1: processor address and data bus is compared for instruction fetches in the un-cached area. when be=?1? and ifuc=?1? the debug break exception is taken on the same instruction. r/w 0 table 21.21 processor bus break control and address mask n - pbcn (part 1 of 2) ejtag (in-circuit emulator) interface register map 79rc32334/332 user reference manual 21 - 31 june 4, 2002 notes processor bus break function processor bus break becomes effective by setting pr ocessor bus control register bits. the debug unit will monitor the processor bus and, depending on the bit setting for instruction fetch from uncache area or data load/store in uncache or cache region (i .e., ifuc, dluc, dsux, pbco bits), address and data comparison is performed. pbao, pbdo, and pbm are holding the address, data, and mask value to be compared for debug interruption. processor bus trace trigger function by setting te=1 bit in the processor control register , the processor bus trace trigger becomes effective. the debug unit will monitor the processor bus and, depending on the bit setting for instruction fetch from uncache area or data load/store in uncache or cache region (i.e., ifuc, dluc, dsuc, pbco bits), address and data comparison is performed. when t he address set by pba0register and the data set by pbd0 register matches according to data mask value, trace information tst(010) or tsq(001) is output to pcst[2:0]. 5 dluc data load from un-cached area this bit enables the comparison on processor address and data bus for data loads in the un-cached area. 0: processor address and data is not compared for data load in the un-cached area. 1: processor address and data is compared for data load in the un-cached area. when be=?1? and dluc=?1? the debug break exception is taken after the next instruction. r/w 0 6 dsuc data store to un-cached area this bit enables the comparison on processor address and data bus for data store to the un-cached area. 0: processor address and data is not compared for storing data into the un-cached area. 1: processor address and data is compared for storing data into the un-cached area. when be=?1? and dsuc=?1? the debug break exception is taken after the next instruction. r/w 0 7 dsca data store to cached area this bit enables the comparison on processor address and data bus for data store to the cached area. 0: processor address and data is not compared for storing data to the cached area. 1: processor address and data is compared for storing data to the cached area. when be=?1? and dsca=?1? the break exception is taken after the next instruction. r/w 0 31..8 lam lower address mask these bits specify the mask value for the 24 bit lower bits of the proces- sor address bus break register (pba n [23..0]). each bit corresponds to the same bit in pba n . 0: address bit is not masked, address bit is compared. 1: address bit is masked, address bit is not compared. r/w 0x000 bit(s) mnemonic description r/w reset table 21.21 processor bus break control and address mask n - pbcn (part 2 of 2) ejtag (in-circuit emulator) interface debug exception 79rc32334/332 user reference manual 21 - 32 june 4, 2002 notes debug exception the debug exception has priority over all ex ceptions, except the reset exception. debug exception causes there are several causes of the debug exception: software debug breakpoint (sd bbp) instruction execution match on hardware dsu registers debug exception from the jtag port. this is ca used by the ejtag probe setting the jtagbrk bit in the ejtag_control_register. during debug mode no other debug exception can be taken. debug exception enabling/disabling the causes of the debug exception can be masked as follows: the software debug breakpoint (sdbbp) instru ction execution is masked in debug mode. the match on hardware dsu registers is enabled by setting the be bit in the corresponding control register. debug exceptions from the jtag port are only masked in debug mode. debug exception handling when the debug exception is raised, the pr ocessor jumps to the debug exception handler. if the proben bit in the ejtag_control_register[15] is set, the debug exception vector is located at address location: 0xff20-0200. (this is mapped in un-cacheable address space). if the proben bit in the ejtag_control_register [15] is cleared, the debug exception vector is located at address location: 0xbfc0-0480. (this is mapped in un-cacheable address space). only the contents of the debug register and t he depc will be affected by the debug exception. the debug mode bit (dm) in the debug register is set to ?1?. one (or more) of the following bits in the debug r egister are set to identify the cause of the debug exception: ? dss: after single step execution of an instructi on and the sst bit in the debug register is set. ? dbp: after execution of the sdbbp instruction. ? ddbl: data address match during a load memory instruction. ? ddbs: data address match during a store memory instruction. ? dib: instruction address match. ? dint: processor bus match or jtagbrk. ? dbd: set to ?1? when the exception was raised for an instruction in the branch delay slot. ? nis: set to ?1? if a non-maskable interrupt oc curred at the same time as the debug exception. ? ums: set to ?1? when the tlb exception occu rred at the same time as the debug exception. ? oes: set to ?1? if another exception (other than reset, tlb, nmi) was raised at the same time as the debug exception. exception priorities: dib have a higher priority than dbp, and jtagbrk has the lowest priority. in case of sdbbp caused exception: the depc register points to the sdbbp instruction, unless that instruction is in the branch delay slot, in which case the depc register points to the branch instruction and dbd bit is set to ?1?. in case the debug exception had other cause besides sddbp: the depc register points to the address of the in struction where the exception was raised (for sin- gle step exception, this is t he instruction to be executed). a single step exception is not raised for an instruction in the branch delay slot. when the deret instruction is executed, a single st ep exception is not raised for an instruction at the return destination. if the return destination is a branch instruction, a single step exception is not raised for that branch instruction or for the instruction in the branch delay slot. ejtag (in-circuit emulator) interface pc trace 79rc32334/332 user reference manual 21 - 33 june 4, 2002 notes exception handling when in debug mode (dm bit is set) in debug mode, the processor core can only take re set type exceptions, all other exceptions are not taken. all interrupts including nmi are masked. when the nmi interrupt occurred during debug mode it is stored internally and the nmi interrupt is ta ken after debug handler is finished (dm = ?0?). a load or store instruction which generated a tlb related exception during debug mode is not taken and is not executed. only the tlf bi t in debug register[11] will be set. when a load or store instruction causes a bus erro r exception when the processor is in debug mode, no exception is taken and the bsf bit in the debug r egister is set. the result of load/store operation is discarded. the debug mode has the same privileges as the kernel mode, i.e. access to all physical memory, the complete instruction set and all registers including gp r and coprocessor 0 instructions, regardless of the value of the kuc bit. servicing the debug exception when a debug exception occurs, the debug exception handler should save the context of the program that was executing. for that, it can use the desave register. after that, the service routine should deter- mine the nature of the exception from the debug regi ster bits and invoke the corresponding exception handler. the depc register holds the address to where pr ocessing resumes after the debug exception routine has finished. the address that has been loaded in the depc register is the virtual address of the instruction that caused the debug exception. if the instruction is in the branch delay slot, the virtual address of the immediately preceding branch or jump in struction is placed in this register and the dbd bit is set. execution of the deret instruction causes a jump to the address in the depc. in case of sdbbp caused exception: the unused bits of the sdbbp instruction (indicated as code) can be used for passing additional information to the except ion handler. in order to allow these bits to be viewed at, the user program should load the contents of the memory word containing this instruction, using the depc register. when the dbd bit in the debug register is set to ?1?, the sdbbp instruction is in the branch delay slot, therefore the value in the depc register should be added with 4. pc trace the basic idea of the instruction trace method is to output the virtual address of an instruction only when the program flow is changed by a jump instruction or ex ception. jump instructions can be divided into the following two groups: pc relative jump and direct jump : the target address of these instructions is fixed and identified by the source program. the target address is us ually specified by a ?l abel? in assembly language e.g. j label1 (jump to label1). indirect jump : the indirect jump instruction jumps to an address contained in a general register. this instruction is usually used for a subroutine ca ll or table jump. the target address is determined during program execution, e.g. jr r1 (jump to contents of register r1). note that the eret instruction is treated as an indirect jump too. a target address of a pc relative or direct jump instruction can be determined by the instruction itself. however, a target address of an indirect jump depends on the contents of a register when the instruction is executed. therefore the processor s hould output a target address of an indirect jump for real-time trace information. jump instructions are also classified into condi tional and unconditional jumps. the dynamic information whether the conditional branch is taken or not taken is necessary for instruction trace. ejtag (in-circuit emulator) interface instruction trace method 79rc32334/332 user reference manual 21 - 34 june 4, 2002 notes instruction trace method the ejtag module requires output pin(s) for the pc trace information. ejtag uses at least the data output jtag_tdo/ejtag_tpc for that. more pins can be dedicated for pc output if the extended ejtag inter- face is used (see pc status and ex ception vector encoding section). the other signals (ejtag_pcst) show the status of execution and also show when one of the break chan- nels (when programmed to output a trigger) has found a match. in the rc32334, the number of ejtag_tpc bits output is 30. to reduce the information at the ejtag_tpc pin(s), the processor only outputs a ta rget address of a direct jump, an indirect jump, a branch instruction and (part of) exception vector addresses. however, t here is the possibility that the target address output is not complete. the target address of an indirect jump may take 30 cycles to output the target address at the 1 bit jtag_tdo/ejtag_tpc pin. if the next indirect jump is exec uted in 30 cycles, then the first target address is not output completely. in pc trace mode, non-sequential program counter a ddress information (pc trace) is output at the ejtag_tpc pin(s), in conjunction with trace information at the ejtag_p cst pins. non-sequential pc trace is output when there is a change in the program flow, caused by: direct jump instructions (j and jal) where the target address is defined. indirect jump instructions (jr, jalr and eret) where the target address is contained in a register. branch instructions (beq, bne, blez, bgtz, bgez, bltz, bltzal, bczt, bczf, beql, bnel, blezl, bgtzl, bltzl, bgezll, bgezal, bltz all, bcztl and bczfl) where a branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset. interrupts and exceptions: an exception code is then output at the ejtag_tpc pin(s). pc status and exception vector encoding pc status encoding the pc trace status (ejtag_pcst) information is output at the same rate as the cpu pipeline clock. the pc status is only active in real-time mode. the ej tag_pcst encodes the status of the mips cpu execution as follows. jumps conditional unconditional pc relative instruction direct jump instruction taken / not taken - indirect jump instruction target address taken / not taken target address table 21.22 dynamic trace information pcst symbol function 1 1 1 stl pipeline stall. during this state there is no trace trigger output. 1 1 0 jmp execution of a taken jump instruction. this status indicates that the jump instruction is taken and also indicates the start of the target pc address output. in this case the target pc address of this jump will be output. 1 0 1 brt execution of a taken direct jump instruction or pc relative instruction. this status indicates the direct or pc relative jump is taken. in this case there is no pc trace output of this jump?s target address. 1 0 0 exp exception generated. this status indicates that an exception occurred, and an exception code is output at the ejtag_tpc pin(s). table 21.23 pc trace status information (part 1 of 2) ejtag (in-circuit emulator) interface pc status and exception vector encoding 79rc32334/332 user reference manual 21 - 35 june 4, 2002 notes status output on delay slots all jump and branch instructions have a delay slot. the instruction in the delay slot is normally executed prior to the jump/branch target instruction, however, so me instructions nullifies (kills) the delay slot instruc- tion rather than executing it. these instructions are: branch likely not taken instructions. the eret instruction. for the nullified delay slot instructions the stl (or ts t) code is output since the instruction is not part of the actual instruction flow; for executed delay sl ot instructions the seq (or tsq) code is output. for the jump/branch instruction itself jmp/brt is output when the jump/branch is taken, and seq (or tsq) is output for the branch when it is not taken. jm p is always output for the eret instruction. for a branch likely not taken instruction seq is output for the branch likely and stl is output for its nullified delay slot. note that the pc trace interpreting software may not be able to determine the exact target of a jump/ branch/eret instruction unless the sour ce is known; this is true even if a complete pc is output for the target. the reason for this, is that an instruction re sulting in a jmp code may or may not have an executed delay slot (only known if source is known), and thus it will either be t he first or the second significant code (code other than stl or tst) after the jmp which will represent the instruction at the target pc. the pc trace interpreting software will however in most case s be able resolve this uncertainty when the first jmp or brt is met in the program code at the target pc. exception vector encoding when an instruction receives an exceptional event, eit her due to an external source (e.g. interrupt) or as part of the execution flow (syscall, overflow etc. ), the exp code is output for that instruction instead of what would otherwise have been output. during an exception, when ejtag_pcst shows the exp c ode, the ejtag_tpc pins output a exception vector code, starting from the lsb of the code. instructi ons that generate a debug exception will not output the exp code nor the exception code at the ejtag_tpc pin(s). exception vector encoding for rc32334: table 21.24 shows the 4 bit exception code output at the ejtag_tpc pin(s) during the exp code at the ejtag_pcst pins. 0 1 1 seq execution of non jump instructions. this status information indicates that the processor has executed one instruction of sequential (in line) code. this status also indicates that the condi- tional jump is not taken. 0 1 0 tst trace trigger information is output when the pipeline is stalled. this condition shows that an address, data or processor bus trace trigger has occurred before the time that the pipeline is stalled. 0 0 1 tsq trace trigger output at execution time. this condition shows that an address, data or pro- cessor bus trace trigger has occurred during processor execution. 0 0 0 dbm debug mode. this condition is active when the debug mode is on (dm = ?1?). this code may also be output when trace in not on and the cpu is in normal mode. exception bev exl a[29] a[9] a[8] a[7] reset, softreset, nmi- - 1000 tlb refill 0 0 0000 table 21.24 exception and exception codes at ejtag_tpc (part 1 of 2) pcst symbol function table 21.23 pc trace status information (part 2 of 2) ejtag (in-circuit emulator) interface external interface definition 79rc32334/332 user reference manual 21 - 36 june 4, 2002 notes external interface definition ejtag the following signals are used during the pc trace mode (table 21.25 shows the complete list of ejtag interface signals). jtag_tdo/ejtag_tpc : during pc trace mode, the jtag_tdo/ej tag_tpc provides a non-sequential pc (ejtag_tpc) at the processor clock. ejtag_tpc is output simultaneously with the program counter trace status signals ejtag_pcst, starting with pc address 2 or 1. depending on the support of mips16 or not. ejtag_pcst[2:0]: pc status trace information, with the encoding described in table 21.23. ejtag_dclk: processor clock: this signal is used by the external ejtag probe to capture the ejtag_tpc and ejtag_pcst signals at the mips cpu clock rate. the ejtag_t pc and ejtag_pcst signals are output at the positive edge of ejtag_dclk. priority of target addr ess output (ejtag_tpc) the target address output at jtag_tdo/ejtag_tpc may change due to occurrence of an exception or of a next jump or branch instruction. there are prioriti es specified at which the ejtag_tpc output will change. the trace mode (tm) bit in the debug control register (dcr[0] ) determines if the current target pc output is stopped and the new target pc started instead, or t hat the current target pc is completely finished. real time ejtag_tpc output (tm=?0? in dcr[0]) during real-time ejtag_tpc output, the pc trace info rmation is output at the processor clock and the pc trace information is in sync. with the program exec ution. the target pc address output may be incomplete. the priorities for target pc output in this mode are: 1. if there is no ejtag_tpc being output, the target address of a taken jump will be output at jtag_tdo/ ejtag_tpc, also when it is a direct jump. the ejtag_pcst pins will show the jmp code (see figure 21.13). 2. if a new indirect jump is executed while the prev ious target pc is being output, the new indirect jump target pc will always start and the previous tar get pc output will be aborted (see figure 21.14). 3. if an exception occurs while the previous tar get pc is being output, an exception vector code is output and then the previous discontinued pc output is resumed (see figure 21.16). 4. if an exception occurs while a previous excepti on vector code is being output, the previous exception vector code output is aborted and the new e xception vector code output is started. 5. if a new direct jump or branch is executed while the previous target pc is being output, then this new direct jump or branch target pc will not be output. instead the ejtag_pcst code will indicate the brt code. the target pc for the direct jump or br anch is only output when t here is no pc trace output for another jump/branch going on (see figure 21.13) . if an exception vector code output is gong on but no jump/branch target pc is pending, then jmp is output for the direct jump and the target pc output for the direct jump starts once the exception vector code has been output. 6. if a jump occurs after exception, ejtag_tpc outputs exception code first and then the target address. cache error 0 - 0010 other 0 - 0011 interrupt (cause.iv=1)0 0 0101 tlb refill 1 0 1100 cache error 1 - 1110 interrupt (cause.iv=1)1 0 1001 other 1 - 1111 exception bev exl a[29] a[9] a[8] a[7] table 21.24 exception and exception codes at ejtag_tpc (part 2 of 2) ejtag (in-circuit emulator) interface examples of pc trace output 79rc32334/332 user reference manual 21 - 37 june 4, 2002 notes non-real time ejtag_tpc output (tm=?1? in dcr[0]) during non-real time trace mode the 30 bit target pc for indirect jumps and the 3 bit exception vector code is always output completely. in this mode, it is only guaranteed that all indirect jump target addresses and exception vector codes are fully output on ejtag_t pc, this is however enough information to completely reconstruct the program executi on flow. the rc32334 implements a single level deep buffer to store the pc trace address. the priorities for the pc trace output are: 1. if there is no ejtag_tpc being output, the target address of a taken jump will be output at jtag_tdo/ ejtag_tpc, also when it is a direct jump. the ejtag_pcst pins wi ll show the jmp code. 2. if an exception occurs while the target pc is being output, the exception ve ctor code is output first and then the previous discontinued pc output is resu med. the processor core is not stalled in this case. 3. if an exception occurs while a previous except ion vector code is being output, the pending exception vector code is output first and then the new excepti on vector code is output. the processor core is stalled in this case. 4. a. if an indirect jump instruction is executed whil e the previous target pc is being output, then the processor core is stalled until the prev ious target pc is completely output. b. if an indirect jump instruction is executed while t he previous target pc from a direct jump is being output, the rc32334 uses the 1 level deep buffer to store the pc trace address. 5. if a new direct jump or branch is executed while the previous target pc is being output, then this new direct jump or branch target pc will not be output. instead the ejtag_pcst code will indicate the brt code. the target pc for the direct jump or br anch is only output when t here is no pc trace output going on (see figure 21.13). 6. if a jump occurs after exception, ejtag_tpc outputs exception code first and then the target address. examples of pc trace output conditional pc relative jump instruction figure 21.13 indicates the executi on of conditional pc relative in structions. the beq and bne instruc- tions are conditional pc relative jumps. because the first jump instruction (beq) is taken and the ejtag_tpc output is not in use, the target pc of the beq starts to output and the ejtag_pcst status is the ?jmp?. the jump status corresponding to the second jump (bne) is t he ?seq? which indicates the jump is not taken. the third jump (bne) is taken, the ejtag_pcst lines show ?brt? but there is no ejtag_tpc output from its target address since it is a direct jump and the ejtag_tpc line is already outputting. figure 21.13 trace of conditional pc relative jump instruction indirect jump instruction the execution of an indirect instru ction is shown in figure 21.14. w hen the first indirect jump (jr1) instruction is executed, the processor outputs the ?jmp ? code at the ejtag_pcst pins and starts to output its target address from the lower bit at the ejtag_tpc pi n. the lower bit is a2. when the second indirect jump instruction (jr2) is executed, the processor stops outpu tting the target address of the first indirect jump and starts outputting the second target address. in this ca se, the target address of the first indirect jump is incomplete. instruction dclk pcst[2:0] tpc stl seq seq jmp seq seq seq seq seq brt seq seq seq seq a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 sub add beq (t) nop add bne (nt) nop add bne (t) nop add branch is taken (jmp). tpc is output branch is not taken (seq) branch is taken (brt). no tpc is output, since it is a direct jump add - ejtag_dclk ejtag_pcst [2:0] ejtag_tpc ejtag (in-circuit emulator) interface examples of pc trace output 79rc32334/332 user reference manual 21 - 38 june 4, 2002 notes figure 21.14 trace of indirect jump instruction pc trace of an exception followed by a jump indirect instruction in figure 21.15, the break instruction is executed and causes an exception. this is indicated by the ?exp? code at ejtag_pcst and the ejtag_tpc starts out putting the 3-bit exception code ?001? starting with the lsb. the taken jr2 instruction causes the jmp code at ejtag_pcst and the outputting of its target address at ejtag_tpc. figure 21.15 trace of an exception followed by a jump indirect instruction pc trace of an indirect instruction followed by an exception in figure 21.16, the indirect jump jr1 starts t he ejtag_tpc output, but the target address output is stopped to allow exception code bits of the exception to be output. after this the target address output is continued again. figure 21.16 trace of indirect jump instruction followed by an exception instruction dclk pcst[2:0] tpc stl seq seq jmp seq seq seq seq seq jmp seq seq seq seq a2 a3 a4 a5 a6 a7 a2 a3 a4 a5 a6 sub add jr1 (t) nop add bne (nt) nop add jr2 (t) nop add branch is taken (jmp). tpc is output branch is not taken (seq) branch is taken (jmp). new tpc is output, since it is an indirect jump. jr1 tpc output aborted add - ejtag_dclk ejtag_pcst [2:0] ejtag_tpc instruction dclk pcst[2:0] tpc stl seq seq stlexpstlstl seq seq jmp seq seq seq seq a2 a3 a4 a5 a6 sub add break (t) - - nop add jr2 (t) nop add branch is taken (jmp). tpc is output. add - - e0 e1 e2 exception code 001 is output at tpc. output of 3 bit code starts with lsb ejtag_dclk ejtag_pcst [2:0] ejtag_tpc instruction dclk pcst[2:0] tpc stl seq seq jmp seq seq exp stl stl seq seq seq seq seq a2 a3 a4 e0 a5 a6 a7 a8 a9 add add jr1 (t) nop andi - - mult add branch is taken (jmp). tpc is output - - add sll e1 e2 exception code is output at tpc. output of 3 bit code starts with lsb branch target address is continued ejtag_dclk ejtag_pcst [2:0] ejtag_tpc ejtag (in-circuit emulator) interface examples of trace trigger output 79rc32334/332 user reference manual 21 - 39 june 4, 2002 notes examples of trace trigger output trace trigger information is output at the ejtag_pcst pins when an instruction address, data or processor bus trigger occurred. in general trace triggers should be indicated on the in struction which caused the trigger. however, since trigger indications can only be indica ted in the pc trace output on seq or stl codes (by replacing these codes with tsq or tst) the trace trigger indication cannot be exactl y defined. if jmp, brt or exp needs to be output, a simultaneous trigger indication must be output on another code and thus the ejtag probe cannot accurately determine the inst ruction that generated the trigger. instruction address trace trigger figure 21.17 shows the occurrence of the trace trigger tsq code at the ejtag_pcst pins for the instruc- tion address that matches the required conditions. figure 21.17 instruction address trace trigger trace trigger and general exception at the same time in figure 21.18, both the trace trigger and an except ion occur at the same moment, then the ejtag_pcst pins show the tst code, followed by the exp code. the 3 bit exception code is output at ejtag_tpc. figure 21.18 trace trigger and general exception at the same time jump indirect causes trace trigger in figure 21.19 the jump indirect (jr2) is the instruct ion that generates the trace trigger. this indicated by the tsq code at the ejtag_pcst pins. instruction dclk pcst[2:0] tpc stl seq seq seq seq tsq seq seq seq jmp seq seq seq seq a2 a3 a4 a5 a6 sub add nop add jr2 (t) nop add branch is taken (jmp). tpc is output. add - add sub add bne (nt) instruction which generates trace trigger. tsq is output in the w stage ejtag_dclk ejtag_pcst [2:0] ejtag_tpc instruction dclk pcst[2:0] tpc stl seq seq tst exp stl stl seq seq jmp seq seq seq seq sub add break (t) - - nop add nop add instruction which generates trace trigger and also exception add - - jr2 (t) e0 a2 a3 a4 e1 e2 a5 a6 ejtag_dclk ejtag_pcst [2:0] ejtag_tpc ejtag (in-circuit emulator) interface switching from real-time trace to debug 79rc32334/332 user reference manual 21 - 40 june 4, 2002 notes figure 21.19 jump indirect causes trace trigger instruction after jump indirect causes trace trigger in figure 21.20 the trace trigger is caused by the instruction following the jr2. the resulting trace trigger output information however is the same. the ejtag probe can not accurately determine the instruc- tion that generated the trigger. figure 21.20 instruction after jump indirect causes trace trigger switching from real-time trace to debug real-time trace mode to debug mode (no ejtag_tpc output) in figure 21.21, the debug exception occurs in the instru ction following the nop instruction. in this case there is no target pc output going on. the debug mode is entered directly after the debug exception. when the instruction causing the debug exception is also set up for generating trace trigger, then the tst code is output at ejtag_pcst just before debug mode is entered. figure 21.21 real-time trace mode to debug mode (no tpc output) instruction dclk pcst[2:0] tpc stl seq seq seq seq tsq seq seq seq jmp tsq seq seq seq a2 a3 a4 a5 a6 sub add nop add jr2 (t) nop add instruction which generates trace trigger add - add sub add bne (nt) trace trigger code tsq is output one clock after jmp ejtag_dclk ejtag_pcst [2:0] ejtag_tpc instruction dclk pcst[2:0] tpc stl seq seq stlexpstlstl seq seq jmp tsq seq seq seq sub add break (t) - - nop add nop add add - - jr2 (t) e0 a2 a3 a4 e1 e2 a5 a6 instruction which generates trace trigger ejtag_dclk ejtag_pcst [2:0] ejtag_tpc seq rf if alu mem wb if rf alu mem wb nop instruction instruction causing debug exception debug exception handler if rf alu mem wb stl dbm (000) dclk pcst[2:0] tdo/tpc tdi/dint dm dint tdi tdo tpc debug exception ejtag_dclk ejtag_pcst [2:0] jtag_tdo/ jtag_tdi/ ejtag_tpc ejtag_dint_n ejtag (in-circuit emulator) interface pin out of the standard ejtag 79rc32334/332 user reference manual 21 - 41 june 4, 2002 notes real-time trace mode to debug mode in figure 21.22, the target pc is being output (e.g. due to execution of an indirect jr instruction) when a debug exception occurs. in this case the debug mode is entered after the trace output is finished. during this time the stl code is output at ejtag_pcst; t he debug mode entry is indicated by the dbm code. in debug mode, the jtag_tdo/ejtag_tpc pin function changes from ejtag_tpc to jtag_tdo; jtag_tdi/ejtag_dint_n pin function changes from ejtag_dint_n to jtag_tdi. figure 21.22 real time trace mode to debug mode (debug exce ption in branch delay slot) pin out of the standard ejtag figure 21.23 represents the timing diagr am for the ejtag interface signals. the standard ejtag connector (without pc trace signal s) is a 12-pin connector. for standard ejtag, a 24-pin connector has been chosen, providing 12 signal pins and 12 ground pins. this guarantees elimina- tion of noise problems by incorpor ating signal-ground type arrangement. figure 21.23 timing diagram of the ejtag interface signals jmp rf if alu mem wb if rf alu mem wb jr instruction nop (delay slot) debug exception handler if stall seq dbm (000) dclk pcst[2:0] tdo/tpc tdi/dint dm dint tdi tdo tpc debug exception stl a2 a3 a4 a5 a31 stall stl stl ejtag_dclk ejtag_pcst [2:0] jtag_tdo/ jtag_tdi/ ejtag_tpc ejtag_dint_n jtag_tdi/ejtag_dint_n ejtag_tms jtag_tdo/ejtag_tpc, ejtag_tpc[8:2] jtag_tdo jtag_tdo ejtag_tpc ejtag_pcst[2:0] jtag_trst_n jtag_tck ejtag_dclk ejtag_pcst t3 t14 t14 t1 t2 t15 t15 t9 t10 t5 t6 t4 t8 t7 t13 t12 t11 ejtag_tpc,ejtag_pcst[2:0] capture notes to diagram: t1 = t tcklow t2 = t tckhigh t3 = t tck t4 = t tdodo t5 = t tdis t6 = t tdih t7 = t pcstdo t8 = t tpcdo t9 = t dckhigh t10 = t dcklow t11 = t dck t12 = t trstdo t13 = t trstr t14 = t tck rise, ttck fall t15 = t dck rise, t dck fall ejtag (in-circuit emulator) interface ejtag application information 79rc32334/332 user reference manual 21 - 42 june 4, 2002 notes table 21.25 shows the pin numbering for the standar d ejtag (ejt) connector. all the even numbered pins are connected to ground. the last columns show the target signal direction and the recommended termination at the target. target te rmination resistors may be internally in the chip or externally on the board. ejtag application information using jtag boundary scan and ejtag figure 21.24 gives an application diagram of a target board showing how the processor?s ejtag signals are connected to the target connector and to the other (boundary scan) ic?s on the board. figure 21.24 application diagram of target board and ejtag connection pin signal target i/o termination 1 1. the value of the series resistor may depend on the actual pcb layout situation. 1 ejtag_trst_n (optional) input 10 k ? pull-down resistor 3 jtag_tdi, ejtag_dint_n input 10 k ? pull-up resistor 5 jtag_tdo/ejtag_tpc output 33 ? series resistor 7 jtag_tms input 10 k ? pull-up resistor 9 jtag_tck input 10 k ? pull-up resistor 2 2. jtag_tck pull-up resistor is not required according to the jtag (ieee1149) standard. it is indicated here to prevent a floating cmos input when the ejtag connector is unconnected. 11 system reset input 10 k ? pull-up resistor 13 ejtag_pcst[0] output 33 ? series resistor 15 ejtag_pcst[1] output 33 ? series resistor 17 ejtag_pcst[2] output 33 ? series resistor 19 ejtag_dclk output 33 ? series resistor 21 ejtag_debugboot input 10 k ? pull-down resistor 23 vio input must be connected to the vcc i/o supply of the device. table 21.25 pin numbering of th e jtag and ejtag target connector jtag_tdo jtag_tms jtag_tck jtag_trst_n jtag_tdo ejtag_tpc jtag_trst_n jtag_tms jtag_tck jtag_tdi jtag testable ic jtag testable ic ejtag debugging jtag boundary scan test jtag_trst_n jtag_tdo jtag_tms sys reset jtag_tck gnd gnd gnd gnd gnd gnd 12 jtag_pcst[0] jtag_pcst[1] jtag_pcst[2] ejtag_dclk gnd gnd gnd gnd jtag_tdi/dint ejtag_pcst[0] ejtag_pcst[1] ejtag_pcst[2] ejtag_dclk 4x 33 ohm jtag_tdi ejtag_dint_n vdd cpu_coldreset_n 5x 10 k (may be on-chip) rc32300 cpu standard ejtag connector (male header pins 2 x 12 pins pitch 1.27 x 1.27 mm) x1 vdd **) **) probe?s rst* to be ?or-ed? with board/mips system reset target board jtag_tdi / ejtag_dint_n jtag_tdo / ejtag_tpc jtag_trst_n ejtag_tms ejtag_tck jtag_tdo ejtag_debug boot gnd vio gnd jtag_tdo jtag_tdi jtag_trst_n jtag_tms jtag_tck gnd ejtag (in-circuit emulator) interface ejtag application information 79rc32334/332 user reference manual 21 - 43 june 4, 2002 notes jumper block x1 on the target board provides the connection of the processor?s jtag_tdo/ejtag_tpc signal to the ejtag connector (during ejtag debugging) or to the other boundary scan testable ic?s on the board (during boundary scan test). this separates t he (high speed) ejtag_tpc information from the other ic?s during ejtag emulation/debugging; after emulat ion/debugging is finished, the jumpers can be set such that the processor is part of the boundary scan test chain: jtag_tdo/ejtag_tpc outputs its serial data to the next following jtag_tdi input and the jtag_tdo of the last ic in the chain gets connected to the ejtag connector. a jtag/boundary scan tester can then be hooked to this connector (pins 1-10 is sufficient in this case). since the ejtag trace pins (ejtag_tpc, ejtag_pcst[2 :0], ejtag_dclk) contain high speed data, the user shall take special care in the pcb layout of thes e signals. the ejtag connector has to be placed close to the ejtag pins of the processor chip; the pc trac e pcb tracks between connector and chip shall be short and preferably be of equal length. the ejtag probe shall have a female connector that is plugged into this target connector. the ejtag probe connector pcb may also contain a (fast) buffer fo r the high-speed trace signals; this external buffer shall be capable of driving the (short ) flat cable to the ejtag probe box. hot plug-in of the ejtag probe to target system in order to allow hot plug (connection while power on) the jtag_trst, jtag_tdi / ejtag_dint, jtag_tms and jtag_tck should be tri-state in the ejtag probe when t he connection is made to target. in this way, the connection will not reset the target board by acciden t, and the input signals to the target could then be driven high to the right level when the vdd is known. ejtag (in-circuit emulator) interface ejtag application information 79rc32334/332 user reference manual 21 - 44 june 4, 2002 notes notes 79rc32334/332 user reference manual a - 1 june 4, 2002 appendix a rc32300 cpu core enhancements to mips ii isa introduction the rc32300 execution unit implements the enhanced mi ps-ii isa. a superset of mips ii, these archi- tectural enhancements include the addition of a mips-iv prefetch operation that in corporates various hint subfields, conditional move instructions that are mips- iv compatible, additional integer multiply unit instruc- tions, and two new instructions designed to enhance t he performance levels of certain dsp algorithms. these features combine to make the cpu well suit ed to applications that require high bandwidth, rapid computation, and/or dsp capability. a discussion of each new integer unit feature implemented in the rc32334 follows. general instruction set information can be found in the idt mips microprocessor family software developer?s guide . prefetch (pref) in general, pref is an advisory in struction that may change the performance of the program but will not cause addressing related exceptions. if the pref inst ruction raises an exception condition, the exception condition is ignored. if an addressing-related exception condition is raised and ignored, no data will be prefetched. in such a case, if no data is prefetched, some action that is not architecturally-visible?such as writeback of a dirty cache line or invalidate a cache line (in the ca se of ?ignorehit? hint)?might take place. pref will not generate a memory operation for a location with an uncached memory access type. as noted in figure a.1, the hint field supplies information about the way the data is expected to be used. for data movement, the mips iv pref instruction is implemented with multiple hints. figure a.1 format of prefetch instruction format: pref hint, offset(base) description: to form an effective byte address, pref adds the 16-bit signed offset to the content of gpr base. it advises that data at the effective addr ess may be used in the near future. the hint field supplies information about the way the data is expected to be used. the format of the prefetch instruction is shown in figure a.1. figure a.2 provides a diagram of the prefetch operation flow. 31 26 25 21 20 16 15 0 pref 110011 base hint 16 5 5 6 offset prefetch (pref) 79rc32334/332 user reference manual a - 2 june 4, 2002 notes figure a.2 flowchart for prefetch operation the defined hint values and prefetch actions are listed in table a.1. value hint field name and definition prefetch action 0load informs the cpu to process the pref as if the cause were a cache miss on a load instruction. as such, the tlb coherency algorithm rules that apply to a load cache miss are applied. for example, if the tlb and chip were to support multi-processing, the resulting read could be marked as ?coherent? or not, depending upon the translation. data is expected to be loaded (not modified). fetch data as if for a load. 1store informs the cpu to process the pref as if the cause were a cache miss on a load instruction. as such, the rules with respect to coherency, write allocation, etc. may be applied to the resulting bus transaction. data is expected to be stored or modified. fetch data as if for a store. 31 ignore hit (kernel mode only) causes the pref to perform a cache refill, even if the target address currently hits in the cache. the mips-iv isa allows pref to revert to a nop operation under exceptional conditions, etc., since the program will be semantically cor- rect, although lower performance, if the cache miss processing occurs later. however, the ?ignore hit? option carries an implicit invalidation of the current cache line. as such, even if the pref/ignore-hit generates an exception, the cache line invalidate occurs when the pref is encountered so that the pro- gram does run correctly later (that is, old cache contents are not used). invalidate the cache line and bring in the new data from memory regardless of the state of the valid bit. table a.1 value of hint field for the prefetch instruction begin operation prefetch ignore hit set? cache hit? exception? complete prefetch cache hit? is modified? invalidate cache line write back modified cache line yes yes no no yes yes no terminate prefetch no no yes elimination of 64-bit instructions 79rc32334/332 user reference manual a - 3 june 4, 2002 notes operation: exception: reserved instruction, if ?ignore hit? is used in user mode. elimination of 64-bit instructions when an instruction requests 64-bit data operations, t he rc32334 signals a trap. this includes both the mips-iii 64-bit instructions and the mips-ii 64-bit coprocessor operations . the trap signal occurs in both user and kernel modes. conditional move operations in addition to the prefetch instruction, the rc32300 core implements the conditional move instructions found in the mips-iv architecture. move conditional on not zero format : movn rd, rs, rt description : if the value in rt is not equal to zero, then the content of rs is placed into rd. operation: exception: reserved instruction. move conditional on zero format: movz rd, rs, rt description: if the value in rt is equal to zero, then the content of rs is placed into rd. operation: exception: reserved instruction. instructions for dsp support the rc32300 cpu core adds new instructions to the mips ii isa, intended to enhance the performance of certain types of dsp algorithms. all of these extensions are supported in the enhanced mips-ii isa. specifically, enhancements in the multiplier have been added to allow fast fused multiply-adds and multiply-subtracts. in addition, rc32300 cpu core adds the three operand multiply operations originally found in the 1st rc4650 and adds instructions to he lp normalize values (count-leading-1?s or 0?s). vaddr <-- gpr[base] + sign_extend(offset) (paddr, uncache) <-- address translation(vaddr, data, load) prefetch(uncache, paddr, vaddr, data, hint) t: if gpr[rt] 0 then gpr[rd] <-- gpr[rs] t: if gpr[rt] = 0 then gpr[rd] <-- gpr[rs] 31 26 25 21 20 16 15 6 5 0 special 000000 rs rt 0 00000 movn 001011 6 5 5 6 55 rd 10 11 31 26 25 21 20 16 15 6 5 0 special 000000 rs rt 0 00000 movz 001010 6 5 5 6 55 rd 10 11 instructions for dsp support 79rc32334/332 user reference manual a - 4 june 4, 2002 notes multiply add format: mad rs, rt description: the content of general registers rs and rt are multiplied? treating both operands as 32-bit two?s complement values?and the result is added to hi/lo. overflow excepti ons do not occur under any circumstances. once the operation is complete, the low-order word of the double result is loaded in lo, and the high- order word of the double result is loaded in hi. operation: exception: none multiply add unsigned format: madu rs, rt description: the content of general registers rs and rt are multiplied, treating both operands as 32-bit unsigned values, and the result is added to hi/lo. no overflow exception occur under any circumstances. when the operation completes, the low-order word of the double result is loaded in lo, and the high- order word of the double result is loaded in hi. the inst ruction is not interlocked so any attempt to read hi/ lo before the operation completes returns undefined value. operation: exception: none multiply subtract format: msub rs, rt t: temp <-- (hi || lo) + gpr[rs] * gpr[rt] lo <-- temp 31..0 hi <-- temp 63..32 t: temp <-- (hi || lo) + (0||gpr[rs]) * (0||gpr[rt]) lo <-- temp 31..0 hi <-- temp 63..32 31 26 25 21 20 16 15 65 0 special2 011100 rs rt 0 00000 mad 000000 6 5 5 5 6 10 11 5 0 00000 rt 31 26 25 21 20 16 15 6 5 0 special2 011100 rs rt 0 00000 madu 000001 6 5 5 6 5 5 11 10 0 00000 31 26 25 21 20 16 15 6 5 0 special2 011100 rs rt 0 00000 msub 000100 6 5 5 5 6 10 11 5 0 00000 instructions for dsp support 79rc32334/332 user reference manual a - 5 june 4, 2002 notes description : the content of general registers rs and rt are multiplied, treating both operands as 32-bit two?s complement values, and the result is subtract ed from hi/lo. no overflow exception occur under any circumstances. when the operation is complete, the low-order word of the double result is loaded in lo, and the high- order word of the double result is loaded into hi. the in struction is not interlocked so any attempt to read hi/ lo before the operation completes returns undefined value. operation: exception: none multiply subtract unsigned format: msubu rs, rt description: the content of general registers rs and rt are multiplied, treating both operand as 32-bit unsigned values, and the result is subtracted from hi/l o. no overflow exception occur under any circum- stances. when the operation completes, the low-order word of the double result is loaded in lo, and the high- order word of the double result is loaded in hi. the inst ruction is not interlocked so any attempt to read hi/ lo before the operation completes returns undefined value. operation: exception: none count leading zeros format: clz rs, rt description: the content of general register rs is scanned from the most significant bit to the least significant bit, and the number of leading zeros is wri tten into general register rt. if no bits were set in general register rs, i.e. rs=0, the content of general register rt is 32. operation: exception: none t: temp <-- (hi || lo) - gpr[rs] * gpr[rt] lo <-- temp 31..0 hi <-- temp 63..32 t: temp <-- (hi || lo) - (0||gpr[rs]) * (0||gpr[rt]) lo <-- temp 31..0 hi <-- temp 63..32 t: rt <-- leading_zeros(rs) 31 26 25 21 20 16 15 6 5 0 special2 011100 rs rt 0 00000 msubu 000101 6 5 5 6 5 5 11 10 0 00000 31 26 25 21 20 16 15 6 50 special2 011100 rs rt 0 0000000000 clz 100000 6 10 5 5 6 instructions for dsp support 79rc32334/332 user reference manual a - 6 june 4, 2002 notes count leading ones format: clo rs, rt description: the content of general register rs is scanned fr om most significant bit to least significant bit, the number of leading ones is written into general r egister rt. if no bits were cleared in general register rs, i.e. rs=0xffffffff, the content of general register rt is 32. operation: exception: none t: rt <-- leading_ones(rs) 31 26 25 21 20 16 15 6 5 0 special2 011100 rs rt 0 0000000000 clo 100001 6 10 5 5 6 notes 79rc32334/332 user reference manual b - 1 june 4, 2002 appendix b opcode map special addi cop0 * special2 ** * beql bnel blezl bgtzl lb sb cache * * ll ** * sc ** * *** * * * * * tge tgeu tlt tltu teq tne 2..0 sll jr mfhi mult add slt sdbbp **** *** * **** ** * special function 0 1 2 3 4 5 6 7 31..29 0 1 2 3 4 5 6 5..3 0 1 2 3 4 5 6 7 7 28..26 opcode 0 1 2 3 4 5 6 7 syscall break sh swl sw swr lwc1 lwc2 pref swc1 swc2 * lh lwl lw lbu lhu lwr srl sra sllv srlv srav jalr mthi mflo mtlo multu div divu addu sub subu and or xor nor sltu cop1 cop2 * addiu slti sltiu andi ori xori lui regimm j jal beq bne blez bgtz * * 2 mul 3 * * * * * movz movn sync * ** * 5 67 2..0 1 special function2 5..3 4 0 0 1 2 3 4 5 6 7 mad madu * * * * ** * clz * clo * * * * * * * * * ** * * * * ** * * * * * * * ** * * * ** * * * * * * * * * * * msub msubu * * ** * 79rc32334/332 user reference manual b - 2 june 4, 2002 notes 2..0 0 1234567 0 1 2 3 tlbwi tlbr tlbwr tlbp f 4 5 6 7 eret ? ?????? ?????? ?????? ?????? wait ????? dret ?????? ?????? cp0 function copz rt mf dmf cf mt dmt ct copz rs bc ?? 01 3 4 56 7 2 co 23..21 25,24 0 1 2 3 5..3 regimm rt 20..19 18..16 12 34 5 6 7 0 0 1 2 3 bltz bgez bltzl bgezl ** ** tgei tgeiu tlti tltiu teqi tnei * * bltzal bgezal bltzall bgezall * * ** * ** * * * * * bcf 18..16 0 1 2 3 4 5 6 7 20..19 0 1 2 3 bcfl ? ? ? bct bctl ? ? ? ? ? notes 79rc32334/332 user reference manual c - 1 june 4, 2002 appendix c the timing of cache operations introduction cache holds a copy of recently read or written to me mory data so that it can be quickly returned to the cpu. to double the effective cache-memory bandwidth, idt cpus implement separate on-chip instruction (i-cache) and data (d-cache) caches. within the rc32334, both an i-cache and d-cache access can occur simultaneously; cache accesses take one processor clock to complete. information specific to the rc32334?s cache organiza tion and operation is provided in chapter 7 of this manual. caveats about cache operations ? all cycle counts are in processor cycles. ? all cache operations have a lower priority than cache misses, write backs and external requests. if the write back buffer contains unwritten data when a cache op is executed, the write back buffer will be retired before the cache op is started. if an instruction cache miss occurs at the same time a cache op is executed, the instruction cache miss will be handled first. cache operations are mutually excl usive with respect to data cache misses. before beginning any cache operation, external requests will be completed first. ? for all data cache ops the cache op state machine waits for the store buffer and response buffer to empty before beginning the cache op. this can add 3 cycl es to any data cache op if there is data in the response buffer or store buffer. the response buf fer contains data from the last data cache miss that has not yet been written to the data cache. t he store buffer contains delayed store data waiting to be written to the data cache. ? cache ops of the form xxxx_writ eback_xxxx may perform a write back which will fill the write back buffer. write backs can affect subsequent cache ops, si nce they will stall until the write back buffer is written back to memory. cache ops which fill t he write back buffer are noted as (writeback) in the following tables. ? all cycle counts are best case assuming no in terference from the me chanisms described above. cache operations tables table c.1 and table c.2 show data cache and instru ction cache operation?s information. a detailed explanation of the fill_i equation follows table c.2. name operation number of cycles index_writeback_invalidate_d examine the cache state and w bit of the pri- mary data cache block at the index specified by the virtual address. if the state is not invalid and the w bit is set, then write back the block to memory. the address to write is taken from the primary cache tag. set cache state of primary cache block to invalid. 10 cycles, if the cache line is clean. 12 cycles, if the cache line is dirty (writeback). index_load_tag_d read the tag for the cache block at the specified index and place it into the taglo cpo register, ignoring parity errors. also load the data parity bits into the ecc register. 7 cycles. table c.1 primary data cache operations (part 1 of 2) cache operations tables 79rc32334/332 user reference manual c - 2 june 4, 2002 notes index_store_tag_d write the tag for the cache block at the specified index from the taglo and taghi cpo registers 8 cycles. create_dirty_exclusive_d this operation is used to avoid loading data needlessly from memory when writing new con- tents into an entire cache block. if the cache block does not contain the specified address, and the block is dirty, write it back to the mem- ory. in all cases, set the cache block tag to the specified physical address and set the cache state to dirty exclusive. 10 cycles, for a cache hit. 13 cycles, for a cache miss if the cache line is clean. 15 cycles, for a cache miss if the cache line is dirty (writeback). hit_invalidate_d if the cache block contains the specified address, mark the cache block invalid. 7 cycles, for a cache miss. 9 cycles, for a cache hit. hit_writeback_invalidate_d if the cache block contains the specified address, write back the data if it is dirty and mark the cache block invalid. 7 cycles, for a cache miss. 12 cycles, for a cache hit if the cache line is clean. 14 cycles, for a cache hit if the cache line is dirty (writeback). hit_writeback_d if the cache block contains the specified address, and the w bit is set, write back the data to memory and clear the w bit. 7 cycles, for a cache miss. 10 cycles, for a cache hit if the cache line is clean. 14 cycles, for a cache hit if the cache line is dirty (writeback). name operation number of cycles index_invalidate_i set the cache state of the cache block to invalid. index_invalidate_i writes the physical address of the cache operation into the tag when it clears the valid bit, which is different from the rc4000 family. 7 cycles. index_load_tag_i read the tag for the cache block at the speci- fied index and place it into the taglo cpo reg- ister, ignoring parity errors. also load the data parity bits into the ecc register. 7 cycles. index_store_tag_i write the tag for the cache block at the specified index from the taglo and taghi cpo registers. 8 cycles. hit_invalidate_i if the cache block contains the specified address, mark the cache block invalid. 7 cycles for a cache miss. 9 cycles for a cache hit. fill_i fill the primary instruction cache block from memory. if the ce bit of the status register is set, the contents of the ecc register are used instead of the computed parity bits for an addressed doubleword, when written to the instruction cache. cycle number must be calculated based on the system response to a memory access, because fill_i causes an instruction cache refill from memory. the number of processor cycles for a fill_i cache op is calculated as follows: number_of_cycles_for_a_fill_i_cacheop = 10 + {0 - (sysdiv - 1)} + (2 x sysdiv) + (ml x sysdiv) + (d x sysdiv) hit_writeback_i if the cache block contains the specified address, write back the data unconditionally. 7 cycles, for a cache miss. 20 cycles, for a cache hit (writeback). table c.2 primary instruction cache operations name operation number of cycles table c.1 primary data cache operations (part 2 of 2) fill_i equation definitions 79rc32334/332 user reference manual c - 3 june 4, 2002 notes fill_i equation definitions the following definitions apply to t he fill_i equation listed in table c.2: sysdiv: number of processor cycles per system cycle: range is between 2 and 8. ml: number of system cycles of memory latency, defined as the number of cycles the internal ip bus is driven by the external agent bef ore the first word of data appears. d: number of system cycles required to return the bl ock of data, defined as the number of cycles begin- ning when the first word of data appears on the internal ip bus and ending when the last word of data appears on the internal ip bus, inclusive. fill_i equation definitions 79rc32334/332 user reference manual c - 4 june 4, 2002 notes notes 79rc32334/332 user reference manual d - 1 june 4, 2002 appendix d rc32334/rc32332 standby mode operation introduction the standby mode operation is a means of reducing the internal core?s power consumption when the cpu is in a ?standby? state. in this sect ion, the standby mode operation is explained. power management the rc32334/rc32332 offers a number of features rele vant to low-power systems, including low-power design, active power management, and a power-down operating mode. power reduction modes the riscore 32300 core is a static design, and products based on this core, such as the rc32334/ rc32332, offer various power reduction modes. in additi on, the riscore 32300 supports a ?wait? instruc- tion that is designed to signal the chip?s other res ources that execution and clocking should be halted. the ?wait? instruction (illustrated and defined below) is used to halt the internal pipeline thus dramati- cally reducing the power consumption of the cpu. format: wait description: used to halt the internal pipeline and r educe the power consumption of the cpu. operation: exceptions: coprocessor unusable exception. entering standby mode to enter standby mode, first execute the wait instru ction. when the wait instruction finishes the w pipe-stage, if the internal ip bus is currently idle, t he internal clocks will shut down, thus freezing the pipe- line. the pll, internal timer, some of the input pin clocks (cpu_int_n[5:4,2:0 ], cpu_nmi_n, cpu_coldreset_n, internal cpu_int_n[3]) will continue to run. in t he rc32334/rc32332, the system controller peripherals will continue to run. however, no dma operations c an occur while the cpu core is in standby mode. if the conditions are not correct when the wait in struction finishes the w pipe-stage (such as the internal ip bus is not idle), the wait is treated as a nop. once the cpu is in standby mode, any interrupt? including the internally generated timer interrupt or th e internal cpu_int_n[3]?will cause the cpu to exit standby mode. figure d.1 illustrates t he flow of the standby mode operation. 0 6 6 5 31 25 24 26 cop0 6 0 wait 19 1 co 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 t: if ad bus is idle then stoppipeline endif entering standby mode 79rc32334/332 user reference manual d - 2 june 4, 2002 notes figure d.1 flowchart for standby mode operation when ?wait? instructions finish the w-stage, the r3600 core will check for bus activity. ?wait? instruction is treated as a ?nop? instruction once in standby mode , the pclock will shutdown, freezing remain active: pll internal timer int(5:0)* nmi* reset* coldreset* if bus activity detected the pipeline; however, these signals and internal blocks will if int(5:0)*, nmi*, reset*, or an internal timer interrupt signal occurs, rc32334/rc32332 will exit standby mode. ad int(5:0)* nmi* reset* coldreset* if bus activity not detected ale ack* rd* wr* cip* after exiting standby mode , rc32334 does not sample any control/ ad bus signals on the first risi ng edge. also, bus activity and other internal processes will resume by using the latched information that existed before entering standby mode. note: during standby mode, all control signals for the cpu must be deasserted or put into the appropriate state, and all input signals, except int(5:0)*, nmi*,reset*, and coldreset* must remain unchanged. if a c hange occurs, the signal will be unaffected. notes 79rc32334/332 user reference manual e - 1 june 4, 2002 appendix e coprocessor 0 hazards introduction this appendix identifies the rc32300 cpu core specific coprocessor 0 hazards. certain instruction combinations are not permitted because the results are unpredictable when combined with events such as pipeline delays, cache misses, interrupts and exceptions. most hazards result from instructions modifyi ng and reading state in different pipeline stages. such hazards are defined between pairs of in structions, not on any single instru ction. other hazards are associ- ated with the restartability of instructions in the presence of exceptions. refer to the idt mips microprocessor family software developer?s guide for information about mips isa hazards. list of hazards rc32334/rc32332 cp0 hazards are as follows: ? a mtc0 followed by a mfc0 is undefined. a one instruction delay between mtc0 and mfc0 is needed for proper operation. this rule applies when the destinat ion of the first instruction is the same as the source of the second instruction. see example #1 below. ? when dwatch is enabled, the two instructions i mmediately following may not be checked for a match with the watch value. ? when iwatch is enabled, the five instructions that follow may not be checked for a match with the i match value. ? when bit 23 of the status register is changed, refills to set a may not be disabled until five instruc- tions later. ? when bit 24 of the status register is changed, refill s to set a may not be disabled until three instruc- tions later. ? cannot clear um, erl, and exl simultaneously. mu st clear um first, then erl and exl can be cleared simultaneously. ? a minimum of two nop instructions should be inserted between the eret instruction and the mtc0 instruction to ensure the exl and erl bi ts are changed correctly. see example #2 below. example #1: this instruction sequence will lead to an undefined result: mtc0 r1, c0_sr mfc0 k0, c0_sr this instruction sequence will lead to the intended result: mtc0 r1, c0_sr mfc0 k0, c0_epc example #2: mtc0 co_status, r5 nop nop eret introduction 79rc32334/332 user reference manual e - 2 june 4, 2002 notes notes 79rc32334/332 user reference manual f - 1 june 4, 2002 appendix f integer multiply scheduling introduction integer multiply performance is substantially enhanced in the rc32334. the rc32300 cpu core adds a mad instruction (multiply-accumulate, with hi and lo as the accumulator). multiply performance is 2 cycles repeat, 3 cycles of latency for 16-bit operands (-2 16 to 2 16 -1). the mad (multiply/add), madu (multiply/add unsigned) msub (multiply/subtract) and msubu (multiply/subtract unsigned) are defined as follows, where hi and lo act as a 64-bit accumulator. these instructions do not trap on addition overflow. after executing this instruction, the hi and lo registers are undefined. for 16-bit operands, the latency of mul is 3 cycles, with a repeat rate of 2 cycles. the mul instruction will also unconditionally slip or stall for all but 2 cycles of its latency. the performance of integer multiply and divide is summarized in table f.1. in addition, the rc32300 cpu core implements anot her new multiply opcode that allows the multiply result to be returned directly to the primary register file: mad rs, rt temp (hi|| lo) + rs * rt hi temp 63 . . 32 lo temp 31 . . 0 madu rs, rt temp (hi|| lo) 31. .0 ) + (0|| rs) * (0|| rt) hi temp 63 . . 32 lo temp 31 . . 0 msub rs, rt temp (hi || lo) - rs * rt hi temp 63 . . 32 lo temp 31 . . 0 msubu rs, rt temp (hi || lo) - (0|| rs) * (0|| rt) hi temp 63 . . 32 lo temp 31 . . 0 mul rd, rs, rt temp rs 31 . . . 0 * rt 31 . . 0 rd temp 31. . . 0 hi undefined lo undefined introduction 79rc32334/332 user reference manual f - 2 june 4, 2002 notes table f.1 integer multiply and divide performance as a special case, a mad or madu that is foll owed by a mul instruction has one additional cycle of repeat above the value specified in the table. in the rc4700, the mflo and mfhi instructions do not make their results available immediately. if the rc4700 instruction references the mflo/mfhi destination, then a 1-cycle slip will occur; however, on the rc32300 cpu core, the result is avail able immediately and there is no slip. opcodes condition latency repeat stall mult, mad -2 15 rt 2 15 -1 3 2 0 mult, mad rt < -2 15 or rt > 2 15 -1 4 3 0 multu, madu 0 rt 2 16 -1 3 2 0 multu, madu rt > 2 16 -1 4 3 0 mul -2 15 rt 2 15 -1 3 2 1 rt < -2 15 or rt > 2 15 -1 4 3 2 div, divu any 36 36 0 notes 79rc32334/332 user reference manual g - 1 june 4, 2002 appendix g rc32332 differences introduction generally, the information contained in this manual applies equally to both the rc32334 and the rc32332. differences between the two devices are noted in this appendix and in occasional notes and footnotes throughout the manual. the rc32332 is based on the same die as the rc32334, except that the rc32332 is housed in a 208 quad flat pack (qfp) package instead of the 256 ball grid array package used by the rc32334. the qfp package option enables idt to provide the solution at a lower cost point than the rc32334, but the reduced number of package connections means that certain features originally included in the rc32334 are reduced or removed from the rc32332. differences in features table g.1 lists the differences in features between the rc32332 and rc32334. memory controller the rc32332 maps out fewer memory address li nes?mem_addr[22:2] instead of mem_addr[25:2]. therefore, with the rc32332, the maximum external memory size that can be supported for each individual chip select is 8mb. pci controller on-chip arbiter the on-chip bus arbiter in the rc32332 supports two external bus masters: pci_req_n[0] and pci_req_n[2]. references in this manual to pci_req_n[1] do not apply to the rc32332. pci controller device id on the rc32332, it is recommended that the pci devi ce id be written as 0205h, either through the configuration register interface, or, if in the pci boot mode, through the pci boot eeprom. using the recommended value will distinguish the controller from the rc32334. the default for the rc32332 is 204h, the same value as for the rc32334. for more details, see ?device id register? on page 12-26. rc32332 rc32334 sdram bus interface 66 mhz 75 mhz memory address lines 23, 8mb maximum per cs 26, 64mb maximum per cs pci maximum frequency 50 mhz 66 mhz on-chip pci arbiter 2 slot 3 slot dma controller flow control for channel 0 flow control for channel 1 and 0 pio controller 8 pio signals 16 pio signals timer controller ? 1 external tc_n/gate_n signal cpu interrupts 2 external 4 external number of uart channels 12 uart controller ? modem control signals for channel 0 packaging 208 qfp 256 plastic bga table g.1 feature set comparison between rc32332 and rc32334 differences in features 79rc32334/332 user reference manual g - 2 june 4, 2002 notes dma controller flow control on the rc32332, there is one flow control si gnal, dma_ready_n[0] for dma channel 0. on the rc32334, there are two flow control signals, dma_ready_n[ 1:0] for dma channels 1 & 0. for more details, see chapter 13. pio controller signals the following 8 pio signals are not available on the rc32332: uart_rts_n[0], uart_cts_n[0], uart_dsr_n[0], uart_dtr_n[0], uart_rx[1], uart_tx[1], timer_tc_n[0], and dma_ready_n[1]. for more details, see chapter 15. the following two tables summarize the diff erences between pio pin names in the rc32334 and rc32332. register bit main function alternate function rc32334 alternate function rc32332 31-12 reserved reserved reserved 11 spi_mosi pio[10] pio[6] 10 spi_sck pio[9] pio[5] 9 spi_ss_n pio[8] pio[4] 8 spi_miso pio[7] pio[3] 7 uart_rx[0] pio[6] pio[2] 6 uart_tx[0] pio[5] pio[1] 5 uart_rx[1] pio[4] reserved 4 uart_tx[1] pio[3] reserved 3 timer_tc_n[0] pio[2] reserved 2 reserved reserved reserved 1 dma_ready_n[0] pio[1] pio[0] 0 dma_ready_n[1] pio[0] reserved table g.2 pio [data/direction/func tion select] register 0 comparison register bit main function alternate function rc32334 alternate function rc32332 31-5 reserved re served reserved 4 uart_cts_n[0] pio[15] reserved 3 uart_dsr_n[0] pio[14] reserved 2 uart_dtr_n[0] pio[13] reserved 1 uart_rts_n[0] pio[12] reserved 0 pci_eeprom_cs pio[11] pio[7] table g.3 pio [data/direction/func tion select] register 1 comparison differences in features 79rc32334/332 user reference manual g - 3 june 4, 2002 notes timer controller signal on the rc32332, the timer overflow/gate signal, time r_tc_n[0] is not present. for more details, see chapter 16. interrupt lines the rc32332 maps out one less interrupt line to t he external pads. the rc32332 has two external interrupt lines available (cpu_int_n[1:0]) in addition to t he nmi line. all references in this manual to the addi- tional interrupt lines in the rc32334 (cpu_int_n[ 5:4], cpu_int_n[2]) do not apply to the rc32332. uart interface the rc32332 has only one serial port (uart0). all feat ures in this user manual referencing uart1 should be ignored if the designer is planning to use the rc32332. additionally, for uart0, all of the modem signals that were bonded out to the external pads in the rc32334?request to send (rts), clear to send (cts), data terminal ready (dtr), and data set ready (dsr)?are not accessible on the rc32332 pins. therefore, the programming of thes e bits in the modem control regist ers does not perform any usable func- tion in the rc32332. internal bus interface sysid register the value for the rc32332 that is programmed in bits 19:8 is 004h. for more details, refer to ?sysid register? on page 8-14. jtag device_id register the value for the rc32332 that is programmed in the pa rt number field, bits 27:12, is 001ah. for more details, see section deviceid in chapter 20. jtag boundary scan cells the rc32332 has 303 boundary scan cells as descr ibed in its bsdl file. the rc32334 has 330 boundary scan cells, as descr ibed in its bsdl file. electrical / pinout see the rc32332 data sheet for information on the ac, dc, and thermal characteristics, and device pinout. pin description table 79rc32334/332 user reference manual g - 4 june 4, 2002 pin description table the following table lists the pins provided on the rc32332. note that those pin names followed by ?_n? are active-low signals. all external pull-ups and pull-downs require 10 k ? resistor. name type reset state status drive strength capability description local system interface mem_data[31:0] i/o z high local system data bus primary data bus for memory. i/o and sdram. mem_addr[22:2] i/o [25:10] z [9:2] l [22:16] low [15:2] high memory address bus these signals provide the memory or dram address, during a memory or dram bus transaction. during each word data, the address increments either in linear or sub-block ordering, depending on the transac- tion type. the table below indicates how the memory write enable signals are used to address discrete memory port width types. mem_addr[22] alternate function: reset_boot_mode[1]. mem_addr[21] alternate function: reset_boot_mode[0]. mem_addr[20] alternate function: reset_pci_host_mode. mem_addr[19] alternate function: modebit [9]. mem_addr[18] alternate function: modebit [8]. mem_addr[17] alternate function: modebit [7]. mem_addr[15] alternate function: sdram_addr[15]. mem_addr[14] alternate function: sdram_addr[14]. mem_addr[13] alternate function: sdram_addr[13]. mem_addr[11] alternate function: sdram_addr[11]. mem_addr[10] alternate function: sdram_addr[10]. mem_addr[9] alternate function: sdram_addr[9]. mem_addr[8] alternate function: sdram_addr[8]. mem_addr[7] alternate function: sdram_addr[7]. mem_addr[6] alternate function: sdram_addr[6]. mem_addr[5] alternate function: sdram_addr[5]. mem_addr[4] alternate function: sdram_addr[4]. mem_addr[3] alternate function: sdram_addr[3]. mem_addr[2] alternate function: sdram_addr[2] mem_cs_n[5:0] output h low memory chip select negated recommend external pull-up. signals that a memory bank is actively selected. mem_oe_n output h high memory output enable negated recommend external pull-up. signals that a memory bank can output its data lines onto the cpu_ad bus. mem_we_n[3:0] output h high memory write enable negated bus signals which bytes are to be written during a memory transaction. bits act as byte enable and mem_addr[1:0] signals for 8-bit or 16-bit wide addressing. mem_wait_n input ? memory wait negated requires external pull-up. sram/ioi/iom modes: allows external wait-states to be injected during the last cycle before data is sam- pled. dpm (dual-port) mode: allows dual-port busy signal to restart memory transaction. alternate function: sdram_wait_n. table 21.26 pin description for rc32332 (part 1 of 6) port width pin signals mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] dma (32-bit) mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] 32-bit mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] 16-bit byte high write e nable mem_addr[1] not used (driven low) byte low write enable 8-bit not used (driven high) mem_addr[1] mem_addr[0] byte write enable pin description table 79rc32334/332 user reference manual g - 5 june 4, 2002 mem_245_oe_n output h low memory fct245 output enable negated controls output enable to optional fct245 transceiver bank by asserting during both reads and writes to a memory or i/o bank. mem_245_dt_r_n output z high memory fct245 direction xmit/rcv negated recommend external pull-up. alternate function: cpu_dt_r_n. see cpu core specific signals below. output_clk output cpu-mas terclk high output clock optional clock output. pci interface pci_ad[31:0] i/o z pci pci multiplexed address/data bus address driven by bus master during initial frame_n assertion, and then the data is driven by the bus master during writes; or the data is driven by the bus slave during reads. pci_cbe_n[3:0] i/o z pci pci multiplexed command/byte enable bus command (not negated) bus driven by the bus master during the initial frame_n assertion. byte enable negated bus driven by the bus master during the data phase(s). pci_par i/o z pci pci parity even parity of the pci_ad[31:0] bus. driven by bus master during address and write data phases. driven by the bus slave during the read data phase. pci_frame_n i/o z pci pci frame negated driven by the bus master. assertion indicates the beginning of a bus transaction. de-assertion indicates the last datum. pci_trdy_n i/o z pci pci target ready negated driven by the bus slave to indicate the current datum can complete. pci_irdy_n i/o z pci pci initiator ready negated driven by the bus master to indicate that the current datum can complete. pci_stop_n i/o z pci pci stop negated driven by the bus slave to terminate the current bus transaction. pci_idsel_n input ? pci initialization device select uses pci_req_n[2] pin. see the pci subsection. pci_perr_n i/o z pci pci parity error negated driven by the receiving bus agent 2 clocks after the data is received, if a parity error occurs. pci_serr_n i/o open- collector zpci system error external pull-up resistor is required. driven by any agent to indicate an address parity error, data parity during a special cycle command, or any other system error. pci_clk input ? pci clock clock for pci bus transactions. uses the rising edge for all timing references. pci_rst_n input l ? pci reset negated host mode: resets all pci related logic. satellite mode: with boot from pci mode: resets all pci related logic and also warm resets the 32332. pci_devsel_n i/o z pci pci device select negated driven by the target to indicate that the target has decoded the present address as a target address. pci_req_n[2] input z ? pci bus request #2 negated requires external pull-up. host mode: pci_req_n[2] is an input indicating a request from an external device. satellite mode: used as pci_idsel pin which selects this device during a configuration read or write. alternate function: pci_idsel (satellite). pci_req_n[0] i/o z high pci bus request #0 negated requires external pull-up for burst mode. host mode: pci_req_n[0] is an input indicating a request from an external device. satellite mode: pci_req_n[0] is an output indicating a request from this device. name type reset state status drive strength capability description table 21.26 pin description for rc32332 (part 2 of 6) pin description table 79rc32334/332 user reference manual g - 6 june 4, 2002 pci_gnt_n[2] output z 1 high pci bus grant #2 negated recommend external pull-up. host mode: pci_gnt_n[2] is an output indicating a grant to an external device. satellite mode: pci_gnt_n[2] is used as the pci_inta_n output pin. external pull-up is required. alternate function: pci_inta_n (satellite). pci_gnt_n[1] i/o x for 1 pci clock then h 2 high pci bus grant #1 negated recommend external pull-up. host mode: not used. satellite mode: used as pci_eprom_cs output pin for serial chip select for loading pci configuration reg- isters in the rc32332 reset initialization vector pci boot mode. defaults to the output direction at reset time. 1st alternate function: pci_eeprom_cs (satellite). 2nd alternate function: pio[7]. pci_gnt_n[0] i/o z high pci bus grant #0 negated host mode: pci_gnt_n[0] is an output indicating a grant to an external device. recommend external pull- up. satellite mode: pci_gnt_n[0] is an input indicating a grant to this device. requires external pull-up. pci_inta_n output open- collector zpci pci interrupt #a negated uses pci_gnt_n[2]. see the pci subsection. pci_lock_n input ? pci lock negated driven by the bus master to indicate that an exclusive operation is occurring. 1 z in host mode; l in satellite non-boot mode; z in satellite boot mode. 2 h in host mode; l in satellite non-boot mode; l in satellite boot mode. sdram control interface sdram_addr_12 output l high sdram address bit 12 and precharge all sdram mode: provides sdram address bit 12 (10 on the sdram chip) during row address and ?pre- charge all? signal during refresh, read and write command. sdram_ras_n output h high sdram ras negated sdram mode: provides sdram ras control signal to all sdram banks. sdram_cas_n output h high sdram cas negated sdram mode: provides sdram cas control signal to all sdram banks. sdram_we_n output h high sdram we negated sdram mode: provides sdram we control signal to all sdram banks. sdram_cke output h high sdram clock enable sdram mode: provides clock enable to all sdram banks. sdram_cs_n[3:0] output h high sdram chip select negated bus recommend external pull-up. sdram mode: provides chip select to each sdram bank. sodimm mode: provides upper select byte enables [7:4]. sdram_s_n[1:0] output h high sdram sodimm select negated bus sdram mode: not used. sdram sodimm mode: upper and lower chip selects. sdram_bemask_n [3:0] output h high sdram byte enable mask negated bus (dqm) sdram mode: provides byte enables for each byte lane of all dram banks. sodimm mode: provides lower select byte enables [3:0]. sdram_245_oe_n output h low sdram fct245 output enable negated recommend external pull-up. sdram mode: controls output enable to optional fct245 transceiver bank by asserting during both reads and writes to any dram bank. sdram_245_dt_r_n output z high sdram fct245 direction transmit/receive recommend external pull-up. uses cpu_dt_r_n. see cpu core specific signals below. name type reset state status drive strength capability description table 21.26 pin description for rc32332 (part 3 of 6) pin description table 79rc32334/332 user reference manual g - 7 june 4, 2002 on-chip peripherals dma_ready_n[0] i/o z low dma ready negated bus requires external pull-up. ready mode: input pin for general purpose dma channel 0 that can initiate the next datum in the current dma descriptor frame. done mode: input pin for general purpose dma channel 0 that can terminate the current dma descriptor frame. dma_ready_n[0] 1st alternate function pio[0]; 2nd alternate function: dma_done_n[0]. pio[7:0] i/o see related pins low programmable input/output general purpose pins that can each can be configur ed as a general purpose input or general purpose out- put. these pins are multiplexed with other pin functions: pci_gnt_n[1], spi_mosi, spi_miso, spi_sck, spi_ss_n, uart_rx[0], uart_tx[0], dma_ready_n[0]. note that pci_gnt_n[1], spi_mosi, spi_sck, and spi_ss_n default to outputs at reset time. the others default to inputs. uart_rx[0] i/o z low uart receive data bus uart mode: uart channel receives data. uart_rx[0] alternate function: pio[2]. uart_tx[0] i/o z low uart transmit data uart mode: uart channel send data. note that this pin defaults to an input at reset time and must be programmed via the pio interface before being used as a uart output. uart_tx[0] alternate function: pio[1]. spi_mosi i/o l low spi data output serial mode: output pin from rc32332 as an input to a serial chip for the serial data input stream. in pci satellite mode, acts as an output pin from rc32332 that connects as an input to a serial chip for the serial data input stream for loading pci configuration registers in the rc32332 reset initialization vector pci boot mode. defaults to the output direction at reset time. 1st alternate function: pio[6]. 2nd alternate function: pci_eeprom_mdo. spi_miso i/o z low spi data input serial mode: input pin to rc32332 from the output of a serial chip for the serial data output stream. in pci satellite mode, acts as an input pin from rc32332 that connects as an output to a serial chip for the serial data output stream for loading pci configuration registers in the rc32332 reset initialization vector pci boot mode. 1st alternate function: pio[3]. 2nd alternate function: pci_eeprom_mdi. spi_sck i/o l low spi clock serial mode: output pin for serial clock. in pci satellite mode, acts as an output pin for serial clock for loading pci configuration registers in the rc323332 reset initialization vector pci boot mode. defaults to the output direction at reset time. 1st alternate function: pio[5]. 2nd alternate function: pci_eeprom_sk. spi_ss_n i/o h low spi chip select output pin selecting the serial protocol device as opposed to the pci satellite mode eeprom device. alternate function: pio[4]. defaults to the output direction at reset time. cpu core specific signals cpu_nmi_n input ? cpu non-maskable interrupt requires external pull-up. this interrupt input is active low to the cpu. cpu_masterclk input ? cpu master system clock provides the basic system clock. cpu_int_n[1:0] input ? cpu interrupt requires external pull-up. these interrupt inputs are active low to the cpu. name type reset state status drive strength capability description table 21.26 pin description for rc32332 (part 4 of 6) pin description table 79rc32334/332 user reference manual g - 8 june 4, 2002 cpu_coldreset_n input l ? cpu cold reset this active-low signal is asserted to the rc32332 after v cc becomes valid on the initial power-up. the reset initialization vectors for the rc32332 are latched by cold reset. cpu_dt_r_n output z ? cpu direction transmit/receive this active-low signal controls the dt/r pin of an optional fct245 transceiver bank. it is asserted during read operations. 1st alternate function: mem_245_dt_r_n. 2nd alternate function: sdram_245_dt_r_n. jtag interface signals jtag_tck input ? jtag test clock requires external pull-down. an input test clock used to shift into or out of the boundary-scan register cells. jtag_tck is independent of the system and the processor clock with nominal 50% duty cycle. jtag_tdi, ejtag_dint_n input ? jtag test data in requires an external pull-up on the board. on the rising edge of jtag_tck, serial input data are shifted into either the instruction or data register, depending on the tap controller state. during real mode, this input is used as an interrupt line to stop the debug unit from real time mode and return the debug unit back to run time mode (standard jtag). requires an external pull-up on the board. this pin is also used as the ejtag_dint_n signal in the ejtag mode. jtag_tdo, ejtag_tpc output z high jtag test data out the jtag_tdo is serial data shifted out from instruction or data register on the falling edge of jtag_tck. when no data is shifted out, the jtag_tdo is tri-stated. during real time mode, this signal provides a non- sequential program counter at the processor clock or at a division of processor clock. this pin is also used as the ejtag_tpc signal in the ejtag mode. jtag_tms input ? jtag test mode select requires external pull-up. the logic signal received at the jtag_tms input is decoded by the tap controller to control test operation. jtag_tms is sampled on the rising edge of the jtag_tck. jtag_trst_n input l ? jtag test reset when neither jtag nor ejtag are being used, jtag_trst_n must be driven or pulled low, or the jtag_tms/ ejtag_tms signals must be pulled up and jtag_clk actively clocked. ejtag_dclk output z ? ejtag test clock processor clock. during real time mode, this signal is used to capture address and data from the ejtag_tpc signal at the processor clock speed or any division of the internal pipeline. ejtag_pcst[2:0] i/o z low ejtag pc trace status information 111 (stl) pipe line stall 110 (jmp) branch/jump forms with pc output 101 (brt) branch/jump forms with no pc output 100 (exp) exception generated with an exception ve ctor code output 011 (seq) sequential performance 010 (tst) trace is outputted at pipeline stall time 001 (tsq) trace trigger output at performance time 000 (dbm) run debug mode alternate function: modebit[2:0]. ejtag_debugboot input ? ejtag debugboot requires an external pull-down. the ejtag_debugboot input is used during reset and forces the cpu core to take a debug exception at the end of the reset sequence instead of a reset exception. this enables the cpu to boot from the ice probe without having the external memory working. this input signal is level sensitive and is not latched inter- nally. this signal will also set the jtagbrk bit in the jtag_control_register[12]. name type reset state status drive strength capability description table 21.26 pin description for rc32332 (part 5 of 6) pin description table 79rc32334/332 user reference manual g - 9 june 4, 2002 ejtag_tms input ? ejtag test mode select requires an external pull-up. the ejtag_tms is sampled on the rising edge of jtag_tck. debug signals debug_cpu_dma_n i/o z low debug cpu versus dma negated assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction was generated from the cpu. de-assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction was generated from dma. alternate function: modebit[6]. debug_cpu_ack_n i/o z low debug cpu acknowledge negated indicates either a data acknowledge to the cpu or dma. alternate function: modebit[4]. debug_cpu_ads_n i/o z low debug cpu address/data strobe negated assertion indicates that either a cpu or a dma transaction is beginning and that the mem_data[31:4] bus has the current block address. alternate function: modebit[5]. debug_cpu_i_d_n i/o z low debug cpu instruction versus data negated assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is a cpu or dma data transaction. de-assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is a cpu instruction transaction. alternate function: modebit[3]. name type reset state status drive strength capability description table 21.26 pin description for rc32332 (part 6 of 6) logic diagram 79rc32334/332 user reference manual g - 10 june 4, 2002 logic diagram the logic diagram of the rc32332 di ffers from that of the rc32334. rc32332 logic symbol mem_cs_n[5:0] mem_oe_n mem_we_n[3:0] jtag_tck jtag_tms jtag_tdi mem_wait_n mem_245_oe_n jtag_tdo jtag_trst_n cpu_masterclk cpu_coldreset_n cpu core signals local system jtag cpu_int_n[1:0] cpu_dt_r_n mem_245_dt_r_n spi_mosi spi_miso spi_ss_n spi_sck sdram_addr[12] sdram_ras_n sdram_cas_n sdram_we_n output_clk uart_rx[0] uart_tx[0] debug_cpu_ack_n debug pci_ad[31:0] pci_cbe_n[3:0] pci_par pci_frame_n pci_trdy_n pci_irdy_n pci_stop_n pci_idsel pci_perr_n pci_serr_n pci_clk pci_rst_n pci_devsel_n pci_req_n[0] pci_gnt_n[0] interface pci_inta_n pci_lock_n pci_eeprom_mdi pci_eeprom_cs pci_eeprom_mdo pci_eeprom_sk dma_ready_n[0] pio[7:0] pci interface interface mem_addr[22:2] sdram_cke sdram_cs_n[3:0] sdram_bemask_n[3:0] sdram_s_n_[1:0] sdram_245_oe_n dma interface pio uart interface sdram_245_dt_r_n mem_data[31:0] cpu_nmi_n debug_cpu_dma_n debug_cpu_ads_n spi interface sdram signals ejtag_tms ejtag_debugboot ejtag_dclk ejtag_pcst[2:0] ejtag debug_cpu_i_d_n sdram_addr[15:13] sdram_addr[11:2] ejtag_tpc pci_gnt_n[2] pci_req_n[2] v cc to i/o gnd v cc i/o v ss power / ground v cc to core v cc core v cc p v ss p 79rc32334/332 user reference manual i - 1 june 4, 2002 symbols "ignore hit" in user mode..........................................................a-3 numerics 64-bit data operating requests ..................................................a-3 a address error exception ............................................................ 3-2 advisory instruction ...................................................................a-1 aligning pclock to masterclock .............................................. 19-2 b base address and base mask registers .................................. 1-22 baud rate calculation formula.................................................. 17-2 baud rate generator ....................................................... 17-1, 17-2 biu control registers ............................................................... 1-21 bta control register ................................................................. 8-9 buffer control register (bcr) ................................................ 17-8 burst period........................................................................... 12-33 bus arbitration, fixed and round r obin8-4, 8-12, 12-1, 12-21, 12-22 bus interface byte-ordering (endianness)............................................... 9-2 control registers ................................................................ 8-6 data transfer sequences (8, 16, 32-bit)............................. 9-2 variable port-widths........................................................... 9-2 bus interface unit controller................................................... 10-4 bypass instruction ................................................................ 20-8 byte-ordering conventions ........................................................ 2-3 c c bits (tlb page coherency attributes) .................................... 5-5 cache line selection algorithm................................................... 7-7 cache operation fill_i................................................................c-3 cache operations, caveats about ..............................................c-1 cache operations, number of cycles for ....................................c-1 cache ops and dwatch exception......................................... 6-9 cache parity values ................................................................. 6-10 cache write algorithms .............................................................. 7-7 computational instructions, cpu, categories of ........................ 3-3 conditional move instructions, on not zero, on zero..................a-3 conventions............................................................................... 1-1 big endian, little endian ..................................................... 1-2 bytes ................................................................................. 1-2 most and least signigicant bits.......................................... 1-2 signals............................................................................... 1-1 coprocessor 0 hazards .............................................................e-1 cp0 hazards .............................................................................e-1 cp0 registers for debug exceptions...................................... 21-22 cpu bus timeout timer.............................................................. 8-5 cpu interrupt ................................................................. 14-1, 14-2 cpu memory space 1 br.............................................. 12-5, 12-7 cpu to pci memory mapping ................................................ 12-4 d d-cache, primary.......................................................................7-3 debug breakpoint ..................................................................21-21 debug exception....................................................................21-32 debug exception return .........................................................21-22 debug operating mode ...................................................21-5, 21-7 debug registers .....................................................................21-22 debug support unit (dsu)......................................................21-6 debug support unit registers................................................21-25 diagnostic states, programming ................................................6-3 differences between rc32332 and rc32334.......................... g-1 divisor latch least register (dll) .........................................17-2 divisor latch most register (dlm) ................................17-2, 17-6 dma arbitration .......................................................................13-7 dma base descriptor register ...............................................13-5 dma control registers..............................................................1-27 dma controller..........................................................................1-5 dma fifo ...............................................................................13-8 dma transfers byte..................................................................................13-4 half-word.................................................................13-5, 13-7 quad-word .......................................................................13-5 unalighed word/burst .......................................................13-5 word.................................................................................13-5 word or burst ...................................................................13-7 dram memory controller register.........................................1-23 dsp support instructions count leading ones ........................................................... a-6 count leading zeros .......................................................... a-5 multiply add ...................................................................... a-3 multiply add unsigned....................................................... a-3 multiply subtract ............................................................... a-4 multiply subtract unsigned................................................ a-4 dual-port memory reads .........................................................10-6 dwatch exception prioritizing....................................................6-9 e ejtag pins .............................................................................21-4 ejtag specification cp0 registers for debug exceptions ..............................21-22 debug exception ............................................................21-32 debug exception return..................................................21-22 debug operating mode ...........................................21-5, 21-7 ejtag pins .....................................................................21-4 hardware breakpoints......................................................21-2 ieee 1149.1 (jtag) see ieee 1149.1 (jtag). jtag operation ...............................................................21-7 match logic ......................................................................21-4 pc trace see pc trace. registers for a debug support unit................................21-25 index index 79rc32334/332 user reference manual i - 2 june 4, 2002 software debug breakpoint............................................ 21-21 trace trigger............................................................ 21-2, 21-4 endianness configuration.......................................................... 2-3 exception addressing ...................................................................... 6-13 condition handling............................................................. 4-4 handler.............................................................................. 6-1 priority of, dwatch register .............................................. 6-9 priority order...................................................................... 6-1 exception processing kernel mode...................................................................... 6-1 user mode ........................................................................ 6-1 exception, debug .................................................................. 21-32 exl bit ...............................................................5-7, 5-9, 6-7, 6-12 expansion interrupt controller ......................................... 1-5, 14-1 interrupt flow ................................................................. 14-13 non-prioritized interrupts, optional algorithm................. 14-13 priority interrupts, optional algorithm............................. 14-13 register group settings .................................................... 14-7 registers and address mapping....................................... 14-3 signals and pins used ..................................................... 14-2 software interrupt service routine (isr) ........................ 14-13 timing diagrams..............................................................14-11 expansion interrupt registers .................................................. 1-23 f fill_i cache operation................................................................c-3 g general exception handling (har dware and software).... 6-22?6-24 general purpose timers ........................................................... 16-2 h hardware breakpoints ............................................................. 21-2 hardware, interlocks.................................................................. 3-3 hazards, coprocessor 0 ............................................................e-1 hint values and prefetch actions ...............................................a-2 i i-cache, primary ........................................................................ 7-3 ieee 1149.1 (jtag)........................20-2, 21-7, 21-8, 21-10, 21-11 in-circuit emulation.................................................................... 1-5 instruction address error exception priority.............................. 6-9 instruction cache miss ..............................................................c-1 interlock condition handling ...................................................... 4-4 internal register map addresses and definitions ..................... 1-21 interrupt controller, prioritized interrupt .................................. 17-3 interrupt cpu ................................................................. 14-1, 14-2 interrupt enable register (ier) .............................................. 17-5 interrupt flow, expansion interrupt controller........................ 14-13 interrupt identity register (iir) ............................................... 17-6 interrupt line register ............................................................. 12-32 interrupt pci............................................................................ 14-1 interrupt pin........................................................................... 12-33 interrupt service routine (isr).................................... 14-2, 14-13 ip bus timeout timer.................................................................. 8-5 iwatch exception priority........................................................... 6-9 j jtag operaton ........................................................................21-7 jtag overview ..........................................................................1-5 jtag signal descriptions jtag_tck ............................................................................20-2 jtag_tdi.............................................................................20-2 jtag_tdo............................................................................20-2 jtag_tms...........................................................................20-2 jtag_trst_n........................................................................20-2 jtag, instruction register ......................................................20-5 k kernel mode..............................................................................6-3 exception processing.........................................................6-1 kseg1.................................................................................5-9 kseg2.................................................................................5-9 kset0..................................................................................5-9 kuseg.................................................................................5-9 on-chip/ice registers ..........................................................5-9 l line control register (lcr)....................................................17-9 line status register (lsr) ..........................................17-3, 17-10 locked cache lines.....................................................................7-8 m max_lat register................................................................12-33 mem/io spaces.......................................................................10-4 memory accesses, wait-state generator ...............................10-4 memory control registers.........................................................1-23 memory controller.....................................................................1-4 memory types..........................................................................10-5 mflo and mfhi instructions ....................................................f-2 min_gnt register................................................................12-33 modem control register (mcr)..............................................17-9 modem status register (msr) ............................................. 17-11 move conditional on not zero, on zero ..................................... a-3 multiplier enhancement instructions......................................... a-3 n non-priorititized interrupts, optional algorithm .......................14-13 o opcode map............................................................................. b-1 operating modes, types of.........................................................5-8 overview ....................................................................................1-4 dma controller..................................................................1-5 expansion interrupt controller...........................................1-5 jtag .................................................................................1-5 memory controller.............................................................1-4 pci bridge .........................................................................1-5 programmable i/o (pio)....................................................1-5 sdram controller.............................................................1-4 timers/counters................................................................1-5 uart.................................................................................1-5 p page coherency attribute bits ....................................................5-5 parity ..............................................................................17-1, 17-3 pc trace index 79rc32334/332 user reference manual i - 3 june 4, 2002 examples of output........................................................ 21-37 exception followed by a jump indirect instruction.......... 21-38 indirect instruction followed by an exception................. 21-38 instruction..................................................21-6, 21-16, 21-33 instruction trace method................................................ 21-34 non-real time tpc output.............................................. 21-37 real time tpc output..................................................... 21-36 signals used.................................................................. 21-36 status information.......................................................... 21-34 status output on delay slots .......................................... 21-35 trace information ............................................................. 21-2 trigger output................................................................. 21-39 pci bridge................................................................................. 1-5 pci commands ...................................................................... 12-9 pci commands bus master enable........................................................ 12-26 fast back-to-back master enable ................................ 12-26 i/o access enable ........................................................ 12-26 memory access enable ................................................ 12-26 memory write and invalidate enable ............................ 12-26 parity error enable........................................................ 12-26 system error enable..................................................... 12-26 pci configuration 66 mhz-capable status flag........................................ 12-27 cacheline size ............................................................... 12-29 class code value register............................................. 12-28 data parity detected..................................................... 12-27 detect parity error ........................................................ 12-27 device select timing .................................................... 12-27 fast back-to-back capable status flag ....................... 12-27 master latency timer ................................................... 12-29 received master abort status ...................................... 12-27 received target abort status ....................................... 12-27 signaled system error.................................................. 12-27 signaled target abort status ........................................ 12-27 pci configuration register s in host mode.............................. 12-10 pci configuration registers in satellite mode .........................12-11 pci configuration space ...................................................... 12-24 pci interface control registers ................................................ 1-29 pci interrupt............................................................................ 14-1 pci memory space base register (br) ................................. 12-6 pci memory-space base ..................................................... 12-14 pci new feature register.................................................... 12-16 pci satellite mode .................................................................. 12-7 pci serial eeprom address fields ...................................... 12-9 pci serial eeprom, booting satellite from ............................ 12-8 pci to cpu memory mapping ................................................ 12-5 pio general purpose input mode.......................................... 15-3 general purpose output mode....................................... 15-3 peripheral function input mode...................................... 15-3 peripheral function output mode................................... 15-3 pio signal pin definitions dma interface dma_done_n ........................................................... 15-5 dma_ready_n ..........................................................15-5 timer timer_tc_n................................................................15-4 uart interface uart_rx .....................................................................15-4 uart_tx .....................................................................15-4 pipeline branch delay......................................................................4-3 stalling ...............................................................................4-4 port width interface support.......................................................9-2 powering down inactive units ................................................... d-1 prefetch instruction................................................................... a-1 prefetch operation .....................................................................4-1 primary d-cache........................................................................7-3 primary i-cache .........................................................................7-3 prioritized interrupt ..................................................................17-3 priority interrupts, optional algorithm .....................................14-13 processor cycles ................................................................................3-3 implementation number.....................................................6-7 modes programming .........................................................6-3 programmable i/o (pio)............................................................1-5 programming pclock...............................................................19-2 r rc32332, different from rc32334........................................... g-1 rc32334, different from rc32332........................................... g-1 read-only registers interrupt identity register (iir) ........................................17-6 receive buffer register (rbr) .......................................17-5 real-time clock .........................................................................16-2 receive buffer register (rbr) ...............................................17-5 receive holding register........................................................17-2 registers bad virtual address register(8)........................................5-7 base address and base mask registers...........................1-22 biu control registers........................................................1-21 boundary-scan register .................................................20-3 buffer control register (bcr).........................................17-8 bus turnaround (bta) control register............................8-8 bus-error address register ..............................................8-9 bypass register ..............................................................20-3 cache error register(27) ................................................6-10 cause register(13) ...........................................................6-5 compare register(11) .......................................................6-3 config register(16) ...........................................................6-8 context register(4) ...........................................................5-5 count register(9) ..............................................................6-2 debug exception program counter register(23)............6-10 debug register(24) .........................................................6-10 debug registers..............................................................21-22 debug support unit registers ........................................21-25 device identification register..........................................20-3 divisor latch least register (dll) .................................17-2 divisor latch most register (dlm) ........................17-2, 17-6 dma control registers......................................................1-27 index 79rc32334/332 user reference manual i - 4 june 4, 2002 dram memory controller register ................................ 1-23 dwatch register(19) ........................................................ 6-9 entryhi register(10) ......................................................... 5-8 entrylo0(2) ....................................................................... 5-4 entrylo1(3) ....................................................................... 5-4 error checking and correcting register(26)................... 6-10 error exception program c ounter register(30).............. 6-12 exception program counter register (14)........................ 6-7 expansion interrupt controller registers ......................... 14-3 expansion interrupt registers........................................... 1-23 hi and lo registers ......................................................... f-1 index register(0) .............................................................. 5-3 instruction register......................................................... 20-5 internal register map addr esses and definitions ............. 1-21 interrupt enable register (ier)....................................... 17-5 interrupt identity register (iir)........................................ 17-6 iwatch register(18) .......................................................... 6-9 line control register (lcr)............................................ 17-9 line status register (lsr) .................................. 17-3, 17-10 memory control registers ................................................ 1-23 modem control register (mcr) ..................................... 17-9 modem status register (msr)......................................17-11 pagemask register(5) ...................................................... 5-6 pci interface contro l registers......................................... 1-29 port width control register .............................................. 8-6 processor revision identifier register(15) ....................... 6-7 random register(1).......................................................... 5-4 read-only registers interrupt identity register (iir)................................ 17-6 receive buffer register (rbr) ............................... 17-5 receive buffer register (rbr) ....................................... 17-5 receive holding register ............................................... 17-2 scratch register (scr) ................................................ 17-12 status register(12)........................................................... 6-3 taglo register(28) ..........................................................6-11 test data register .......................................................... 20-3 timer controller registers ................................................. 1-25 transmit buffer register (tbr)....................................... 17-5 transmit holding register .............................................. 17-2 uart 0 ........................................................................... 17-4 uart 1 ........................................................................... 17-4 uart control registers.................................................... 1-26 wired register(6).............................................................. 5-6 write-only registers buffer control register (bcr)................................. 17-8 transmit buffer register (tbr)............................... 17-5 reinitializing, reset interface .................................................... 19-3 reset configuration options........................................................ 6-8 reset configuration settings..................................................... 19-4 reset exception servicing ........................................................ 6-15 reset sequence timing...............................................................d-1 reset vector inialization ........................................................... 19-6 retry timeout value ................................................................ 12-34 reverse endianness, programming ........................................... 6-3 revision number ........................................................................ 6-7 s satellite mode, pci .................................................................12-7 scratch register (scr).........................................................17-12 sdram 32-bit support ............................................................ 11-8 sdram bank priority scheme ................................................. 11-7 sdram base and mask registers ........................................... 11-7 sdram clock .......................................................................... 11-4 sdram controller.....................................................................1-4 sdram custom transaction .................................................... 11-8 sdram external buffers.......................................................... 11-4 sdram subblock address ordering ...................................... 11-4 serial peripheral interface (spi) ...............................................1-5 slipped instruction .....................................................................4-6 slow-to-turn-off eeproms small, medium, and large systems ..................................10-3 software debug breakpoint....................................................21-21 software generated exceptions (sw1 or sw0) .......................6-22 software interrupt service routine (isr).................................14-13 software interrupts.....................................................................6-5 spi interface signal descriptions spi_miso ..........................................................................18-2 spi_mosi ..........................................................................18-2 spi_sck ............................................................................18-2 spi_ss_n ..........................................................................18-2 status register, user mode.......................................................5-8 sysid register ........................................................................8-14 t tap controller state assignments ...........................................................21-9 state diagram...................................................................21-7 timer controller registers..........................................................1-25 timer interrupt, compare register(11).......................................6-3 timer signal definitions timer_gate_n ...................................................................16-3 timer signal definitions timer_tc_n........................................................................16-3 timers, general purpose ..........................................................16-2 timers/counters overview.........................................................1-5 time-slice clock........................................................................16-2 timing diagrams, expansion interrupt controller ................... 14-11 tlb management, attribute bits ................................................5-2 trace trigger ....................................................................21-2, 21-4 trace, pc see pc trace. transceivers and buffering small, medium, and large systems ..................................10-3 transmit buffer register (tbr)...............................................17-5 transmit holding register.......................................................17-2 trap signal................................................................................. a-3 trdy timeout value ..............................................................12-33 u uart baud rate generator.........................................................17-2 divisor value ....................................................................17-2 interrupt 0 ........................................................................17-3 receive buffer size ...........................................................17-2 index 79rc32334/332 user reference manual i - 5 june 4, 2002 transmit buffer size.......................................................... 17-2 uart 0 and 1 registers, address of ....................................... 17-1 uart 0 registers .................................................................... 17-4 uart 1 registers .................................................................... 17-4 uart control registers ........................................................... 1-26 uart overview......................................................................... 1-5 user mode ................................................................................ 6-3 exception processing ........................................................ 6-1 virtual address space........................................................ 5-8 v vector base for the cache error exception ............................. 6-14 vendor id................................................................................ 8-15 w wait instruction inactive units .....................................................................d-1 standby mode ...................................................................d-1 wait-state generator (wsg) .................................................. 10-4 wait-states dual-port accesses......................................................... 10-7 watchdog timer rollover........................................................... 8-5 wired register, writing to.......................................................... 5-7 word parity ................................................................................ 7-2 write-only registers buffer control register (bcr) ........................................ 17-8 transmit buffer register (tbr)....................................... 17-5 index 79rc32334/332 user reference manual i - 6 june 4, 2002 |
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